CN102254868A - 提供有配线插槽的芯片元件的制造方法 - Google Patents

提供有配线插槽的芯片元件的制造方法 Download PDF

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CN102254868A
CN102254868A CN2011101329578A CN201110132957A CN102254868A CN 102254868 A CN102254868 A CN 102254868A CN 2011101329578 A CN2011101329578 A CN 2011101329578A CN 201110132957 A CN201110132957 A CN 201110132957A CN 102254868 A CN102254868 A CN 102254868A
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让.布龙
多米尼克.维卡德
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Abstract

本发明公开了一种提供有配线插槽的芯片元件的制造方法，涉及由形成在晶片(20)上的器件(22)制造提供有槽(14)的芯片元件(10)的方法。该方法的步骤包括在晶片(20)上沉积牺牲膜(26)以使每个器件(22)的中心部分暴露并且覆盖该器件的边缘，在该器件的边缘处要形成槽；在牺牲膜上施加模子(28)；将可硬化材料(30)注入模子中；将该可硬化材料硬化；在器件之间切割晶片；以及去除牺牲层。

Description

提供有配线插槽的芯片元件的制造方法
技术领域
本发明涉及微电子芯片元件，其最大尺寸可以小于一毫米，该芯片元件被固定到用于例如给芯片提供电源的导电配线。
背景技术
图1表示芯片元件10的透视图，芯片元件10固定到两个平行的配线12a和12b，如专利申请WO2009112644所述。元件10大体为为平行六面体形状，其两个相对侧表面提供有各自的平行槽14a和14b，平行槽14a和14b延伸在元件10的整个长度上。这些槽的每一个都分别容放配线12a和12b之一。
配线12a和12b通常具有电连接的功能，例如，给元件10的芯片中形成的发光二极管提供电流。配线12a和12b因此导电，并且通过每个槽的侧壁上形成的导电块16与芯片电连接。槽的宽度和块16的高度根据配线12的直径选择，从而每个配线被夹在块和槽14的相对侧壁之间。
图1的类型的元件通常由两部分组成。第一部分18a对应于元件的底部三分之一，由芯片形成。第二部分18b对应于元件的其余顶部，形成保护盖。芯片的有源表面面对盖18b，包括块16且形成槽14的第一侧壁。盖18b具有T型截面，从而它能够形成槽的第二侧壁和底部。
考虑到芯片元件10体积小，在芯片18a上装配盖18b引起一定的问题。以可重复的方式恒定分开槽14侧壁的距离是特别困难的。如上述专利申请WO2009112644所述，所希望的是配线12通过在一侧的块16和另一侧的槽的相对侧壁之间弹性地夹在槽中而被固定。如果分开距离太大，则配线12不能被夹住。如果分开距离太小，则配线12不能在没有破坏元件10的情况下***槽中。
发明内容
因此，意在实现槽的侧壁之间的可重复且精确距离的方法。
为了满足这样的要求，所提供的制造方法由形成于晶片(20)上的器件(22)制造提供有槽(14)的芯片元件(10)。该方法包括步骤：在晶片(20)上沉积牺牲膜(26)，以使每个器件(22)的中心部分暴露，并且在要形成槽的位置覆盖器件的边缘；在牺牲膜上施加模子(mold)(28)；将可硬化材料(30)注入模子中；将可硬化材料硬化；切割器件之间的晶片；以及去除牺牲膜。
附图说明
其他优点和特征通过下面对本发明特定实施例的描述将更加明显易懂，这些特定实施例为了非限定示例的目的给出且表示在附图中，在附图中：
图1(前面已经描述)表示固定到两个配线的芯片元件的透视图；
图2A至2F表示方法的各个步骤，由此可以制造具有槽的芯片元件，该槽具有精确且可重复的宽度。
具体实施方式
图2A表示晶片20的局部截面图，在晶片20上已经形成成套的集成器件22，其对应于欲获得的芯片元件的芯片18a。这些器件22的每一个在其两个边缘上提供有导电块16，导电块16随后用于建立与配线12的接触。
晶片20(例如由硅制造)在该示例中已经被减薄，从而其厚度与最终芯片元件所需的尺寸相匹配。优选地，由于晶片20已经被减薄且呈现降低的刚性，所以被减薄的晶片通过其后表面固定到支撑板或者“把手(handle)”24，以给该组件以所需的刚性用于制造方法的各个步骤。通常来说，在支撑板24上的晶片20的组件必须在器件22的各个制造操作期间经受所遇到的高温。
在图2B中，牺牲膜26在晶片20的顶表面上沉积成厚层，例如100μm。该膜26由能够以半导体领域中的通常技术图案化、平坦化和去除的材料制造。该材料例如为树脂、聚酰亚胺或金属。
在下文将会看到，该膜26的厚度限定了要形成的槽14的宽度。通常的沉积技术能够实现要获得的膜的厚度的足够精度。要求精确的距离实际上是分开每个块16的顶部与槽的相对壁的距离。制造块16的技术也能实现所需的精度。
如所示的，膜26例如通过光刻被图案化，以使得器件22的中心部分被暴露，而覆盖提供有块16的边缘(设计为形成要形成的槽的第一侧壁的区域)。图案化优选为各向异性，从而膜26中的开口呈现垂直于晶片的壁，这些壁限定了要形成的槽的底部。
在图2C中，包括与器件22对应的腔体的模子28施加在膜26上。模子28的腔体与膜26中的孔一起限定了芯片元件的要形成的盖板18b的形状，例如具有T型截面的盖板。
可硬化液体30被注入模子28的每个腔体中，可硬化液体30呈现盖板所希望的特性，例如，在器件22为发光二极管的情况下为透明的环氧树脂。
图2D表示树脂30已经硬化且模子28已经移除后所获得的结果。在器件22上面，树脂30形成盖板18b，并且使得在围绕器件22的区域中膜26被暴露。
在图2E中，通过顶表面进行切割(dicing)，以分开器件22并且形成芯片18a。如所示的，切割切口(dicing cut)32穿过盖板18b之间由模子留下的空间，穿过膜26，并且开始切割晶片20而不穿透晶片20。
在图2F中，例如，通过等离子体或者化学蚀刻去除牺牲膜26的剩余部分。盖板18b限定的槽14因此在芯片18a的块16的上方被清除。
牺牲膜26的去除优选在切割后进行。通过以这样的顺序进行，防止切割的碎屑沉积在槽14中且防止影响后续的配线12和块16之间的电接触的建立。
然后进行支撑板24的移除，随后在后表面上研磨晶片20直到在切割切口底部的位置的平面P，以获得各芯片元件10。
为了保持在移除板24期间以及研磨期间晶片20的安全，盖板18b例如可压在可移除的粘合剂支撑上(未示出)。研磨后，各芯片元件10保持粘合到粘合剂支撑，然后，在晶片分割后，处于类似于传统芯片的状态下。然后，芯片元件可以通过传统的芯片处理工具使用。
根据变型，支撑板24在图2E的切割步骤前被移除，并且晶片20通过其后表面固定到可移除的粘合剂支撑。切割切口32然后穿过晶片20，并且切割进入粘合剂支撑。
为了结束芯片元件的制造，所有要做的是去除位于槽14处的牺牲膜26的残留片。这种去除优选通过与粘合剂兼容的低温方法进行，例如，通过提供可由化学蚀刻去除的金属制造的牺牲膜26。
在前述的情况下，可以使成套的单独芯片元件10粘贴到支撑上，准备通过传统的处理工具被使用。在该变型中，不是由盖板18b粘贴到支撑上，而是由芯片18a将元件粘贴。
该变型的一个优点是避免了晶片20的后表面的研磨步骤以及因研磨产生的碎屑沉积在槽14中的风险。
根据另一个选择性实施例，图2C中所示的模子不是对每个器件22均包括单独的腔体，而是具有延伸在整套器件22上的单一腔体。在此情况下，在注入且硬化树脂30后，在图2D的步骤，树脂30的层均匀地覆盖牺牲膜26。各盖板18b于是由切割切口32在图2E的步骤中形成。

Claims (5)

1.一种由形成在晶片(20)上的器件(22)制造提供有槽(14)的芯片元件(10)的方法，其特征在于包括下面的步骤：
在所述晶片(20)上沉积牺牲膜(26)，以使每个所述器件(22)的中心部分暴露并且覆盖所述器件的边缘，在所述器件的边缘处要形成所述槽；
在所述牺牲膜上施加模子(28)；
将可硬化材料(30)注入所述模子中；
将所述可硬化材料硬化；
在所述器件之间切割晶片；以及
去除所述牺牲膜。
2.根据权利要求1所述的方法，其中所述模子(28)包括与每个芯片对应的腔体。
3.根据权利要求1所述的方法，其中所述切割步骤在所述牺牲膜的去除步骤前进行。
4.根据权利要求1所述的方法，其中所述切割步骤中形成的切割切口(32)不完全穿过所述晶片(20)，所述方法还包括在所述晶片的后表面上研磨所述晶片直到到达所述切割切口的步骤。
5.根据权利要求1所述的方法，其中所述晶片(20)通过该晶片的后表面固定到支撑板(24)，所述方法包括在所述切割步骤后从所述支撑板移除所述晶片的步骤。
CN201110132957.8A 2010-05-18 2011-05-18 提供有配线插槽的芯片元件的制造方法 Expired - Fee Related CN102254868B (zh)

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Application Number Priority Date Filing Date Title
FR1002080A FR2960339B1 (fr) 2010-05-18 2010-05-18 Procede de realisation d'elements a puce munis de rainures d'insertion de fils
FR10/02080 2010-05-18

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FR2960339A1 (fr) 2011-11-25
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US8258044B2 (en) 2012-09-04
CN102254868B (zh) 2016-07-06
FR2960339B1 (fr) 2012-05-18
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JP2011240481A (ja) 2011-12-01
US20110287606A1 (en) 2011-11-24

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