CN102244518A - System and method for realizing parallel decompression of hardware - Google Patents
System and method for realizing parallel decompression of hardware Download PDFInfo
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Abstract
The invention discloses a system and method for realizing parallel decompression of hardware. The system comprises a variable-length bit manipulation module, a Huffman table recovery module, a Huffman coding module and a decoding module, wherein the variable-length bit manipulation module is used for carrying out variable-length bit manipulation on to-be-decompressed data to acquire variable-length data; the Huffman table recovery module is used for recovering a Huffman table in accordance with the variable-length data; the Huffman coding module is used for executing Huffman coding in parallel in accordance with the Huffman table; and the decoding module is used for carrying out decoding in accordance with the Huffman coding result. According to the system and method for realizing the parallel decompression of hardware, an FPGA (field programmable gate array) is utilized to realize a Gzip decompressing function, a parallel decompression algorithm is utilized and a hardware circuit structure suitable for the algorithm is designed, thus improving the processing efficiency of the decompression greatly.
Description
Technical field
The present invention relates to the data decompression technology, relate in particular to a kind of hard-wired system and method for parallel decompression.
Background technology
In the large-scale data of the Internet is handled, it is one of very important means that data are carried out compression and decompression, it can increase substantially the available capacity of disk, the effective bandwidth of input and output (I/O) when improving read-write operation, thereby effectively reduce (the IDC of Internet data center, Internet Data Center) cost improves application layer program implementation speed.
Current, the Gzip algorithm is generally adopted in the compression and decompression of data, and carries out data processing by the mode of software algorithm, and there is the bit manipulation of a large amount of serials Gzip algorithm the inside, and the efficient of using software algorithm to handle is lower.
And the algorithm that Gzip decompresses all adopts the mode of software to realize, specifically, the Gzip decompression algorithm is a kind of multistage algorithm of tabling look-up, adopt multistage mode of tabling look-up to finish Huffman (Huffman) decoding, that is to say that solving a sign indicating number may need to table look-up repeatedly, the advantage of this method is that the use amount of internal memory is less, corresponding major part is searched only need once table look-up and promptly can be finished, efficient is higher, so use extensively in the software the inside, but this algorithm degree of parallelism is lower, can take a large amount of cpu resources in large-scale data processing, is not suitable for hardware and realizes.
CPU with dominant frequency 2.66GHz is an example, and its bandwidth of compressing is 50Mb/s, and the bandwidth of decompression is 200Mb/s.In large-scale data was handled, the data flow of decompression to be compressed was huge; Therefore, must take a large amount of cpu resources when using CPU to carry out compressed and decompressed processing, the problem that cpu resource takies when carrying out data decompression is then more obvious.
Therefore, can the treatment effeciency that how to increase substantially decompression becomes the technical problem that existing Gzip decompression technique needs to be resolved hurrily, especially provide corresponding solution at existing Gzip decompression algorithm.
Summary of the invention
The technical problem that the present invention will solve provides a kind of hard-wired system and method for parallel decompression, can effectively improve the decompression efficient of existing Gzip decompression algorithm.
One aspect of the present invention provides a kind of hard-wired system of parallel decompression, and this system comprises: the bit manipulation module of random length, be used to treat the bit manipulation that decompressed data is carried out random length, and obtain the data of random length; The Huffman code table recovers module, is used for the data according to random length, recovers the Huffman code table; The Huffman decoding module is used for according to the Huffman code table executed in parallel Huffman decoding; And decoder module, be used for result according to Huffman decoding, decode.
Among the embodiment of the hard-wired system of parallel decompression provided by the invention, the bit manipulation module of random length further comprises: data merge submodule, be used for the data that decompressed data and metadata cache submodule are shifted after the operation for the treatment of that input reads are merged, generate the new decompressed data for the treatment of; MUX is used for data cached selection the according to input; If data cached less than predetermined figure place, the data strobe after so just data merging submodule being merged also is written in the metadata cache submodule; Otherwise, upgrade data in the metadata cache submodule with the data after the displacement; The metadata cache submodule is used for the new decompressed data for the treatment of of data cached merging submodule input, and to the decompressed data for the treatment of of displacement submodule output random length; The displacement submodule is used for the data that data buffer memory submodule is determined are carried out the dextroposition operation, abandoning the data that the one-period of lasting uses, and data newly-generated after the shifting function is exported to data merging submodule.
Among the embodiment of the hard-wired system of parallel decompression provided by the invention, the Huffman code table recovers module and further comprises: the code length calculating sub module, be used for data according to random length, and calculate the code length of each coded data correspondence; The code length sub module stored is used to store the code length that the code length calculating sub module calculates; The Huffman code table recovers submodule, is used for according to result calculated, adds up the number of each code length, adds up the symbol of each code length correspondence, and to after the symbol ordering, recovers the Huffman code table according to each code length.
Among the embodiment of the hard-wired system of parallel decompression provided by the invention, the Huffman decoding module further comprises: submodule is changed in the position, is used for the input data are carried out bit inversion, to restore the input data; Comparison sub-module is used for the data that the data after restore are taken out maximum code length, and does relatively parallel with the expansion initial code; Leading 1 detection sub-module is used for the comparative result according to comparison sub-module, determines that start bit is the position of " 1 ", thereby determines the actual code length of current data; Code table initial address submodule is used for obtaining as address lookup according to the actual code length that leading 1 detection sub-module is determined the initial address of the Huffman code table of actual code length correspondence; Data cutting submodule, the code length that is used for changing according to the position submodule dateout and data carries out cutting to dateout, keeps the low data of code length bit wide, obtains the Huffman data to decode.
Among the embodiment of the hard-wired system of parallel decompression provided by the invention, decoder module is selected the Lz77 decoder module for use, is used for carrying out the Lz77 decode operation according to the result of Huffman decoding.
Among the embodiment of the hard-wired system of parallel decompression provided by the invention, the Lz77 decoder module further comprises: decoding control submodule, the data result that is used for the Huffman decoding that obtains according to the Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching; The history data store submodule is used for the data of being mated according to the address storage that decoding control submodule provides; The syndrome module is used for the matched data that decoding control submodule obtains is carried out the CRC32 verification, to judge the correctness that decompresses.
Another aspect of the present invention provides a kind of hard-wired method of parallel decompression, and this method comprises: treat the bit manipulation that decompressed data is carried out random length, obtain the data of random length; According to the data of random length, recover the Huffman code table; According to the Huffman code table, the executed in parallel Huffman decoding; And, carry out the Lz77 decoding according to the result of Huffman decoding.
Among the embodiment of the hard-wired method of parallel decompression provided by the invention, treat decompressed data and carry out the bit manipulation of random length, the data of obtaining random length further comprise: the data that data are merged after the submodule input reads treat decompressed data and be shifted operation merge, and generate the new decompressed data for the treatment of; Data cached selection the according to input; If data cached less than predetermined figure place, the data strobe after so just data merging submodule being merged also is written in the metadata cache submodule; Otherwise, upgrade data in the metadata cache submodule with the data after the displacement; Buffer memory is new treats decompressed data, and the output random length treat decompressed data; And the decompressed data for the treatment of of random length carried out dextroposition operation, abandoning the data that the one-period of lasting uses, and data newly-generated after the shifting function are exported to data merging submodule.
Among the embodiment of the hard-wired method of parallel decompression provided by the invention,, recover the Huffman code table and further comprise:, calculate the code length of each coded data correspondence according to the data of random length according to the data of random length; The code length that storage computation goes out; And, add up the number of each code length according to result calculated, add up the symbol of each code length correspondence, and, recover the Huffman code table according to each code length to after the symbol ordering.
Among the embodiment of the hard-wired method of parallel decompression provided by the invention, according to the Huffman code table, the executed in parallel Huffman decoding further comprises: the input data are carried out bit inversion, to restore the input data; Take out the data of maximum code length the data after restoring, and do relatively parallel with the expansion initial code; According to the comparative result of comparison sub-module, determine that start bit is the position of " 1 ", thereby determine the actual code length of current data; Obtain the initial address of the Huffman code table of actual code length correspondence as address lookup according to the definite actual code length of leading 1 detection sub-module; The code length that changes submodule dateout and data according to the position carries out cutting to dateout, keeps the low data of code length bit wide, obtains the Huffman data to decode.
Among the embodiment of the hard-wired method of parallel decompression provided by the invention, according to the result of Huffman decoding, decoding further comprises and selects for use the Lz77 decoder module to carry out the Lz77 decode operation according to the result of Huffman decoding.
Among the embodiment of the hard-wired method of parallel decompression provided by the invention, result according to Huffman decoding, carrying out Lz77 decoding further comprises: the data result of the Huffman decoding that obtains according to the Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching; According to address storage matched data; And matched data carried out the CRC32 verification, to judge the correctness that decompresses.
The invention provides a kind of hard-wired system and method for parallel decompression, use programmable logic device (FPGA) to remove to realize the Gzip decompressing function, by adopting a kind of parallel decompression algorithm, and design is fit to the hardware circuit of this algorithm, thereby increases substantially the treatment effeciency of decompression.
Description of drawings
Fig. 1 illustrates the structural representation of the hard-wired system of a kind of parallel decompression that the embodiment of the invention provides;
Fig. 2 illustrates the structural representation of embodiment of the hard-wired system of parallel decompression provided by the invention;
Fig. 3 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention;
Fig. 4 illustrates the particular circuit configurations schematic diagram of the bit manipulation module of random length among the embodiment of hard-wired system of parallel decompression provided by the invention;
Fig. 5 illustrates the flow chart of the method for Gzip technology recovery code table in the prior art;
Fig. 6 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention;
Fig. 7 illustrates the structural representation that Huffman code table among the embodiment of hard-wired system of parallel decompression provided by the invention recovers the embodiment of module;
Fig. 8 illustrates the particular circuit configurations schematic diagram that Huffman code table among the embodiment of hard-wired system of parallel decompression provided by the invention recovers module;
Fig. 9 illustrates the structural representation of code table storage among the embodiment of hard-wired system of parallel decompression provided by the invention;
Figure 10 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention;
Figure 11 illustrates the particular circuit configurations schematic diagram of Huffman parallel decoding module among the embodiment of hard-wired system of parallel decompression provided by the invention;
Figure 12 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention;
Figure 13 illustrates the structural representation of the embodiment of Lz77 decoder module among the embodiment of hard-wired system of parallel decompression provided by the invention;
Figure 14 illustrates the particular circuit configurations schematic diagram of Lz77 decoder module among the embodiment of hard-wired system of parallel decompression provided by the invention;
Figure 15 illustrates the flow chart of the hard-wired method of a kind of parallel decompression that the embodiment of the invention provides;
Figure 16 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention;
Figure 17 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention;
Figure 18 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention;
Figure 19 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention;
Figure 20 illustrates the schematic flow sheet of a concrete application examples of hard-wired method of parallel decompression provided by the invention.
Embodiment
With exemplary embodiment of the present invention the present invention is described more fully and illustrates with reference to the accompanying drawings.
Fig. 1 illustrates the structural representation of the hard-wired system of a kind of parallel decompression that the embodiment of the invention provides.
As shown in Figure 1, a kind of hard-wired system 100 of parallel decompression comprises: the bit manipulation module 102 of random length, Huffman code table recover module 104, Huffman decoding module 106 and Lz77 decoder module 108.
Wherein, the bit manipulation module (Bitwise_management) 102 of random length is used to treat the bit manipulation that decompressed data is carried out random length, obtains the data of random length.For example, the bit manipulation module 102 of random length is used for beforely going into to go out earlier module (In_FIFO_if) and reading new data, the data of the employed data bit width of output current period, and abandon operations such as already used data, be responsible for the data bit operation of whole decompression process, realize the efficient output of random length data.
The Huffman code table recovers module (Huft_build) 104, is used for the data according to random length, recovers the Huffman code table.For example, receive the data of random length of bit manipulation module 102 outputs of random length,, and described Huffman code table is stored in the random-access memory (ram) according to the data stream recovery Huffman code table that receives.The restoration methods of Huffman code table can adopt the existing code table restoration methods in this area, also can adopt code table restoration methods provided by the invention; Relevant content can be further detailed in embodiment subsequently.
Huffman decoding module (Lookup_table) 106 is used for according to the Huffman code table executed in parallel Huffman decoding.For example, recover the Huffman code table that module 104 is recovered, carry out Huffman decoding concurrently, from input traffic, recover original huffman coded data according to the Huffman code table.
Decoder module 108 is used for the result according to Huffman decoding, decodes.For example,, adopt Lz77 decoder module (Lz77_inv) from historical data, to search corresponding matched data, export this matched data with the renewal historical data, thereby mate for subsequent decoding according to the result of Huffman decoding module decoding.
The invention provides a kind of hard-wired system of parallel decompression, design is fit to the hardware circuit of Gzip decompression algorithm, adopt the bit manipulation module of random length to realize the fast processing of the random length position of data, Huffman decoding module parallel decoding and Lz77 decoder module are decoded, thereby increase substantially the treatment effeciency of decompression.
Fig. 2 illustrates the structural representation of embodiment of the hard-wired system of parallel decompression provided by the invention.
As shown in Figure 2, a kind of hard-wired system 200 of parallel decompression comprises: the bit manipulation module 202 of random length, data head parsing module 203, Huffman code table recover module 204, static code table memory module 205, Huffman decoding module 206, dynamic code table memory module 207, Lz77 decoder module 208 and module total control module 210.
Wherein, the bit manipulation module 202 of random length is used to treat the bit manipulation that decompressed data is carried out random length, obtains the data of random length.For example, the bit manipulation module 102 of random length is used for beforely going into to go out earlier module (In_FIFO_if) and reading new data, the data of the employed data bit width of output current period, and abandon operations such as already used data, be responsible for the data bit operation of whole decompression process, realize the efficient output of random length data.
Data head parsing module (Parse_data) 203, be used for reading and treat decompressed data from the bit manipulation module 202 of random length, resolve its packed data head, the global information that extracts from the head of compression blocks is (as compression type, whether be last data block etc.), one of control signal when the information that parses can send to module master control unit 210 as other module executable operations (dotted line is represented control signal among Fig. 2, and solid line represents that data-signal flows to).
The Huffman code table recovers module 204, is used for the data according to random length, recovers the Huffman code table.For example, the data of the random length of bit manipulation module 202 outputs of Huffman code table recovery module 204 reception random lengths, according to the data stream recovery Huffman code table that receives, and described Huffman code table is stored in the dynamic code table memory module (Dynamic_table) 207.The restoration methods of Huffman code table can adopt the existing code table restoration methods in this area, also can adopt code table restoration methods provided by the invention; Relevant content can be further detailed in embodiment subsequently.
Huffman decoding module 206 is used for according to the Huffman code table executed in parallel Huffman decoding.For example, recover the Huffman code table that module 104 is recovered according to the Huffman code table, as the code table type, the static table or the dynamic table of storage in queries static code table memory module 205 or the dynamic code table memory module 207, carry out Huffman decoding concurrently, from input traffic, recover original huffman coded data.
Static code table memory module (Statics_table) 205 and dynamic code table memory module (Dynamic_table) 207 are used for to storing static table or the dynamic table that Huffman decoding module 206 provides inquiry; Wherein static table is fixed, and is stored in the ROM the inside; Dynamic table is dynamically to generate, and is stored in the RAM the inside.Code table data during the corresponding static Hafman decoding of static code table are changeless, and the ROM the inside of programming in sheet if current data block adopts is the static coding mode, is then stored Huffman decoding module 206 and inquired about from static code table reading of data.Dynamic code table is to generate according to the coded message of current data block is dynamic, for each compression blocks, the Huffman code table recovers module 204 and generates corresponding dynamic code table, write dynamic code table memory module 207, storage Huffman decoding module 206 reads out from dynamic code table memory module 207 again during decoding.
Module total control module (Ctrl_unit) 210, be used for receiving global information that data head parsing module 203 parses control signal as other module, and to bit manipulation module 202, the data head parsing module 203 of random length, the Huffman code table recovers module 204, Huffman decoding module 206, Lz77 decoder module 208 and module total control module 210 that the control signal of carrying out the corresponding operating flow process is provided.
The hard-wired system of parallel decompression provided by the invention, carry out the bit manipulation of a large amount of random lengths by the mode of hardware structure, but carry out the parallel decoding operation, thereby in one-period, finish the algorithm of a Hafman decoding, have higher decoding efficiency.
In the overall process that Gzip decompresses, relate to the resolution data head, recover the Huffman code table, initial data is carried out operations such as Huffman decoding, the data that all need to take out random length the regular data flow (as 32 fixed-length data streams) from input are handled.The difficult point of random length bit manipulation is treatment effeciency, promptly will calculate this used data bit width in cycle the inside in current period, then last one-period is abandoned with the data of crossing, and takes out new data again and handles.For addressing the above problem, the present invention subsequently will provide a kind of bit manipulation module of random length of overall importance to handle random length bit manipulations all in the decompression process.
Fig. 3 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention.
As shown in Figure 3, a kind of hard-wired system 300 of parallel decompression comprises: the bit manipulation module 302 of random length, data head parsing module 303, Huffman code table recover module 304, static code table memory module 305, Huffman decoding module 306, dynamic code table memory module 307, Lz77 decoder module 308 and module total control module 310; Wherein the data head parsing module 303, the Huffman code table recovers module 304, static code table memory module 305, Huffman decoding module 306, dynamic code table memory module 307, Lz77 decoder module 308 and module total control module 310 can have respectively and data head parsing module 203 shown in Figure 2, the Huffman code table recovers module 204, static code table memory module 205, Huffman decoding module 206, dynamic code table memory module 207, Lz77 decoder module 208 and module total control module 210 have same or analogous structure, for for purpose of brevity, repeat no more its technology contents here.
As shown in Figure 3, the bit manipulation module 302 of random length further comprises: data merge submodule 3020, metadata cache submodule 3022 and displacement submodule 3024.
Wherein, data merge submodule 3020, are used for the data that decompressed data and metadata cache submodule 3020 are shifted after the operation for the treatment of that input reads are merged, and generate the new decompressed data for the treatment of.For example, data merge the data of being left after submodule 3020 reads input 32 data to be decompressed and is shifted the submodule shifting function and carry out the data merging, and decompressed data is to upgrade data in buffer in the metadata cache submodule thereby generate new treating.
For solveing the technical problem, the present invention has also carried out the hypostazation of circuit structure to the module of described functionalization when the efficient hardware framework is provided.The present invention subsequently will provide the circuit structure of each hardware structure correspondence.
Fig. 4 illustrates the particular circuit configurations schematic diagram of the bit manipulation module of random length among the embodiment of hard-wired system of parallel decompression provided by the invention.
As shown in Figure 4, the microstructure of the bit manipulation module 400 of random length mainly comprises: data merge cells 402, MUX 404, data buffer storage unit 406 and shift unit 408.Specifically, bit manipulation module 400 inputs of random length read regular input data (as 32 input data), the data cached current period that is chosen in that MUX 404 is used for according to input is the remaining data of a buffer memory, or the data after buffer memory remaining data and the new data merging; Specifically, if for example data in buffer is less than 64-bit, the data strobe after just data merge cells 402 being merged also is written to buffer memory, otherwise just the Data Update after the displacement is arrived data buffer storage unit 406, uses when being shifted as next time; Data buffer storage unit 406 (as the metadata cache of 96 d type flip flops formations) is used for the data of buffer memory MUX 404 inputs, data after data merge cells 402 will be imported data and shift unit 408 and move to right combine, be input in the data buffer storage unit 406 via MUX 404 then, valid data in data buffer storage unit 406 are less than 64, then the bit manipulation module 400 of random length will be read in new data from the outside, carries out data at data merge cells 402 and merges the data of upgrading 406 li of data buffer storage units afterwards.The bit wide (importing the side-play amount of displacement unit 408 as shown in Figure 4) of the random length data that the displacement unit 408 of the bit manipulation module 400 of random length used in last one-period according to other module, data in the data buffer unit 406 are carried out the dextroposition operation, thereby used data are abandoned, and new random length data (are outputed to corresponding module as 1～16bit), thereby realize that data shift upgrades the back remaining data are being kept in the data buffer storage unit 406.
The hard-wired system of parallel decompression provided by the invention, realize the random length bit manipulation module of the overall situation by data merge cells and shift unit, simplified design greatly, all modules have been avoided the expense on data consistency is safeguarded all from this module reading of data.
The Gzip technology is recovered the content that the method for Huffman code table mainly is the Huffman code table that extraction was encoded from input traffic in the prior art, then described content encoded is deciphered, and recovers corresponding code table again.In the Gzip compress technique, what use is standard Huffman coding method, the code length that only need know the leaf node of Huffman tree just can recover whole code table, so also just the code length of each list item of code table has been write packed data stream the inside in coding stage, in order to improve compression ratio, code length has been done run length coding, and the result after the run length coding has been done the Huffman coding one time.
Purpose of the present invention will realize the Gzip decoding exactly, in view of the coding of Gzip is fixed, therefore, the decompression that the present invention provides also must be carried out code table recovery and decoding according to fixing flow process, i.e. the present invention adopts and the existing identical flow process of method of recovering code table.The Gzip technology is recovered the method for code table in the subsequent introduction prior art.
Fig. 5 illustrates the flow chart of the method for Gzip technology recovery code table in the prior art.
As shown in Figure 5, flow process 500 comprises step 502, takes out the code length of bltree table from data flow.Step 504 is set up the bltree table according to the code length of the aforementioned bltree table that obtains.Step 506 is looked into the bltree table respectively, carries out distance of swimming long decode, obtains the code length of ltree table and dtree table.Step 508 is set up the ltree table.Step 510 is set up the dtree table.In the process that Gzip decompresses, need from packed data stream, recover three Huffman code tables, comprise bltree table, ltree table and dtree table.Since Gzip coding stage with regard to pre-specified respective coding mode, therefore, wherein the code length of bltree table is directly to extract from the data flow of importing; When recovering two other code table (ltree table and dtree table), the bltree table that needs inquiry earlier to recover is carried out distance of swimming long decode then, so just can obtain each code length of ltree table and dtree table.
The flow process of the recovery Huffman code table that adopts in view of the present invention is a flow process same as the prior art, therefore, no longer does concrete expansion; Those skilled in the art can know the technology that whole recovery Huffman code table process is adopted according to the instruction of explanation of the present invention and prior art.
Fig. 6 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention.
As shown in Figure 6, a kind of hard-wired system 600 of parallel decompression comprises: the bit manipulation module 602 of random length, data head parsing module 603, Huffman code table recover module 604, static code table memory module 605, Huffman decoding module 606, dynamic code table memory module 607, Lz77 decoder module 608 and module total control module 610; The bit manipulation module 602 of random length wherein, data head parsing module 603, static code table memory module 605, Huffman decoding module 606, dynamic code table memory module 607, Lz77 decoder module 608 and module total control module 610 can have the bit manipulation module 202 with random length shown in Figure 2 respectively, data head parsing module 203, static code table memory module 205, Huffman decoding module 206, dynamic code table memory module 207, Lz77 decoder module 208 and module total control module 210 have same or analogous structure, for for purpose of brevity, repeat no more its technology contents here.
As shown in Figure 6, Huffman code table recovery module 604 further comprises: code length calculating sub module 6040, code length sub module stored 6042 and Huffman code table recover submodule 6044.
Wherein, code length calculating sub module 6040 is used for the data according to random length, calculates and recovers the needed code length of Huffman code table.Specifically, the code length of bltree is through run length coding, only need carry out distance of swimming long decode to the bltree data of packed data stream the inside, just can obtain bltree fully, the code length of ltree and dtree is to encode through the code table of bltree, so will recover ltree and dtree from packed data stream the inside, the Hafman decoding of process and the data discussed later is similar, repeats no more here.
Code length sub module stored 6042 is used to store the code length that the code length calculating sub module calculates.
The Huffman code table recovers submodule 6044, is used for according to result calculated, adds up the number of each code length, adds up the symbol of each code length correspondence, and to after the symbol ordering, recovers the Huffman code table according to each code length.In the prior art, Huffman encoding has 316 symbols (symbol) needs coding, comprise 256 original characters (literal), 30 length (length) and 30 distances (distance), each symbol code length is different, what will do here is to set up a table (table) to each code length, and that store the inside is corresponding symbol.
The hard-wired system of parallel decompression provided by the invention, recover module by the Huffman code table, can be implemented in and handle input data in the one-period, realization recovers three Huffman code tables and distance of swimming long decode is handled, thereby reaches the treatment effeciency maximization.
Fig. 7 illustrates the structural representation that Huffman code table among the embodiment of hard-wired system of parallel decompression provided by the invention recovers the embodiment of module.
As shown in Figure 7, the Huffman code table recovers in the structured flowchart of module 700, code length calculating sub module (Calc_code_len) 702 is calculated the code length of each coded data correspondence, show needed code length to be used to recovering three Huffman, the code length that calculates can be written to the RAM the inside of code length sub module stored (Len_ram) 704; The code length of bltree table directly extracts from input traffic, and the code length of ltree table and dtree table need be searched the bltree table according to the random length data in the input code flow, then the data of the gained of tabling look-up is finished distance of swimming long decode.Recover submodule (Build_table) 706 by the Huffman code table and begin to recover code table according to code length.Finite state machine (FSM, Finite State Module) 708 is used to control the processing sequence of whole Huffman code table recovery process code length calculating sub module 702, code length sub module stored 704, Huffman code table recovery submodule 706.
Huffman code table provided by the invention recovers in the embodiment of module, code length calculating sub module 702 is at first added up the number of each code length, the actual symbol that adds up the representative of each code length then (for instance, if code length is 5, character a, b, c coding code length all are 5 coding time so, and corresponding code length is that 5 symbol comprises character a, b, c), and the symbol ordering deposited, set up a table at last each code length, the content of list item is corresponding symbol.Adopt this mode, recovering code table only needs 2 code length sub module stored 704 of traversal earlier, sets up corresponding table then.Those skilled in the art can be clear that, consuming time under the worst case is 3 times of list item maximum number, that is: maximum ltree table maximum has 286 list items, maximumly even in this case consuming timely also are no more than for 900 cycles.
Fig. 8 illustrates the particular circuit configurations schematic diagram that Huffman code table among the embodiment of hard-wired system of parallel decompression provided by the invention recovers module.
Huffman code table recovery process mainly contains 4 steps, and the first step is finished the statistics of each code length occurrence number, second step finish each code length of statistics for symbol, and write RAM the inside in order, third and fourth step was set up corresponding table to each code length.Fig. 8 has provided the Huffman code table respectively and has recovered the circuit micro-structural that module realizes above-mentioned four step correspondences.As shown in Figure 8, register file (Len_cnt_rft) 802 is used for the code length of each packed data correspondence of receiving compressed data stream the inside, and writes down the statistical information of code length.Register file (Start_offset_rf) 804 is used for writing down the offset address of code length at code table.Random access memory (Symbol_ram) 806: the memory of the code length of record character and correspondence.Code length-number store (Length_num) 808 is used to store the symbol number of each code length correspondence; As code length 5, to 3 symbol should be arranged, " length_num " of that code length 5 is exactly 3.Initial code memory (Base_code) 810, initial code when being used for the storage standards Huffman encoding and sign indicating number number, the code table that supplies to calculate and recover the code length correspondence is (because in the huffman coding, the sign indicating number size of same code length increases progressively, as long as so known the number of initial code and sign indicating number, just can calculate all sign indicating numbers).Cplens/cpdist memory 814, wherein Cplens (Copy lengthsfor literal codes 257..285) be used for the storage " 257～285 " these 28 symbol for coupling base length, Cpdist (Copy offsets for distance codes 0..29), the cardinal distance that is used for " 0～29 " these 30 distance symbol correspondences from.Top Cplens/cpdist and Cplext/cpdext belong to the matching length of Gzip the inside regulation and the method for expressing of distance, promptly adopt basic length/distance (as symbol) and extra bits (extra bit) to form.Can represent more length (length) and distance (distance) like this with less symbol.(Calc table entry) 816 is used for calculating its corresponding extra position information (extra) according to the character that decoding is come out, and can realize by the mode of looking into Cplens/cpdist and Cplext/cpdext table.
Fig. 9 illustrates the structural representation of code table storage among the embodiment of hard-wired system of parallel decompression provided by the invention.
After three Huffman code tables are built up, need store to provide efficiently according to certain mode and search.The mode of the memory layout-design (memory layout) that the present invention adopts is stored symbol and extra information.As shown in Figure 9, code table information adopts the layout-design mode of close-coupled, does not waste memory space.In order to search fast, the initial address of each table can be kept at the register the inside; In view of all setting up a form for each code length, maximum 15 of each code length, therefore, each sign indicating number has 15 tables at most, that is to say that 15 registers of common needs (as Len1 index, Len2 index......Len15 index) write down the initial address of each table.In the RAM memory, the bit wide of each list item is 13-bit, and wherein low 9-bit represents the symbol value, and high 4-bit represents the extra value.Just obtain the result that all need by one query, thereby guarantee to provide the fastest search operation with the storage resources of minimum to described memory.
Figure 10 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention.
As shown in figure 10, a kind of hard-wired system 1000 of parallel decompression comprises: the bit manipulation module 1002 of random length, data head parsing module 1003, Huffman code table recover module 1004, static code table memory module 1005, Huffman decoding module 1006, dynamic code table memory module 1007, Lz77 decoder module 1008 and module total control module 1010; The bit manipulation module 1002 of random length wherein, data head parsing module 1003, the Huffman code table recovers module 1004, static code table memory module 1005, dynamic code table memory module 1007, Lz77 decoder module 1008 and module total control module 1010 can have the bit manipulation module 202 with random length shown in Figure 2 respectively, data head parsing module 203, the Huffman code table recovers module 204, static code table memory module 205, dynamic code table memory module 207, Lz77 decoder module 208 and module total control module 210 have same or analogous structure, for for purpose of brevity, repeat no more its technology contents here.
As shown in figure 10, Huffman decoding module 1006 further comprises: submodule 10060, comparison sub-module 10062, leading 1 detection sub-module 10064, code table initial address submodule 10066 and data cutting submodule 10068 are changed in the position.
Wherein, submodule 10060 is changed in the position, is used for the input data are carried out bit inversion, to restore the input data.
Leading 1 detection sub-module 10064 is used for the comparative result according to comparison sub-module, determines that start bit is the position of " 1 ", thereby determines the actual code length of current data.
Code table initial address submodule 10066 is used for obtaining initial code/base address actual code length correspondence, in symbol table (base code) according to the actual code length that leading 1 detection sub-module is determined as address lookup.
Data cutting submodule 10068, the code length that is used for the input data that obtain according to code table initial address submodule carries out cutting to the input data, keeps the low data of code length bit wide, obtains the Huffman data to decode.For example, use data to decode to be less than the low level of its code length bit wide initial address corresponding together, inquire about corresponding table, can obtain the data behind the decompress(ion) in symbol RAM the inside with its code length.
Figure 11 illustrates the particular circuit configurations schematic diagram of Huffman parallel decoding module among the embodiment of hard-wired system of parallel decompression provided by the invention.
As shown in figure 11, the circuit micro-structural 1100 of Huffman parallel decoding module comprises among the hard-wired system of parallel decompression provided by the invention embodiment: unit (Bit_rev) 1102 is changed in the position, the register of storing the initial code (base code) that is extended to fixed length is (as Base_code_extend 1, Base_code_extend 2......Base_code_extend 15) 1104, leading 1 detecting unit (Leading one detect) 1106, code table initial address register file (Index_rf) 1108, cut out random length data cell (Truncate) 1110 from fixed-length data, table (table 1～15) 1112 is stored coding and each coding corresponding characters of identical code length respectively.
The Huffman coding belongs to indefinite long code, before finishing actual decoding and do not know effective bit wide of the current data that will decipher, therefore the circuit micro-structural 1100 of Huffman parallel decoding module provided by the invention is taken out the data of maximum code length (as 15-bit) at every turn from input traffic, and the position is changed unit 1102 it is carried out bit inversion; For instance, the bit inversion of input data is the 1st and the 15th exchange of 15-bit data of input, the 2nd and the 14th exchange ..., and the like, doing like this is that data have been done same inversion when compressing, and need restore data.
After original input data carried out bit inversion, the data that obtain restoring were done the expansion initial code (Base code extended) of 15 code lengths of storage in this restored data and the register 1104 relatively parallel, and result relatively is the data of 15-bit.The initial code of expansion is the initial code of each code length to be carried out the expansion of 15-bit, extended method is the 15-bit that moves left to initial code, low level mends 0, if the maximum code length less than 15 of current Huffman code table, then the expansion initial code assignment greater than maximum code length becomes 0x3fff.
After parallel the comparison, leading 1 detecting unit 1106 detects result data relatively, determining to begin most is that bit position of 1, this position has represented that the actual code length of current data (judges promptly these input data drop on which interval of extended code, can judge effective bit wide of present input data like this, just code length).
Use this code length as address lookup code table initial address register file (Index_rf) 1108 subsequently, obtain the initial address of corresponding code length for table.Meanwhile, concerning the input data that obtain code length, also need these input data are carried out cutting, just cut out random length data cell 1110 from fixed-length data an invalid high position is removed, keep the low data of code length bit wide, these data are the Huffman coded data.So far obtain Huffman sign indicating number and code length thereof, also had the initial address of the table of its code length correspondence.The difference of the initial code of use Huffman sign indicating number and corresponding code length can inquire the symbol and the extra bit wide thereof of this Huffman sign indicating number correspondence as the table bias internal of the table of this code length correspondence.
The circuit micro-structural of Huffman parallel decoding module has realized complete parallel Huffman decoding among the embodiment of the hard-wired system of parallel decompression provided by the invention, can be in one-period the inside concurrently finish searching of a plurality of tables (maximum 15), calculate the code length of present input data and inquire its corresponding symbol; Guarantee that aforementioned decode procedure finishes in one-period.
Figure 12 illustrates the structural representation of another embodiment of the hard-wired system of parallel decompression provided by the invention.
As shown in figure 12, a kind of hard-wired system 1200 of parallel decompression comprises: the bit manipulation module 1202 of random length, data head parsing module 1203, Huffman code table recover module 1204, static code table memory module 1205, Huffman decoding module 1206, dynamic code table memory module 1207, Lz77 decoder module 1208 and module total control module 1210; The bit manipulation module 1202 of random length wherein, data head parsing module 1203, the Huffman code table recovers module 1204, static code table memory module 1205, Huffman decoding module 1206, dynamic code table memory module 1207 and module total control module 1210 can have the bit manipulation module 202 with random length shown in Figure 2 respectively, data head parsing module 203, the Huffman code table recovers module 204, static code table memory module 205, Huffman decoding module 206, dynamic code table memory module 207 and module total control module 210 have same or analogous structure, for for purpose of brevity, repeat no more its technology contents here.
As shown in figure 12, Lz77 decoder module 1208 further comprises: decoding control submodule 12080, history data store submodule 12082 and syndrome module 12084.
Wherein, decoding control submodule 12080, the data result that is used for the Huffman decoding that obtains according to the Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching.
The address storage matched data that provides according to decoding control submodule is provided history data store submodule 12082.
The processing of Lz77 decode procedure mainly is the result according to Huffman parallel decoding module decoding, searches corresponding matched data from the historical data window, exports then and upgrades this data segment in history window, and the result is mated use for subsequent decoding.Therefore, the treatment effeciency of this part directly affects the efficient of decompress(ion).
Figure 13 illustrates the structural representation of the embodiment of Lz77 decoder module among the embodiment of hard-wired system of parallel decompression provided by the invention.
As shown in figure 13, Lz77 decoder module 1300 comprises: lz77 decoding control unit (Lz77_ctrl) 1302, historical data windows units (RAM) 1304, CRC32 verification unit (CRC32) 1306 and dateout buffer memory (OUT_FIFO) 1308.
Lz77 decoding control unit 1302 character (decode results) that compiling is come out according to Huffman decoding module (Lookup_table) generates the address of reading or write historical data windows units (RAM) 1304, finishes the matching treatment of data; In addition, state informations such as the CRC32 verification of 1302 pairs of data of lz77 decoding control unit, output are controlled.
Adopt the dual port RAM (32Kbyte Dual port RAM) of 32Kb as historical data windows units (RAM) 1304 among the present invention, be used for providing matched data memory space (comprise directly matched data is write the current address, perhaps behind corresponding address reading data, write in the current address again) to lz77 decoding control unit 1302.
The present invention realizes having designed a kind of data stream type processing structure of Lz77 decoder module on the basis of complexity and treatment effeciency taking into account circuit, make decompressed data weekly the phase output is all arranged, do not have bandwidth loss.
Figure 14 illustrates the particular circuit configurations schematic diagram of Lz77 decoder module among the embodiment of hard-wired system of parallel decompression provided by the invention.
As shown in figure 14, the particular circuit configurations 1400 of Lz77 decoder module at first reads the decode results data from the first-in first-out interface (FIFO) of Huffman decoding module, judge that the data of reading into are original character (literal), or length/distance (length/distance).If literal, then these data are sent to the write data port of RAM, upgrade correlation behavior information simultaneously; If length/distance then needs first calculated address side-play amount index, from corresponding address reading of data, be then written in the current address then, repeat this process and finish up to current matching length.Continue to read the Huffman decode results, repeat above-mentioned processing procedure, decompress up to whole file and finish.
The data implication of the I/O of the d type flip flop shown in Figure 14 has explanation on the line of its Q end, the input or from adder, adder one is brought in the output from d type flip flop, and an end is 1 or address deviant, and representative adds one or add address deviant to the content of d type flip flop the inside.
Those skilled in the art can be clear that from above-mentioned Lz77 decoding process, in order to guarantee to remain stream mode in Lz77 decode procedure the inside data processing, need the efficient storage management of historical character string window, promptly to realize efficient processing to data flow, it mainly is the complete pipelining that will guarantee in the data handling procedure, and to the efficient management of RAM read/write address, promptly efficiently handle RAW (Read After Write) and take a risk, be unlikely to cause pipeline stall because take a risk.This is because the write operation of RAM wants 2 cycles (cycle) just can come into force, if also need to read data to be written in these two cycle, then can cause RAW to take a risk; Therefore need do particular processing to this situation.For example, when the data result that reads in be length/distance coupling to the time, if RAM reads the difference of write address in address and last cycle greater than 2, be that data to be read have been kept in the ram window, can read length data continuously with pipeline system, and be written in the corresponding ram window and go; If RAM reads the difference of write address in address and last cycle smaller or equal to 2, be that data to be read also do not write among the RAM of this address, then need when writing RAM, to be temporary in the data of last one-period in the register, when writing RAM at every turn from register sense data, to eliminate the inherent delay of RAM itself, improve data-handling efficiency.
Figure 15 illustrates the flow chart of the hard-wired method of a kind of parallel decompression that the embodiment of the invention provides.
As shown in figure 15, a kind of hard-wired method flow 1500 of parallel decompression comprises step 1502, treats the bit manipulation that decompressed data is carried out random length, obtains the data of random length.For example, the bit manipulation module 102 of random length is used for beforely going into to go out earlier module (In_FIFO_if) and reading new data, the data of the employed data bit width of output current period, and abandon operations such as already used data, be responsible for the data bit operation of whole decompression process, realize the efficient output of random length data.
The hard-wired method of parallel decompression provided by the invention, carry out the bit manipulation of a large amount of random lengths by the mode of hardware structure, but carry out the parallel decoding operation, thereby in one-period, finish the algorithm of a Hafman decoding, have higher decoding efficiency.
Figure 16 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention.
As shown in figure 16, the hard-wired method flow 1600 of parallel decompression comprises: step 16020～16023,1604,1606 and 1608, wherein step 1604,1606 and 1608 can be carried out respectively and step 1504 shown in Figure 15,1506 and 1508 same or analogous technology contents, for for purpose of brevity, repeat no more its technology contents here.
The hard-wired method of parallel decompression provided by the invention, realize the random length bit manipulation module of the overall situation by data merge cells and shift unit, simplified design greatly, all modules have been avoided the expense on data consistency is safeguarded all from this module reading of data.
Figure 17 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention.
As shown in figure 17, the hard-wired method flow 1700 of parallel decompression comprises: step 1702～1706 and 1708, wherein step 1702,1706 and 1708 can be carried out respectively and step 1502 shown in Figure 15,1506 and 1508 same or analogous technology contents, for for purpose of brevity, repeat no more its technology contents here.
The code length that step 1704, storage computation go out.For example, the code length that calculates can be write the RAM the inside of code length sub module stored (Len_ram); Wherein, the code length of bltree table directly extracts from input traffic, and the code length of ltree table and dtree table need be searched the bltree table according to the random length data in the input code flow, then the data of the gained of tabling look-up is finished distance of swimming long decode.
The hard-wired method of parallel decompression provided by the invention, even under worst case, consuming time is 3 times of list item maximum number, that is: maximum ltree table maximum has 286 list items, even so maximumly consuming timely also is no more than for 900 cycles.
Figure 18 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention.
As shown in figure 18, the hard-wired method flow 1800 of parallel decompression comprises: step 1802,1804,18061～18065 and 1808, wherein step 1802,1804 and 1808 can be carried out respectively and step 1502 shown in Figure 15,1504 and 1508 same or analogous technology contents, for for purpose of brevity, repeat no more its technology contents here.
Step 18060 is carried out bit inversion to the input data, to restore the input data.For example, take out the data of maximum code length (as 15-bit) from input traffic, the position is changed the unit it is carried out bit inversion at every turn; Specifically, the bit inversion of input data is the 1st and the 15th exchange of 15-bit data of input, the 2nd and the 14th exchange ..., and the like, doing like this is that data have been done same inversion when compressing, and need restore data.
Step 18061, the data of taking out maximum code length the data after restoring, and do relatively parallel with the expansion initial code.For example, the expansion initial code (Base code extended) of 15 code lengths storing in aforementioned restored data that obtains and the register is done relatively parallel, result relatively is the data of 15-bit.The initial code of expansion is the initial code of each code length to be carried out the expansion of 15-bit, extended method is the 15-bit that moves left to initial code, low level mends 0, if the maximum code length less than 15 of current Huffman code table, then the expansion initial code assignment greater than maximum code length becomes 0x3fff.
Step 18062 according to the comparative result of comparison sub-module, determines that start bit is the position of " 1 ", thereby determines the actual code length of current data.For example, after parallel the comparison, leading 1 detecting unit detects result data relatively, determining to begin most is that bit position of 1, this position has represented that the actual code length of current data (judges promptly these input data drop on which interval of extended code, can judge effective bit wide of present input data like this, just code length).
Step 18063, the actual code length of determining according to leading 1 detection sub-module obtains the code length of the input data of actual code length correspondence as address lookup.For example, use the aforementioned code length that obtains, obtain the initial address of corresponding code length for table as address lookup code table initial address register file (Index_rf).
Step 18064, the code length of the input data that obtain according to code table initial address submodule carries out cutting to the input data, keeps the low data of code length bit wide, obtains the Huffman decoding data.For example, also need these input data are carried out cutting concerning the input data that obtain code length, just cut out the random length data cell from fixed-length data an invalid high position is removed, keep the low data of code length bit wide, these data are the Huffman coded data.
So far obtain Huffman sign indicating number and code length thereof, also had the initial address of the table of its code length correspondence.The difference of the initial code of use Huffman sign indicating number and corresponding code length can inquire the symbol and the extra bit wide thereof of this Huffman sign indicating number correspondence as the table bias internal of the table of this code length correspondence.
Figure 19 illustrates the flow chart of another embodiment of the hard-wired method of parallel decompression provided by the invention.
As shown in figure 19, the hard-wired method flow 1900 of parallel decompression comprises: step 1902,1904,1906 and 1908～1910, wherein step 1902,1904 and 1906 can be carried out respectively and step 1502 shown in Figure 15,1504 and 1506 same or analogous technology contents, for for purpose of brevity, repeat no more its technology contents here.
The hard-wired method of parallel decompression provided by the invention, on the basis of taking into account circuit realization complexity and treatment effeciency, designed a kind of data stream type of Lz77 decoder module and handled structure, make decompressed data weekly the phase output is all arranged, do not have bandwidth loss.
Figure 20 illustrates the schematic flow sheet of a concrete application examples of hard-wired method of parallel decompression provided by the invention.
As shown in figure 20, a kind of hard-wired method flow 2000 of parallel decompression comprises step 2002, and the data that data are merged after the submodule input reads treat decompressed data and be shifted operation merge, and generate the new decompressed data for the treatment of.For example, data merge the data of being left after submodule reads input 32 data to be decompressed and is shifted the submodule shifting function and carry out the data merging, and decompressed data is to upgrade data in buffer in the metadata cache submodule thereby generate new treating.
Step 2004, buffer memory is new treats decompressed data, and the output random length treat decompressed data.For example, the metadata cache submodule receives and the data of 96 of buffer memorys, exports one 64 data at current period.
Step 2006 is carried out dextroposition operation to the decompressed data for the treatment of of random length, abandoning the data that the one-period of lasting uses, and data newly-generated after the shifting function is exported to data merging submodule.For example, the submodule that is shifted need carry out the dextroposition operation to the data of current cache in the data cache sub-module, abandons 64 bit data of one-period output, and remaining 32 bit data are returned to data merging submodule; If after the data shift right operation according to the output of last one-period, remaining data then need not return data merging submodule and carry out the data union operation greater than certain length (as 64).
Step 2008 according to the data of random length, is calculated the code length of each coded data correspondence.For example, according to the data of the random length of the bit manipulation module of random length output, the code length that calculates each coded data correspondence is used to recover three Huffman tables.
The code length that step 2010, storage computation go out.For example, the code length that calculates can be write the RAM the inside of code length sub module stored (Len_ram); Wherein, the code length of bltree table directly extracts from input traffic, and the code length of ltree table and dtree table need be searched the bltree table according to the random length data in the input code flow, then the data of the gained of tabling look-up is finished distance of swimming long decode.
Step 2012 according to result calculated, is added up the number of each code length, adds up the symbol of each code length correspondence, and to after the symbol ordering, recovers the Huffman code table according to each code length.For example, the code length calculating sub module is at first added up the number of each code length, the actual symbol that adds up the representative of each code length then (for instance, if code length is 5, character a, b, c coding code length all are 5 coding time so, and corresponding code length is that 5 symbol comprises character a, b, c), and the symbol ordering deposited, set up a table at last each code length, the content of list item is corresponding symbol.Adopt this mode, recovering code table only needs 2 code length sub module stored 704 of traversal earlier, sets up corresponding bltree table, ltree table and dtree table then.
Step 2014 is carried out bit inversion to the input data, to restore the input data.For example, take out the data of maximum code length (as 15-bit) from input traffic, the position is changed the unit it is carried out bit inversion at every turn; Specifically, the bit inversion of input data is the 1st and the 15th exchange of 15-bit data of input, the 2nd and the 14th exchange ..., and the like, doing like this is that data have been done same inversion when compressing, and need restore data.
Step 2016, the data of taking out maximum code length the data after restoring, and do relatively parallel with the expansion initial code.For example, the expansion initial code (Base code extended) of 15 code lengths storing in aforementioned restored data that obtains and the register is done relatively parallel, result relatively is the data of 15-bit.The initial code of expansion is the initial code of each code length to be carried out the expansion of 15-bit, extended method is the 15-bit that moves left to initial code, low level mends 0, if the maximum code length less than 15 of current Huffman code table, then the expansion initial code assignment greater than maximum code length becomes 0x3fff.
Step 2018 according to the comparative result of comparison sub-module, determines that start bit is the position of " 1 ", thereby determines the actual code length of current data.For example, after parallel the comparison, leading 1 detecting unit detects result data relatively, determining to begin most is that bit position of 1, this position has represented that the actual code length of current data (judges promptly these input data drop on which interval of extended code, can judge effective bit wide of present input data like this, just code length).
Step 2020, the actual code length of determining according to leading 1 detection sub-module obtains the initial address of the Huffman code table of actual code length correspondence as address lookup.For example, use the aforementioned code length that obtains, obtain the initial address of corresponding code length, the initial address of table 1 promptly shown in Figure 11～15 for table as address lookup code table initial address register file (Index_rf).
Step 2022, the code length that changes submodule dateout and data according to the position carries out cutting to dateout, keeps the low data of code length bit wide, obtains the Huffman data to decode.For example, also need these input data are carried out cutting concerning the input data that obtain code length, just cut out the random length data cell from fixed-length data an invalid high position is removed, keep the low data of code length bit wide, these data are the Huffman coded data.So far obtain Huffman sign indicating number and code length thereof, also had the initial address of the table of its code length correspondence.The difference of the initial code of use Huffman sign indicating number and corresponding code length can inquire the symbol and the extra bit wide thereof of this Huffman sign indicating number correspondence as the table bias internal of the table of this code length correspondence.
Step 2024, the data result of the Huffman decoding that obtains according to the Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching.For example, the lz77 decoding control unit character (decode results) that compiling is come out according to Huffman decoding module (Lookup_table) generates the address of reading or write historical data windows units (RAM), finishes the matching treatment of data; In addition, lz77 decoding control unit is controlled state informations such as the CRC32 verification of data, outputs.
Step 2026 is according to address storage matched data.For example, the dual port RAM (32Kbyte Dual port RAM) that adopts 32Kb is as historical data windows units (RAM), be used for providing matched data memory space (comprise directly matched data is write the current address, perhaps behind corresponding address reading data, write in the current address again) to lz77 decoding control unit.
Step 2028 is carried out the CRC32 verification to matched data, to judge the correctness that decompresses.For example, the CRC32 verification unit is used for the initial data that lz77 decoding control unit decodes is out carried out the CRC32 verification, compares with original CRC, judges decompression result's correctness.By after the verification of CRC32 verification unit, this decompression result carries out interface via the unit module of dateout buffer memory (OUT_FIFO) and rear end in the decompression result.
The Huffman decoding needs the bit manipulation of random length, in order to guarantee that the streaming of data is handled, need in one-period, finish following three steps operation: the Huffman decoding, abandon used data according to current code length then, the data that decoding is next time needed are taken out again.After the Huffman decoding, data will be passed through the Lz77 decoding processing, and processing method is according to the Huffman decoded results, searches corresponding matched data from historical character window, export and be updated to historical character window the inside then.The hard-wired method of parallel decompression provided by the invention, the mode of a form (tables for each length) is all set up in employing to each code length, walk abreast on the hardware and search 15 forms, under any circumstance, one-period just can be finished a Huffman decoding, the method that adopts than software has higher degree of parallelism, has higher decoding efficiency.
With reference to the exemplary description of aforementioned the present invention, those skilled in the art can clearly know the present invention and have the following advantages:
The invention provides a kind of hard-wired system and method for parallel decompression, use programmable logic device (FPGA) to remove to realize the Gzip decompressing function, by adopting a kind of parallel decompression algorithm, and design is fit to the hardware circuit of this algorithm, thereby increases substantially the treatment effeciency of decompression.
The invention discloses a kind of hard-wired system and method for parallel decompression, realize the random length bit manipulation module of the overall situation by data merge cells and shift unit, simplified design greatly, all modules have been avoided the expense on data consistency is safeguarded all from this module reading of data.
The invention discloses a kind of hard-wired system and method for parallel decompression, even under worst case, consuming time is 3 times of list item maximum number, that is: maximum ltree table maximum has 286 list items, even so maximumly consuming timely also is no more than for 900 cycles.
The invention discloses a kind of hard-wired system and method for parallel decompression, on the basis of taking into account circuit realization complexity and treatment effeciency, designed a kind of data stream type of Lz77 decoder module and handled structure, make decompressed data weekly the phase output is all arranged, do not have bandwidth loss.
Description of the invention provides for example with for the purpose of describing, and is not exhaustively or limit the invention to disclosed form.Many modifications and variations are obvious for the ordinary skill in the art.Selecting and describing embodiment is for better explanation principle of the present invention and practical application, thereby and makes those of ordinary skill in the art can understand the various embodiment that have various modifications that the present invention's design is suitable for special-purpose.
Claims (12)
1. the hard-wired system of a parallel decompression is characterized in that, described system comprises:
The bit manipulation module of random length is used to treat the bit manipulation that decompressed data is carried out random length, obtains the data of random length;
The Huffman code table recovers module, is used for the data according to described random length, recovers the Huffman code table;
The Huffman decoding module is used for according to described Huffman code table, executed in parallel Huffman decoding; And
Decoder module is used for the result according to Huffman decoding, decodes.
2. system according to claim 1 is characterized in that, the bit manipulation module of described random length further comprises:
Data merge submodule, are used for the data that decompressed data and metadata cache submodule are shifted after the operation for the treatment of that input reads are merged, and generate the new decompressed data for the treatment of;
MUX is used for data cached selection the according to input; If described data cached less than predetermined figure place, the data strobe after so just described data merging submodule being merged also is written in the described metadata cache submodule; Otherwise, upgrade data in the described metadata cache submodule with the data after the displacement;
Described metadata cache submodule is used for the described new decompressed data for the treatment of that the described data of buffer memory merge the submodule input, and to the decompressed data for the treatment of of displacement submodule output random length;
Described displacement submodule is used for the data of described metadata cache submodule are carried out dextroposition operation, abandoning the data that the one-period of lasting uses, and data newly-generated after the shifting function is exported to described data merging submodule.
3. system according to claim 1 is characterized in that, described Huffman code table recovers module and further comprises:
The code length calculating sub module is used for the data according to described random length, calculates the code length of each coded data correspondence;
The code length sub module stored is used to store the code length that described code length calculating sub module calculates;
The Huffman code table recovers submodule, is used for according to result calculated, adds up the number of each code length, adds up the symbol of each described code length correspondence, and to after the described symbol ordering, recovers the Huffman code table according to each described code length.
4. system according to claim 1 is characterized in that, described Huffman decoding module further comprises:
Submodule is changed in the position, is used for the input data are carried out bit inversion, to restore described input data;
Comparison sub-module is used for the data that the data after restore are taken out maximum code length, and does relatively parallel with the expansion initial code;
Leading 1 detection sub-module is used for the comparative result according to described comparison sub-module, determines that start bit is the position of " 1 ", thereby determines the actual code length of current data;
Code table initial address submodule is used for obtaining as address lookup according to the actual code length that described leading 1 detection sub-module is determined the initial address of the Huffman code table of described actual code length correspondence;
Data cutting submodule, the code length that is used for changing according to described position submodule dateout and data carries out cutting to described dateout, keeps the low data of described code length bit wide, obtains the Huffman data to decode.
5. system according to claim 1 is characterized in that described decoder module is selected the Lz77 decoder module for use, is used for carrying out the Lz77 decode operation according to the result of Huffman decoding.
6. system according to claim 5 is characterized in that, described Lz77 decoder module further comprises:
Decoding control submodule, the data result that is used for the Huffman decoding that obtains according to described Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching;
The history data store submodule is used for the data of being mated according to the address storage that described decoding control submodule provides;
The syndrome module is used for the matched data that decoding control submodule obtains is carried out the CRC32 verification, to judge the correctness that decompresses.
7. the hard-wired method of a parallel decompression is characterized in that, described method comprises:
Treat decompressed data and carry out the bit manipulation of random length, obtain the data of random length;
According to the data of described random length, recover the Huffman code table;
According to described Huffman code table, executed in parallel Huffman decoding; And
Result according to Huffman decoding decodes.
8. method according to claim 7 is characterized in that, describedly treats the bit manipulation that decompressed data is carried out random length, and the data of obtaining random length further comprise:
The data that data are merged after the submodule input reads treat decompressed data and be shifted operation merge, and generate the new decompressed data for the treatment of;
Data cached selection the according to input; If described data cached less than predetermined figure place, the data strobe after so just described data merging submodule being merged also is written in the metadata cache submodule; Otherwise, upgrade data in the described metadata cache submodule with the data after the displacement;
The described new decompressed data for the treatment of of buffer memory, and the output random length treat decompressed data; And
The decompressed data for the treatment of to described random length is carried out dextroposition operation, abandoning the data that the one-period of lasting uses, and data newly-generated after the shifting function is exported to described data merging submodule.
9. method according to claim 7 is characterized in that, described data according to described random length are recovered the Huffman code table and further comprised:
According to the data of described random length, calculate the code length of each coded data correspondence;
The described code length that storage computation goes out; And
According to result calculated, add up the number of each code length, add up the symbol of each described code length correspondence, and, recover the Huffman code table according to each described code length to after the described symbol ordering.
10. method according to claim 7 is characterized in that, described according to described Huffman code table, the executed in parallel Huffman decoding further comprises:
The input data are carried out bit inversion, to restore described input data;
Take out the data of maximum code length the data after restoring, and do relatively parallel with the expansion initial code;
According to the comparative result of described comparison sub-module, determine that start bit is the position of " 1 ", thereby determine the actual code length of current data;
Obtain the initial address of the Huffman code table of described actual code length correspondence as address lookup according to the definite actual code length of described leading 1 detection sub-module;
The code length that changes submodule dateout and data according to described position carries out cutting to described dateout, keeps the low data of described code length bit wide, obtains the Huffman data to decode.
11. method according to claim 7 is characterized in that, described result according to Huffman decoding, and decoding further comprises and selects for use the Lz77 decoder module to carry out the Lz77 decode operation according to the result of Huffman decoding.
12. method according to claim 11 is characterized in that, described result according to Huffman decoding carries out the Lz77 decoding and further comprises:
The data result of the Huffman decoding that obtains according to described Huffman decoding module generates the address of reading or write the history data store submodule, finishes Data Matching;
According to described address storage matched data; And
Described matched data is carried out the CRC32 verification, to judge the correctness that decompresses.
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