CN102243872A - Method and system for encoding and decoding digital audio signals - Google Patents

Abstract

The invention is suitable for the technical field of encoding and decoding and particularly provides an audio encoding-decoding system and method. In the invention, for a long block, the NDCT (Non-uniform Discrete Cosine Transform) and the IMDCT (Inverse Modified Discrete Cosine Transform) are converted into the DCT-IV type operation with 18 points, and the DCT-IV type operation with 18 points is converted into the three DCT-IV type operations with 6 points; and for a short block, the MDCT (Modified Discrete Cosine Transform) and the IMDCT are directly converted into the DCT-IV type operation with 6 points. Thus, all the operations can be unified into the DCT-IV type operation with 6 points; the sharing of an MDCT and IMDCT operation unit can be realized on the basis of the DCT-IV type operation with 6 points; the structure of the unit is simple; and the circuit can be highly multiplexed, thereby simultaneously saving the area of the circuit and lowering the cost.

Description

The method and system that audio digital signals is encoded, decoded

Technical field

The invention belongs to the coding and decoding technical field, relate in particular to a kind of method and system that audio digital signals is encoded, decoded.

Background technology

In the mp3 coding/decoding system of conversion compression, utilize the energy accumulating of time-frequency conversion, signal energy is gathered on the minority conversion coefficient, thereby improve code efficiency.ISO MPEG (InternationalOrganization for Standardization Moving Picture Experts Group, ISO (International Standards Organization) dynamic image expert group) audio standard provides a cover General Audio decoding method, for the mp3 encoding and decoding, time-frequency conversion mainly is MDCT (the Modified Discrete CosineTransform that adopts in the coding, the improvement discrete cosine transform) and the decoding in the employing IMDCT (Inverse ModifiedDiscrete Cosine Transform, the oppositely discrete cosine transform of improvement), and, be divided into corresponding long piece MDCT again according to the difference of block size, long piece IMDCT and short block MDCT, short block IMDCT.

The expression formula of MDCT is as follows:

$y\left(n\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}X\left(k\right)\·{\mathrm{\Φ}}_{n,k}=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}X\left(k\right)\·\cos \{\frac{2\mathrm{\π}}{N}\·(n+\frac{1}{2})\·(k+\frac{N+2}{4})\},$ $n=0~\frac{N}{2}-1---\left(1\right)$

The expression formula of IMDCT is as follows:

$y\left(n\right)=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}a\left(k\right)\·\cos \{\frac{2\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{N+2}{4})\},$ n＝0～(N-1)(2)

During long piece conversion, N=36; During the short block conversion, N=12.

Fig. 1 is a kind of process flow diagram of conventional MDCT operational method, and according to the process flow diagram of Fig. 1, the step of this way is as follows:

S101: digital input signals is provided, and its length equals block length N;

S102: obtain the intermediate computations signal by input signal, main principle is to have utilized Φ _{N, k}The trigonometric function symmetry, main implementation method is:

$\left\{\begin{array}{c}\mathrm{XX}\left(k\right)=X(N/4+k)-X(N/4-k-1)\\ \mathrm{XX}(N/4+k)=X(N/2+k)+X(N-k-1)\end{array}\right.,k=0~N/4-1---\left(3\right)$

Wherein, X is that length is the input signal of N, and XX is a M signal; K is a running index.

S103: calculate the MDCT operation result according to M signal, its specific practice is as follows:

$y\left(n\right)=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}\mathrm{XX}\left(k\right)*{\mathrm{\Φ}}_{n,k},$ n＝0～N/2-1(4)

In the hardware of step S103 is realized, will consume N ²/ 4 multiplication, when N=36, its multiplying amount will be 324.

S104: output MDCT figure signal: at last operation result is exported.

This hardware realizes directly having adopted the method for multiply accumulating, and advantage is relatively simple for structure, but that its shortcoming is the multiplying amount is very big.The multiplying amount of the primal algorithm that ISO MPEG provides is 648, adopt conventional way after the multiplying amount can be decreased to 324, but with respect to the coding in modules such as analysis filter, the operand of MDCT is still huge.Because operand and processing time that time-frequency conversion itself needs are a large amount of, therefore, seek fast algorithm, reduce the target that its operand is the mp3 encoding and decoding.And because the algorithm of MDCT and IMDCT is not quite similar, in realizing, great majority need to adopt the mode of handling respectively to calculate, adopted in the realization of fast algorithm at some, because the calculating of length piece also is not quite similar, need to use two covering devices to calculate respectively, so need to realize respectively the computing of long piece MDCT, short block MDCT, long piece IDMCT and short block IMDCT in the general realization, design is complicated, and cost is difficult to control.

The described implementation method of Fig. 1 has only been used symmetry, make operand reduce half, but for the mp3 audio decoder, operand is still very big, the someone proposes further to reduce the disposal route of operand successively, method has a lot, but all be to be optimized at a certain application (such as the IMDCT computing of long piece or the MDCT computing of short block), this kind optimization can obviously reduce operand, but different if desired operational forms (for example needs to be the IMDCT of length piece simultaneously, MDCT handles), then need corresponding disposal route of several covers and module, as shown in Figure 2, may need 4 independent arithmetic elements at most, consume bigger, be unfavorable for reducing cost, and should use can be more loaded down with trivial details.

Summary of the invention

The purpose of the embodiment of the invention is to provide a kind of method and system that audio digital signals is encoded, decoded, and is intended to make audio coding decoding computing simplicity of design, cost to be easy to control.

The embodiment of the invention is achieved in that carries out Methods for Coding to audio digital signals, and this coding method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. described digital signal is carried out the MDCT computing, described MDCT computing comprises to the MDCT computing of long piece or to the MDCT computing of short block, described to long piece the MDCT computing or the MDCT computing of short block converted to discrete cosine transform four type DCT-IV computings.

The embodiment of the invention also provides the method that audio digital signals is decoded, and this coding/decoding method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. described digital signal is carried out the IMDCT computing, described IMDCT computing comprises to the IMDCT computing of long piece or to the IMDCT computing of short block, described to long piece the IMDCT computing or the IMDCT computing of short block converted to discrete cosine transform four type DCT-IV computings.

The embodiment of the invention also provides the method for audio digital signals being carried out encoding and decoding, and this method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. to described digital signal encoding and decoding, the discrete cosine transform MDCT computing that when coding, described digital signal is improved, the discrete cosine transform IMDCT computing that when decoding described digital signal is oppositely improved, described MDCT computing and IMDCT computing all convert discrete cosine transform four type DCT-IV computings to.

The embodiment of the invention also provides the coded system of audio digital signals, and this coded system comprises:

IO interface is used to receive at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for long piece digital signal long piece MDCT computing that described IO interface is received or the short block digital signal is carried out short block MDCT computing, described long piece MDCT computing or short block MDCT computing convert discrete cosine transform four type DCT-IV computings to.

The embodiment of the invention also provides the decode system of audio digital signals, and this decode system comprises:

IO interface is used to obtain at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for long piece digital signal long piece IMDCT computing that described IO interface is received or the short block digital signal is carried out short block IMDCT computing, described long piece IMDCT computing or short block IMDCT computing convert discrete cosine transform four type DCT-IV computings to.

The embodiment of the invention also provides the coding/decoding system of audio digital signals, and this coding/decoding system comprises:

IO interface is used to receive at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for digital signal encoding and decoding that described IO interface is received, the discrete cosine transform MDCT computing that when coding, described digital signal is improved, the discrete cosine transform IMDCT computing that when decoding described digital signal is oppositely improved, described MDCT computing or IMDCT computing convert discrete cosine transform four type DCT-IV computings to.

In the embodiment of the invention, by will long piece MDCT, short block MDCT, long piece IMDCT, short block IMDCT all be converted to 6 DCT-IV type computing, thereby can realize that MDCT and IMDCT, long piece and short block can shared main arithmetic elements, and this unit is simple in structure, circuit can be highly multiplexing, also reduced cost when saving circuit area.

Description of drawings

Fig. 1 is the process flow diagram of the MDCT operational method that provides of prior art;

Fig. 2 is the architecture principle figure of the audio coding and decoding system that provides of prior art;

Fig. 3 is the realization flow figure of the coding method that provides of the embodiment of the invention;

Fig. 4 is the specific implementation process flow diagram of the coding method that provides of the embodiment of the invention;

Fig. 5 is the specific implementation process flow diagram of the coding/decoding method that provides of the embodiment of the invention;

Fig. 6 is the specific implementation process flow diagram of the decoding method that provides of the embodiment of the invention;

Fig. 7 is the structure principle chart of the audio coding and decoding system that provides of the embodiment of the invention;

Fig. 8 is the structural drawing that system shown in Figure 7 is realized with the integrated circuit form;

Fig. 9 is the structure principle chart of the Operations Analysis in the system shown in Figure 7;

Figure 10 is the structure principle chart of the logic control element in the system shown in Figure 7;

Figure 11 is the structure principle chart of the arithmetic element in the system shown in Figure 7;

Figure 12 is the work synoptic diagram of the MDCT pre-treatment control circuit that provides of the embodiment of the invention;

Figure 13, Figure 14 and Figure 15 are the synoptic diagram of the long piece pre-treatment that provides of the embodiment of the invention;

Figure 16 is the workflow diagram of the arithmetic element that provides of the embodiment of the invention;

Figure 17 is the work synoptic diagram of the long piece aftertreatment that provides of the embodiment of the invention;

Figure 18 A, Figure 18 B are the work synoptic diagram of the IMDCT aftertreatment that provides of the embodiment of the invention;

Figure 19 is the realization flow figure of the coding method that provides of the embodiment of the invention;

Figure 20 is the realization flow figure of the coding/decoding method that provides of the embodiment of the invention;

Figure 21 is the specific implementation process flow diagram of the coding/decoding method that provides of the embodiment of the invention;

Figure 22 is the realization flow figure of the decoding method that provides of the embodiment of the invention;

Figure 23 is the specific implementation process flow diagram of the decoding method that provides of the embodiment of the invention.

Embodiment

In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.

In the embodiment of the invention, will long piece and short block digital signal, all transform 6 DCT-IV type computing.Therefore can to unify be 6 DCT-IV computings in all computings, can realize the shared of arithmetic element on this basis.

At first, it is as follows MDCT and IMDCT to be transformed 6 the derivation of DCT-IV type computing:

For IMDCT:

$y\left(n\right)=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}a\left(k\right)\·\cos \{\frac{2\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{N+2}{4})\},$ n＝0～(N-1)(5)

If:

N=0～(N/2-1) (6)

Because symmetry is arranged:

As long as so obtain c (n) [0, the N/2) value on, just can obtain y (n) [0, N) Shang Mian value, for long piece, c (n) is 18 DCT-IV computing, for short block, c (n) then is 6 DCT-IV computing.

For MDCT:

$y\left(n\right)=\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}X\left(k\right)\·\cos \{\frac{2\mathrm{\π}}{N}\·(n+\frac{1}{2})\·(k+\frac{N+2}{4})\},$ n＝0～(N/2-1)(7)

If: $\left\{\begin{array}{c}a\left(k\right)=X(k-N/4)-X((3N/4-1)-k),k=N/4~(N/2-1)\\ a\left(k\right)=-X(3N/4+k)-X((3N/4-1)-k),k=0~(N/4-1)\\ c\left(n\right)=y\left(n\right),n=0~(N/2-1)\end{array}\right.---\left(8\right)$

Then:

N=0～(N/2-1), promptly identical with formula (6), just can obtain y (n) as long as calculate c (n).For long piece, c (n) is 18 DCT-IV computing, and for short block, c (n) then is 6 DCT-IV computing.

As from the foregoing, long piece IMDCT and MDCT can obtain by 18 DCT-IV computing, and short block IMDCT and MDCT can obtain by 6 DCT-IV computing.

For 18 DCT-IV computing shown in formula (6) and formula (8), can be converted into 36 DCT-IV computing in the following manner:

$c\left(n\right)=\underset{k=0}{\overset{N/2-1}{\mathrm{\Σ}}}a\left(k\right)\·\cos \{\frac{2\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ n＝0～(N/2-1)(9)

If: $\left\{\begin{array}{c}c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},n=0~(N/6-1)\\ c(3n+1)=A\left(n\right),n=0~(N/6-1)\\ c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},n=0~(N/6-1)\end{array}\right.---\left(10\right)$

So, calculate A (n), B (n) and C (n) at 6, just can obtain 18 c (n).

If: $\begin{array}{c}{f}_k=a\left(k\right)\\ g_k=a(N/6+k)\\ h_k=a(N/3+k),k=\mathrm{0,1}...(N/6-1)\\ f_k^{\′}=f_{N/6-1-k}\\ g_k^{\′}=g_{N/6-1-k}\end{array}---\left(11\right)$

${\mathrm{\φ}}_{n,k}=\{\frac{6\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ θ _k＝(2k+1)π/N (12)

Derive through arrangement, can obtain formula (13):

$A\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}(f_k-g_k^{\′}-h_k)\·\cos {\mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

$B\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}(h_k-g_k^{\′})\·\sin {\mathrm{\θ}}_k+({2f}_k+g_k^{\′}+h_k)\cos {\mathrm{\θ}}_k]\·\cos {\mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

$C\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·\cos {\mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\θ}}_k]\·{\cos \mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

(13)

If: am _k=f _k-g ' _k-h _k, k=0,1... (N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\′})\·\sin {\mathrm{\θ}}_k+(2f_k+g_k^{\′}+h_k){\cos \mathrm{\θ}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·\cos {\mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\θ}}_k,$ k＝0，1...(N/6-1)(14)

A (n), B (n) and C (n) are 6 DCT-IV type computings as can be seen by formula (13) and (14), so far, no matter be long piece, short block, MDCT or IMDCT, can shared identical arithmetic element (6 DCT-IV computings), add that pre-service and aftertreatment realize.

Fig. 3 shows the realization flow of the coding method that the embodiment of the invention provides, and for convenience of description, only shows the part relevant with present embodiment.

The long piece that provides for the outside or the digital audio and video signals of short block, at first to carry out pre-treatment so that long or short block are converted to discrete cosine transform four type DCT-IV computings, then long piece or short block digital signal after handling are carried out MDCT or IMDCT computing, wherein above-mentioned MDCT or IMDCT computing are to finish in same its main operational unit, after computing finishes, carry out aftertreatment output MDCT or IMDCT operation result.

Fig. 4 shows the specific implementation process flow diagram of the coding method that the embodiment of the invention provides, the discrete cosine transform MDCT computing that this coding method improves described digital signal, and details are as follows:

Steps A. at least one audio digital signals is provided, and this digital signal is long piece or short block;

Step B. carries out the MDCT computing to this digital signal, comprises to the MDCT computing of long piece or to the MDCT computing of short block, all converts discrete cosine transform four type DCT-IV computings to the MDCT computing of long piece with to the MDCT computing of short block.。

In above-mentioned steps B, the MDCT computing specifically comprises pre-treatment, computing, aftertreatment three phases, and each stage, the concrete operation of carrying out was as follows:

B1. digital signal is done pre-treatment, this pre-treatment converts long MDCT computing and short block MDCT computing to the DCT-IV computing;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when digital signal is short block, carry out a DCT-IV computing, when digital signal is long piece, carry out three DCT-IV computings;

B3. the DCT-IV operation result is carried out aftertreatment, output MDCT operation result.

According to the difference of long piece, short block, the concrete operations of pretreatment stage are also different, and for example long piece also need long piece pre-treatment after the MDCT pre-treatment, so step B1 specifically comprises again:

B11. judge that digital signal is long piece or short block, when digital signal is short block, execution in step B12, when digital signal is long piece, execution in step B13;

B12. carry out short block MDCT pre-treatment, short block MDCT pre-treatment is to utilize symmetry the MDCT computing of short block is converted to 6 DCT-IV computing; Execution in step B15;

B13. executive chairman's piece MDCT pre-treatment, long piece MDCT pre-treatment are to utilize symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing;

In the embodiment of the invention, above-mentioned steps B.12 and the short block MDCT pre-treatment B.13 and long piece MDCT pre-treatment carry out according to following formula:

a(k)＝X(k-N/4)-X((3N/4-1)-k)，k＝N/4～(N/2-1)

a(k)＝-X(3N/4+k)-X((3N/4-1)-k)，k＝0～(N/4-1)

Wherein, X is that length is the input signal of N, and k is a running index, and in the short block MDCT pre-treatment, N is 12, and in the long piece MDCT pre-treatment, N is 36.

B14. to the long piece pre-treatment of the data after the long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing;

Above-mentioned long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\′})\·{\sin \mathrm{\θ}}_k+(2f_k+g_k^{\′}+h_k)\cos {\mathrm{\θ}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·{\cos \mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k){\sin \mathrm{\θ}}_k,$ k＝0，1...(N/6-1)

Wherein, N is 36, am _k, bm _k, cm _kBe respectively the digital signal of 3 groups 6 suitable DCT-IV computing, the f in the above-mentioned formula _k, g _k, h _k, f ' _k, g ' _k, φ _{N, k}Be defined as follows respectively:

f _k＝a(k)

g _k＝a(N/6+k)

h _k＝a(N/3+k)，k＝0，1...(N/6-1)

f′ _k＝f _N/6-1-k

g′ _k＝g _N/6-1-k

${\mathrm{\φ}}_{n,k}=\{\frac{6\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ θ _k＝(2k+1)π/N，

I.e. formula above (11) and (12), wherein function a is the digital signal of after the pre-treatment 18 or 6 s' suitable DCT-IV computing, i.e. the definition of formula (8).

B15. pre-treatment finishes.

Post-processing stages specifically need be carried out following operation:

B31. judge that digital signal is long piece or short block, when digital signal is short block, execution in step B32; When digital signal is long piece, execution in step B33;

B32. with the DCT-IV operation result of short block, promptly the MDCT operation result is exported, execution in step B34;

B33. the long piece aftertreatment of three DCT-IV operation results that will long piece, the long aftertreatment of determining converts three DCT-IV operation results of long to 18 DCT-IV operation results, and promptly the MDCT operation result is exported;

Above-mentioned long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

Wherein, N is 36, and A (n), B (n), C (n) are respectively and are defined as follows:

$A\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}(f_k-g_k^{\′}-h_k)\·{\cos \mathrm{\θ}}_{n,k},$ n＝0～(N/6-1)

$B\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}(h_k-g_k^{\′})\·\sin {\mathrm{\θ}}_k+({2f}_k+g_k^{\′}+h_k)\cos {\mathrm{\θ}}_k]\·\cos {\mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

$C\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·\cos {\mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\θ}}_k]\·{\cos \mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

I.e. formula above (13), the f in the above-mentioned formula _k, g _k, h _k, f ' _k, g ' _k, φ _{N, k}Be defined as follows respectively:

f _k＝a(k)

g _k＝a(N/6+k)

h _k＝a(N/3+k)，k＝0，1...(N/6-1)

f′ _k＝f _N/6-1-k

g′ _k＝g _N/6-1-k

${\mathrm{\φ}}_{n,k}=\{\frac{6\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ θ _k＝(2k+1)π/N，

Function a is the digital signal after the pre-treatment.

B34. aftertreatment finishes.

Fig. 5 shows the specific implementation process flow diagram of the coding/decoding method that the embodiment of the invention provides, the discrete cosine transform IMDCT computing that this coding/decoding method is oppositely improved described digital signal, and details are as follows:

Steps A. at least one audio digital signals is provided, and this digital signal is long piece or short block;

Step B. carries out the IMDCT computing to this digital signal, comprises to the IMDCT computing of long piece or to the IMDCT computing of short block, converts discrete cosine transform four type DCT-IV computings to the IMDCT computing of long piece or to the IMDCT computing of short block.

In above-mentioned steps B, the IMDCT computing comprises pre-treatment, computing, aftertreatment three phases equally, and each stage, the concrete operation of carrying out was as follows:

B1. digital signal is done pre-treatment, this pre-treatment converts long IMDCT computing and short block IMDCT computing to the DCT-IV computing;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when digital signal is short block, carry out a DCT-IV computing, when digital signal is long piece, carry out three DCT-IV computings;

B3. the DCT-IV operation result is carried out aftertreatment, output IMDCT operation result.

According to the difference of long piece, short block, the concrete operations of pretreatment stage are also different, so step B1 specifically comprises again:

B11. judge that digital signal is long piece or short block, when digital signal is short block, execution in step B13, when digital signal is long piece, execution in step B12;

B12. when digital signal is long piece, the pre-treatment of executive chairman's piece, long piece pre-treatment is the IMDCT computing of long piece is converted to 6 DCT-IV computing;

B13. pre-treatment finishes.

Above-mentioned long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\′})\·{\sin \mathrm{\θ}}_k+(2f_k+g_k^{\′}+h_k)\cos {\mathrm{\θ}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·{\cos \mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k){\sin \mathrm{\θ}}_k,$ k＝0，1...(N/6-1)

Wherein, N is 36, am _k, bm _k, cm _kBe respectively the digital signal of 3 groups 6 suitable DCT-IV computing, the fk in the above-mentioned formula, g _k, h _k, f ' _k, g ' _k, φ _{N, k}Be defined as follows respectively:

f _k＝a(k)

g _k＝a(N/6+k)

h _k＝a(N/3+k)，k＝0，1...(N/6-1)

f′ _k＝f _N/6-1-k

g′ _k＝g _N/6-1-k

${\mathrm{\φ}}_{n,k}=\{\frac{6\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ θ _k＝(2k+1)π/N，

I.e. formula above (11) and (12), wherein function alpha is the digital signal of after the pre-treatment 18 or 6 s' suitable DCT-N computing, i.e. the definition of formula (8).

Post-processing stages specifically need be carried out following operation:

B31. judge that digital signal is long piece or short block, when digital signal is short block, execution in step B32; When digital signal is long piece, execution in step B33;

B32. the DCT-IV operation result with short block carries out the IMDCT aftertreatment, and the IMDCT aftertreatment converts the DCT-IV operation result of short block to the output of short block IMDCT operation result, execution in step B35;

B33. the long piece aftertreatment of three DCT-IV operation results that will long piece, long piece aftertreatment converts three DCT-IV operation results of long to 18 DCT-IV operation results;

B34. 18 DCT-IV operation results are carried out the IMDCT aftertreatment, the IMDCT aftertreatment is the output of 18 DCT-IV operation result conversion growth piece IMDCT operation results;

B35. aftertreatment finishes.

Above-mentioned long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

Wherein, N is 36, and A (n), B (n), C (n) are respectively and are defined as follows:

$A\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}(f_k-g_k^{\′}-h_k)\·{\cos \mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

$B\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}(h_k-g_k^{\′})\·\sin {\mathrm{\θ}}_k+({2f}_k+g_k^{\′}+h_k)\cos {\mathrm{\θ}}_k]\·\cos {\mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

$C\left(n\right)=\underset{k=0}{\overset{N/6-1}{\mathrm{\Σ}}}[\sqrt{3}({(-1)}^n{f}_k^{\′}+{(-1)}^n{g}_k-h_k+)\·\cos {\mathrm{\θ}}_k+({(-1)}^{(n+1)}{f}_k^{\′}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\θ}}_k]\·{\cos \mathrm{\φ}}_{n,k},$ n＝0～(N/6-1)

I.e. formula above (13), the f in the above-mentioned formula _k, g _k, h _k, f ' _k, g ' _k, φ _{N, k}Be defined as follows respectively:

f _k＝a(k)

g _k＝a(N/6+k)

h _k＝a(N/3+k)，k＝0，1...(N/6-1)

f′ _k＝f _N/6-1-k

g′ _k＝g _N/6-1-k

${\mathrm{\φ}}_{n,k}=\{\frac{6\mathrm{\π}}{N}\·(k+\frac{1}{2})\·(n+\frac{1}{2})\},$ θ _k＝(2k+1)π/N，

Function a is the digital signal after the pre-treatment.

The above-mentioned IMDCT of stating aftertreatment is carried out according to following formula:

$y\left(n\right)=\left\{\begin{array}{c}y\left(n\right)=c(n+\frac{N}{4})\\ y(\frac{N}{2}-n-1)=-c(n+\frac{N}{4})\\ y(\frac{3N}{4}-n-1)=-c\left(n\right)\\ y(\frac{3\mathrm{<figure-callout\; id="4"\; label="N"\; filenames="HSA00000118512400072.png,HSA00000118512400101.png"\; state="\{\{state\}\}">N</figure-callout>}}{4}+n)=-c\left(n\right)\end{array}\right.,n=0~\frac{N}{4}-1$

When carrying out short block IMDCT aftertreatment, N is 12; When carrying out short block IMDCT aftertreatment, N is 36.Y (n) is the final output result of IMDCT computing, and function c is the operation result of 18 DCT-IV.

Fig. 6 shows the specific implementation process flow diagram of the decoding method that the embodiment of the invention provides, and details are as follows:

Steps A. at least one audio digital signals is provided, and this digital signal is long piece or short block;

Step B. carries out MDCT computing to this digital signal to these digital signal encoding and decoding when coding, when decoding this digital signal is carried out the IMDCT computing, and MDCT computing and IMDCT computing all convert discrete cosine transform four type DCT-IV computings to.。

In the embodiment of the invention, MDCT computing and IMDCT computing all convert the DCT-IV computing to.

The concrete respectively operation of carrying out of pre-treatment in above-mentioned steps B, computing, aftertreatment three phases is as follows:

B1. digital signal is done pre-treatment, this pre-treatment all converts MDCT computing and IMDCT computing to the DCT-IV computing;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when digital signal is short block, carry out a DCT-IV computing, when digital signal is long piece, carry out three DCT-IV computings;

B3. the DCT-IV operation result is carried out aftertreatment, when carrying out the MDCT computing, aftertreatment converts the DCT-IV operation result output of to MDCT operation result; When carrying out the IMDCT computing, aftertreatment converts the DCT-IV operation result output of to IMDCT operation result.

According to the difference of long piece, short block, the concrete operations of pretreatment stage are also different, so step B1 specifically comprises again:

B11. judge it is to carry out MDCT computing or IMDCT computing, when carrying out the MDCT computing, execution in step B12; When carrying out the IMDCT computing, execution in step B16;

B12. judge that digital signal is short block or long piece, when digital signal is short block, execution in step B13; When digital signal is long piece, execution in step B14;

B13. carry out short block MDCT pre-treatment, short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing, execution in step B18;

B14. when digital signal was long piece, executive chairman's piece MDCT pre-treatment, long piece MDCT pre-treatment utilized symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing;

B15. to the long piece pre-treatment of the data after the long piece MDCT pre-treatment, long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing, execution in step B18;

B16. judge that digital signal is short block or long piece, when digital signal is short block, execution in step B18; When digital signal is long piece, execution in step B17;

B17. to the long piece pre-treatment of digital signal, long piece pre-treatment is the IMDCT computing of digital signal is converted to 6 DCT-IV computing;

B18. pre-treatment finishes.

Post-processing stages specifically need be carried out following operation:

B31. judge it is to carry out MDCT computing or IMDCT computing, when carrying out the MDCT computing, execution in step B32; When carrying out the IMDCT computing, execution in step B34;

B32. judge that digital signal is short block or long piece, when digital signal is short block, with short block DCT-IV operation result, i.e. short block MDCT operation result output, execution in step B37; When digital signal is long piece, execution in step B33;

B33. executive chairman's piece aftertreatment, long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to, promptly long piece MDCT operation result output, execution in step B37;

B34. judge that digital signal is short block or long piece, when digital signal is short block, execution in step B36; When digital signal is long piece, execution in step B35;

B35. executive chairman's piece aftertreatment, described long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to;

B36. carry out the IMDCT aftertreatment, when carrying out short block IMDCT computing, described IMDCT aftertreatment converts short block DCT-IV operation result the output of to IMDCT operation result; When executive chairman's piece IMDCT computing, described IMDCT aftertreatment converts described DCT-IV operation result the output of to IMDCT operation result at 18;

B37. aftertreatment finishes.

Fig. 7 shows the audio coding that the embodiment of the invention provides and/or the structural principle of decode system, and Fig. 8 then is the structural drawing that system shown in Figure 7 is realized with the integrated circuit form, and wherein frame of broken lines represents that inner cellular construction can be integrated on the integrated circuit.For convenience of description, in Fig. 7, Fig. 8, only show the part relevant with present embodiment.

With reference to Fig. 7, Fig. 8, IO interface 3 is used for communicating by letter with external logic 1, receives at least one pending audio digital signals in the lump, and this digital signal is long piece or short block, mainly finishes the function that receives control signal and feedback compute mode; Registers group 2 is mainly other each unit functions such as data are temporary, state demonstration, parameter configuration is provided; Generation, computing and the storage of the data of computing in the Operations Analysis 4 major control arithmetic elements 6; 5 main conversions of being responsible between the computing flow process of logic control element are as the conversion between beginning, intermediate treatment, end and each state; RAM and ROM 7 are memory device.Operations Analysis 4, logic control element 5 and registers group 2 are connected, and are used for from registers group 2 access datas, and control is carried out computing to data, operation result is stored among the RAM after finishing related operation again.

Arithmetic element 6 is connected with Operations Analysis 4 with registers group 2, and the long piece digital signal or the short block digital signal that are used under the control of logic control element 5 and Operations Analysis 4 described IO interface being received are carried out MDCT and/or IMDCT computing.The principle of work of system is described during hereinafter respectively to coding, decoding, three kinds of situations of encoding and decoding.

1, when said system is used to encode separately.Arithmetic element 6 is done pre-treatment to digital signal under the control of 6 Operations Analysis 4 and logic control element 5, pre-treatment converts long MDCT computing and short block MDCT computing to the DCT-IV computing; And, when digital signal is short block, carry out a DCT-IV computing to digital signal execution DCT-IV computing through pre-treatment, when digital signal is long piece, carry out three DCT-IV computings; Arithmetic element 6 is carried out aftertreatment to described DCT-IV operation result under the control of Operations Analysis 4 and described logic control element 5, output MDCT operation result.

Operations Analysis 4 is used to also judge that the digital signal that IO interface 3 receives is long piece or short block; When judging that digital signal is short block, arithmetic element 6 is carried out short block MDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, and short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing; When judging that described digital signal is long piece, arithmetic element 6 is executive chairman's piece MDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, and described long piece MDCT pre-treatment utilizes symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing; And further to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing.

Wherein, carry out describe in the same writing coding method of formula of short block MDCT pre-treatment and long piece MDCT pre-treatment, long piece pre-treatment time institute foundation identical, repeat no more herein.

Operations Analysis 4 is used to also judge that the digital signal that IO interface 3 receives is long piece or short block; When judging that described digital signal is short block, with the DCT-IV operation result of described short block, promptly export by the MDCT operation result under the control of Operations Analysis 4 and logic control element 5 for arithmetic element 6; When judging that digital signal is long piece, arithmetic element 6 under the control of Operations Analysis 4 and logic control element 5 with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results, i.e. MDCT operation result output.

Wherein, that describes in the same writing coding method of formula of long piece aftertreatment time institute foundation is identical, repeats no more herein.

2, when said system is used to encode separately.Arithmetic element 4 is done pre-treatment to digital signal under the control of Operations Analysis 6 and logic control element 5, described pre-treatment converts long IMDCT computing or short block IMDCT computing to discrete cosine transform four type DCT-IV computings; And carry out the DCT-IV computing in the arithmetic element to being input to through the digital signal of pre-treatment, and when described digital signal is short block, carry out a DCT-IV computing, when described digital signal is long piece, carry out three DCT-IV computings; Arithmetic element 4 is carried out aftertreatment to described DCT-IV operation result under the control of Operations Analysis 6 and logic control element 5, output IMDCT operation result.

Operations Analysis 4 is used to also judge that the digital signal that IO interface 3 receives is long piece or short block; When judging that digital signal is short block, do not do pre-treatment; When judging that digital signal is long piece, arithmetic element 6 is executive chairman's piece MDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, and described long piece pre-treatment is the IMDCT computing of long piece is converted to 6 DCT-IV computing.

Operations Analysis 4 is used to also judge that the digital signal that IO interface 3 receives is long piece or short block; When judging that digital signal is short block, arithmetic element 6 is carried out the IMDCT aftertreatment with the DCT-IV operation result of described short block under the control of Operations Analysis 4 and logic control element 5, described IMDCT aftertreatment converts the DCT-IV operation result of short block the output of to short block IMDCT operation result; When judging that described digital signal is long piece, arithmetic element 6 under the control of Operations Analysis 4 and logic control element 5 with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results, and described 18 DCT-IV operation results are carried out the IMDCT aftertreatment, described IMDCT aftertreatment is the output of 18 DCT-IV operation results conversion growth piece IMDCT operation results.

Wherein, that describes in the same above coding/decoding method of the formula of the pre-treatment of executive chairman's piece, long piece aftertreatment, IMDCT aftertreatment time institute foundation is identical, repeats no more herein.

3, when said system is used for encoding and decoding.Arithmetic element 6 all converts MDCT computing and IMDCT computing to discrete cosine transform four type DCT-IV computings under the control of Operations Analysis 4 and logic control element 5.

Under the control of Operations Analysis 4 and logic control element 5,6 pairs of digital signals of arithmetic element are done pre-treatment, and described pre-treatment all converts MDCT computing and IMDCT computing to discrete cosine transform four type DCT-IV computings; Digital signal after 6 pairs of pre-treatments of arithmetic element is carried out the DCT-IV computing, when described digital signal is short block, carries out a DCT-IV computing, when described digital signal is long piece, carries out three DCT-IV computings; Arithmetic element 6 is carried out aftertreatment to the result of described DCT-IV computing again, and when carrying out the MDCT computing, described aftertreatment converts the DCT-IV operation result output of to MDCT operation result; When carrying out the IMDCT computing, described aftertreatment converts the DCT-IV operation result output of to IMDCT operation result.

It need execution MDCT computing still be the IMDCT computing that Operations Analysis 4 also is used to judge current, judges that simultaneously the digital signal that IO interface 3 receives is long piece or short block; When Operations Analysis 4 is judged as current when need carrying out short block MDCT computing, arithmetic element 6 is carried out short block MDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, described short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing; When Operations Analysis 4 is judged as current when needing executive chairman's piece MDCT computing, arithmetic element 6 is executive chairman's piece MDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, and described long piece MDCT pre-treatment utilizes symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing; And to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing; When Operations Analysis 4 is judged as current when needing executive chairman's piece IMDCT computing, arithmetic element 6 is carried out long piece IMDCT pre-treatment under the control of Operations Analysis 4 and logic control element 5, described long piece pre-treatment is the IMDCT computing of described digital signal is converted to 6 DCT-IV computing.

What Operations Analysis 4 also was used to judge current execution is MDCT computing or IMDCT computing, judges that simultaneously the digital signal that IO interface 3 receives is long piece or short block; When Operations Analysis 4 be judged as current execution be short block MDCT computing the time, arithmetic element 6 under the control of Operations Analysis 4 and logic control element 5 with short block DCT-IV operation result, i.e. short block MDCT operation result output; When Operations Analysis 4 be judged as current execution be long piece MDCT computing the time, arithmetic element 6 is the aftertreatment of executive chairman's piece under the control of Operations Analysis 4 and logic control element 5, described long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to, promptly long piece MDCT operation result output; When Operations Analysis 4 be judged as current execution be long piece IMDCT computing the time, arithmetic element 6 is the aftertreatment of executive chairman's piece under the control of Operations Analysis 4 and logic control element 5, and three DCT-IV operation results that described long piece aftertreatment will long piece convert 18 DCT-IV operation result to; And carry out the IMDCT aftertreatment, described IMDCT aftertreatment converts described DCT-IV operation result the output of to IMDCT operation result at 18; When Operations Analysis 4 be judged as current execution be short block IMDCT computing the time, arithmetic element 6 converts IMDCT operation result output at following short block DCT-IV operation result of the control of Operations Analysis 4 and logic control element 5.

Fig. 9 is the structure principle chart of Operations Analysis 4, Operations Analysis 4 mainly generates subelement 46 by main control state machine 44 and arithmetic element control signal and finishes s operation control work, wherein main control state machine 44 is connected with logic control element 5 among Fig. 4, also with length piece judgment sub-unit 41, encoding and decoding judgment sub-unit 42 (be used for coding separately, when being used to decode separately, this subelement does not need), counter 45 connects, and is used to judge the type of calculating and the state exchange that control is calculated.The arithmetic element control signal generates subelement 46 and is connected with arithmetic element 6 among Fig. 4, also is connected with main control state machine 44, counter 45, is used to generate the s operation control signal.Auxiliary control signal generates subelement 47 and generates some auxiliary control signals, as length block mark and encoding and decoding sign etc.; Length piece judgment sub-unit 41 is used to judge that the digital signal of input is long piece digital signal or short block digital signal; Encoding and decoding judgment sub-unit 42 is used to judge that the digital signal of input is coded digital signal or decoded digital signal; Coefficient generates subelement 43 and is connected with arithmetic element control signal generation subelement 47, is used for generating the access signal of calculating process fixed coefficient.Counter 45 is responsible for counting.The arithmetic element control signal generate signal that subelement 46 generates mainly comprise add/down control signal, take advantage of/take advantage of increase control signal, arithmetic element registers group control signal, RAM (random accessmemory, random access memory) read-write control signal etc.

The major function of Operations Analysis 4 is an access data from RAM, ROM 7, under the effect of s operation control signal, data are sent into registers group 2, and enter arithmetic element 6 and carry out computing, finish behind the related operation again the result is stored among the RAM in the storer 7.

Figure 10 is the structural drawing of logic control element 5, realization flow according to hardware is divided, logic control element 5 is divided into 6 parts, be MDCT pre-treatment logic control circuit 51 (not needing when being used to decode separately), long piece pre-treatment logic control circuit 52, multiplex circuit logic control circuit 53, long piece aftertreatment logic control circuit 54, IMDCT aftertreatment logic control circuit 55 (not needing when being used to encode separately), and state conversion logic 56 between the each several part.51,52,53,54 and 55 unified be connected to Operations Analysis 4 and IO interface 3,56 also is connected to Operations Analysis 4, control the memory access accessing operation of corresponding calculating process, s operation control and and IO interface communication.

Wherein, MDCT pre-treatment control circuit 51 is used for carrying out the MDCT pre-treatment with the coded digital signal of 6 pairs of inputs of Operations Analysis 4 common control and calculation unit.Long piece pre-treatment control circuit 52 is used for the long piece pre-treatment of long piece digital signal with 6 pairs of inputs of Operations Analysis 4 common control and calculation unit.Multiplexing arithmetic element control circuit 53 is used to control the multiplexing logic control to arithmetic element 6, no matter long piece, short block, MDCT still is the IMDCT computing, its most computing is all finished in this part, add some pre-treatments (51,52) and aftertreatment (54,55), just can finish required computing.Long piece aftertreatment control circuit 54 be used for 6 pairs of computings of Operations Analysis 4 common control and calculation unit after the long piece aftertreatment of long piece digital signal.IMDCT aftertreatment control circuit 55 is used for carrying out the IMDCT aftertreatment with 6 pairs of result of decoding operation of Operations Analysis 4 common control and calculation unit.State conversion logic 56 is used for controlling the state exchange of calculating process between each nonidentity operation stage, as the conversion between beginning, intermediate treatment, end and each state of computing.

Figure 11 is the structural drawing of arithmetic element 6, and arithmetic element 6 is mainly finished plus-minus method and the multiplying in the whole calculating process.Comprise RAM 601, be used to store the digital signal for the treatment of the encoding and decoding computing and the intermediate operations result of input; ROM 602, are used to store operation coefficient; First register 603, its input end is connected with described RAM; Second register 604, its input end is connected with ROM602; Multiplier 605, two input end are connected with the output terminal of first register 603 and the output terminal of second register 604 respectively; The 3rd register 606, its input end is connected with the output terminal of multiplier 605; First selector 607, its first data input pin is connected with the output terminal of first register 603; Second selector 608, its first data input pin is connected with the output terminal of first register 603, and second data input pin is connected with the output terminal of the 3rd register 606; Add/subtracter 609, two input end is connected with the output terminal of first selector 607 and the output terminal of second selector 608 respectively; The 4th register 610, its input end with add/output terminal of subtracter 609 is connected, its output terminal is connected with second data input pin of first selector 607; Address control unit 611, it is connected with ROM 602 with RAM 601, is used to generate the address of access data; Register selected cell 612, it is connected with first register 603, second register 604, the 3rd register 606, the 4th register 610 and registers group 2, is used to select to participate in the register of computing; Multiplier control module 613, it is connected with multiplier 605, is used to control the computing of multiplier 605; Selector switch control module 614, it is connected with second selector 608 with first selector 607, is used for from the data selection suitable data output of two inputs of first selector 607 and second selector 608; Add/subtracter control module 615, its with add/subtracter 610 is connected, be used to control add/computing of subtracter 610.

The principle of work of arithmetic element shown in Figure 11 is described below: the digital signal of input will be stored in RAM 601 before carrying out MDCT or IMDCT.In whole calculating process, RAM 601 also will be used to store intermediate result.The coefficient that needs in the hardware circuit to use all will be stored in coefficients R OM 602.Multiplier 605 is mainly finished the multiplying in the calculating process: the data of reading from RAM 601 will be temporarily stored in first register 603, the coefficient of reading from ROM 602 will be temporarily stored in the register the 2 604, the value of the register the 1 and second register 604 will be admitted to multiplier 605 and carry out multiplying then, and the result of multiplying will be temporarily stored in the 3rd register 606.The output of the 4th register 610 and first register 603 is respectively two inputs of first selector 607, the output of the 3rd register 606 and first register 603 is respectively two inputs of second selector 608, wherein, first register 603 is output as the data of storage among the RAM 601, the 3rd register 606 is output as the operation result of multiplier 605, and the 4th register 610 is output as and adds/operation result of subtracter 609.Like this, add/subtracter 609 just can finish the plus-minus method hybrid operation of following several situations: 1, the addition of data or subtraction among the RAM 601,2 data of coming out from RAM 601 enter first selector 607 and second selector 608 respectively through first register 603, enter then to add/subtracter 609 finishes and adds/subtraction; 2, the multiply accumulating computing, the result of multiplying for the first time will enter by second selector 608 and add/subtracter 609, be temporarily stored in then in the 4th register 610, so that provide the input data for first selector 607.Secondary multiplication result will enter by second selector 608 and add/B of subtracter 609 end, being temporarily stored in result in the 4th register 610 will enter and add/the A end of subtracter 609, the result of both computings will be temporarily stored in the 4th register 610, so that provide the input data for first selector 607.The process of multiply accumulating will finish until multiply accumulating always by top method circulation.The arithmetic operation of the MDCT pre-treatment control circuit 51 among Fig. 6, long piece pre-treatment control circuit 52, multiplexing arithmetic element control circuit 53, long piece aftertreatment control circuit 54 and IMDCT aftertreatment control circuit 5, can be decomposed into memory addressing, register addressing, plus-minus method and multiplying.With multiplexing 6 the DCT-IV computing of arithmetic element is example, formula as follows:

$c\left(n\right)=\underset{k=0}{\overset{5}{\mathrm{\&Sigma;}}}a\left(k\right)\&CenterDot;\cos \{\frac{\mathrm{\&pi;}}{6}\&CenterDot;(k+\frac{1}{2})\&CenterDot;(n+\frac{1}{2})\},$ n＝0～5

$a\left(k\right)\&CenterDot;\cos \{\frac{\mathrm{\&pi;}}{6}\&CenterDot;(k+\frac{1}{2})\&CenterDot;(n+\frac{1}{2})\}$

At first read a (k) from RAM, coefficient is read again to registers group in k=0～5 from Rom

The input of multiplier is selected by selecting device then to registers group in n=0～5, k=0～5, and an input of multiplier obtains from the register of storage a (k), and another input is from storage

Register obtain, and then finish a in the multiplier (k) with

Multiplication, last same selection adds, the input of subtracter, is adding, is finishing adding up of multiplication result in the subtracter, until all computings are finished, the storage operation result is in RAM.

Figure 12 is the work synoptic diagram of the MDCT pre-treatment control circuit 51 in the logic control element, and wherein, X0-X35 represents input signal, a0---a17 represents through the output result after MDCT pre-treatment control circuit 51 and the arithmetic element 6.With first is example, at first from RAM 601, take out the 28th input data and the 25th input data, deliver to selector switch 607 and selector switch 608 respectively, enter then add/A, the B of subtracter 609 end finishes and adds/subtraction, at last operation result is left among the RAM 601.Also can executive chairman's short block determining step S804 after computing finishes, to determine next step computing.

Figure 13,14 and 15 is synoptic diagram of long piece pre-treatment step S805, the input data am of A (n), B (n) and C (n) _k, bm _kAnd cm _kThe pre-treatment difference, need to handle respectively.Am _kCalculating as shown in figure 13, bm _kCalculating as shown in figure 14, cm _kCalculating as shown in figure 15.Long piece pre-treatment step need carry out plus-minus method and multiplication/multiply accumulating computing to the input data, and need store corresponding multiplication coefficient at ROM.Earlier read a (k) from RAM during processing, multiplication/multiply accumulating and plus and minus calculation are carried out these data with from the corresponding coefficient that ROM obtains then in k=0～17 in registers group, at last the am as a result that obtains _k, k=0,1...5, bm _k, k=0,1...5 and cm _kK=0,1...5 deposits back among the RAM and goes.This part comprises operation registers, produces the input selection control and the output control logic of the read-write logic of RAM and ROM, generation adder-subtractor and multiplier.

The hardware realization flow figure of arithmetic element 6 is as shown in figure 16:

Step S1601: flow process begins;

Step S1602: the address that generates the input data;

Step S1603: the input Data Loading is advanced registers group;

Step S1604: carry out corresponding multiplication, signed magnitude arithmetic(al) according to steering logic;

Step S1605: intermediate result is also deposited in registers group;

Step S1606: judge to calculate whether finish, short block only need enter multiplexing its main operational unit and calculate once, long piece then needs cycle calculations 3 times;

Step S1607: output results to RAM;

Step S1608: its main operational finishes.

Long piece post processing operations as shown in figure 17, the operation result of 3 groups 6 DCT-IV is converted into the operation result of 18 DCT-IV, be the described computing of formula (10), computing is fairly simple, only needs simple signed magnitude arithmetic(al) and regenerate memory address to get final product.

The available Figure 18 A of the operation of IMDCT aftertreatment and Figure 18 B describe: promptly carry out the IMDCT aftertreatment if desired, can be with after passing through multiplexing its main operational element circuit step or long piece post-processing step, the value that is kept among the RAM is divided into 2 parts, represents with A, the B shown in Figure 18 A respectively, carry out the IMDCT aftertreatment after, output data quantitatively is 2 times before the output, it is B in proper order ,-B ,-A,-A is shown in Figure 18 B.

In the embodiment of the invention, by will long piece MDCT, short block MDCT, long piece IMDCT, short block IMDCT all be converted to 6 DCT-IV type computing, thereby can realize that MDCT and IMDCT, long piece and short block can shared main arithmetic elements, and this unit is simple in structure, and circuit can be highly multiplexing, saved circuit area, the multiplying amount only is 114 during long piece, short block multiplication amount is 36 only, has reduced operand, has reduced power consumption.

The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (49)

1. audio digital signals is carried out Methods for Coding, it is characterized in that, this coding method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. described digital signal is carried out the MDCT computing, described MDCT computing comprises to the MDCT computing of long piece or to the MDCT computing of short block, described to long piece the MDCT computing or the MDCT computing of short block converted to discrete cosine transform four type DCT-IV computings.

2. coding method according to claim 1 is characterized in that, described MDCT computing comprises:

B1. described digital signal is done pre-treatment, described pre-treatment converts long MDCT computing or short block MDCT computing to discrete cosine transform four type DCT-IV computings;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when described digital signal is short block, carry out a DCT-IV computing, when described digital signal is long piece, carry out three DCT-IV computings;

B3. described DCT-IV operation result is carried out aftertreatment, output MDCT operation result.

3. coding method according to claim 2 is characterized in that, described pre-treatment comprises:

B11. judge that described digital signal is long piece or short block, when described digital signal is short block, execution in step B12, when described digital signal is long piece, execution in step B13;

B12. carry out short block MDCT pre-treatment, described short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing; Execution in step B15;

B13. executive chairman's piece MDCT pre-treatment, described long piece MDCT pre-treatment utilize symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing;

B14. to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing;

B15. pre-treatment finishes.

4. coding method according to claim 2 is characterized in that, described short block MDCT pre-treatment or long piece MDCT pre-treatment are carried out according to following formula:

a(k)＝X(k-N/4)-X((3N/4-1)-k)，k＝N/4～(N/2-1)

a(k)＝-X(3N/4+k)-X((3N/4-1)-k)，k＝0～(N/4-1)

In the short block MDCT pre-treatment, N is 12;

In the long piece MDCT pre-treatment, N is 36.

5. coding method according to claim 2 is characterized in that, described long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\&prime;})\&CenterDot;\sin {\mathrm{\&theta;}}_k+({2f}_k+g_k^{\&prime;}+h_k)\cos {\mathrm{\&theta;}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\&prime;}+{(-1)}^n{g}_k-h_k+)\&CenterDot;{\cos \mathrm{\&theta;}}_k+({(-1)}^{(n+1)}{f}_k^{\&prime;}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\&theta;}}_k,$ K=0,1... (N/6-1) _NBe 36.

6. coding method according to claim 2 is characterized in that, described aftertreatment comprises:

B31. judge that described digital signal is long piece or short block, when described digital signal is short block, execution in step B32; When described digital signal is long piece, execution in step B33;

B32. with the DCT-IV operation result of described short block, promptly the MDCT operation result is exported, execution in step B34;

B33. with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results, i.e. MDCT operation result output;

B34. aftertreatment finishes.

7. coding method according to claim 6 is characterized in that, described long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

N is 36.

8. the method that audio digital signals is decoded is characterized in that, this coding/decoding method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. described digital signal is carried out the IMDCT computing, described IMDCT computing comprises to the IMDCT computing of long piece or to the IMDCT computing of short block, described to long piece the IMDCT computing or the IMDCT computing of short block converted to discrete cosine transform four type DCT-IV computings.

9. coding/decoding method according to claim 8 is characterized in that, described IMDCT computing comprises:

B1. described digital signal is done pre-treatment, described pre-treatment converts long IMDCT computing or short block IMDCT computing to discrete cosine transform four type DCT-IV computings;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when described digital signal is short block, carry out a DCT-IV computing, when described digital signal is long piece, carry out three DCT-IV computings;

B3. described DCT-IV operation result is carried out aftertreatment, output IMDCT operation result.

10. coding/decoding method according to claim 9 is characterized in that, described pre-treatment comprises:

B11. judge that described digital signal is long piece or short block, when described digital signal is short block, execution in step B13, when described digital signal is long piece, execution in step B12;

B12. when described digital signal is long piece, the pre-treatment of executive chairman's piece, described long piece pre-treatment is the IMDCT computing of long piece is converted to 6 DCT-IV computing;

B13. pre-treatment finishes.

11. coding/decoding method according to claim 10 is characterized in that, described long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\&prime;})\&CenterDot;\sin {\mathrm{\&theta;}}_k+({2f}_k+g_k^{\&prime;}+h_k)\cos {\mathrm{\&theta;}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\&prime;}+{(-1)}^n{g}_k-h_k+)\&CenterDot;{\cos \mathrm{\&theta;}}_k+({(-1)}^{(n+1)}{f}_k^{\&prime;}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\&theta;}}_k,$ K=0,1... (N/6-1) _NBe 36.

12. coding/decoding method according to claim 9 is characterized in that, described aftertreatment comprises:

B31. judge that described digital signal is long piece or short block, when described digital signal is short block, execution in step B32; When described digital signal is long piece, execution in step B33;

B32. the DCT-IV operation result with described short block carries out the IMDCT aftertreatment, and described IMDCT aftertreatment converts the DCT-IV operation result of short block to the output of short block IMDCT operation result, execution in step B35;

B33. with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results;

B34. described 18 DCT-IV operation results are carried out the IMDCT aftertreatment, described IMDCT aftertreatment is the output of 18 DCT-IV operation result conversion growth piece IMDCT operation results;

B35. aftertreatment finishes.

13. coding/decoding method according to claim 12 is characterized in that, described long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

N is 36.

14. coding/decoding method according to claim 12 is characterized in that, described IMDCT aftertreatment is carried out according to following formula:

$y\left(n\right)=\left\{\begin{array}{c}y\left(n\right)=c(n+\frac{N}{4})\\ y(\frac{N}{2}-n-1)=-c(n+\frac{N}{4})\\ y(\frac{3N}{4}-n-1)=-c\left(n\right)\\ y(\frac{3N}{4}+n)=-c\left(n\right)\end{array}\right.,n=0~\frac{N}{4}-1$

When carrying out short block IMDCT aftertreatment, N is 12;

When carrying out short block IMDCT aftertreatment, N is 36.

15. the method to audio digital signals carries out encoding and decoding is characterized in that, this method comprises:

A. obtain at least one audio digital signals, described digital signal is long piece or short block;

B. to described digital signal encoding and decoding, the discrete cosine transform MDCT computing that when coding, described digital signal is improved, the discrete cosine transform IMDCT computing that when decoding described digital signal is oppositely improved, described MDCT computing and IMDCT computing all convert discrete cosine transform four type DCT-IV computings to.

16. decoding method according to claim 15 is characterized in that, described digital signal codec is comprised:

B1. described digital signal is done pre-treatment, described pre-treatment converts described MDCT computing or described IMDCT computing to discrete cosine transform four type DCT-IV computings;

B2. the digital signal through pre-treatment is input to and carries out the DCT-IV computing in the arithmetic element, when described digital signal is short block, carry out a DCT-IV computing, when described digital signal is long piece, carry out three DCT-IV computings;

B3. described DCT-IV operation result is carried out aftertreatment, when carrying out the MDCT computing, described aftertreatment converts the DCT-IV operation result output of to MDCT operation result; When carrying out the IMDCT computing, described aftertreatment converts the DCT-IV operation result output of to IMDCT operation result.

17. decoding method according to claim 16 is characterized in that, described pre-treatment comprises:

B11. judge it is to carry out MDCT computing or IMDCT computing, when carrying out the MDCT computing, execution in step B12; When carrying out the IMDCT computing, execution in step B16;

B12. judge that described digital signal is short block or long piece, when described digital signal is short block, execution in step B13; When described digital signal is long piece, execution in step B14;

B13. carry out short block MDCT pre-treatment, described short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing, execution in step B18;

B14. when described digital signal was long piece, executive chairman's piece MDCT pre-treatment, described long piece MDCT pre-treatment utilized symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing;

B15. to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing, execution in step B18;

B16. judge that described digital signal is short block or long piece, when described digital signal is short block, execution in step B18; When described digital signal is long piece, execution in step B17;

B17. to the long piece pre-treatment of described digital signal, described long piece pre-treatment is the IMDCT computing of described digital signal is converted to 6 DCT-IV computing;

B18. pre-treatment finishes.

18. decoding method according to claim 16 is characterized in that, described aftertreatment comprises:

B31. judge it is to carry out MDCT computing or IMDCT computing, when carrying out the MDCT computing, execution in step B32; When carrying out the IMDCT computing, execution in step B34;

B32. judge that described digital signal is short block or long piece, when described digital signal is short block, with short block DCT-IV operation result, i.e. short block MDCT operation result output, execution in step B37; When described digital signal is long piece, execution in step B33;

B33. executive chairman's piece aftertreatment, described long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to, promptly long piece MDCT operation result output, execution in step B37;

B34. judge that described digital signal is short block or long piece, when described digital signal is short block, execution in step B36; When described digital signal is long piece, execution in step B35;

B35. executive chairman's piece aftertreatment, described long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to;

B36. carry out the IMDCT aftertreatment, when carrying out short block IMDCT computing, described IMDCT aftertreatment converts short block DCT-IV operation result the output of to IMDCT operation result; When executive chairman's piece IMDCT computing, described IMDCT aftertreatment converts described DCT-IV operation result the output of to IMDCT operation result at 18;

B37. aftertreatment finishes.

19. the coded system of audio digital signals is characterized in that, this coded system comprises:

IO interface is used to receive at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for long piece digital signal long piece MDCT computing that described IO interface is received or the short block digital signal is carried out short block MDCT computing, described long piece MDCT computing or short block MDCT computing convert discrete cosine transform four type DCT-IV computings to.

20. the coded system of audio digital signals according to claim 19 is characterized in that, this coded system also comprises:

Operations Analysis is used to generate operation coefficient and s operation control signal;

Logic control element is used to control the conversion between the computing flow process;

Described arithmetic element is done pre-treatment to described digital signal under the control of described Operations Analysis and described logic control element, described pre-treatment converts long MDCT computing or short block MDCT computing to discrete cosine transform four type DCT-IV computings; And, when described digital signal is short block, carry out a DCT-IV computing to digital signal execution DCT-IV computing through pre-treatment, when described digital signal is long piece, carry out three DCT-IV computings;

Described arithmetic element is carried out aftertreatment to described DCT-IV operation result under the control of described Operations Analysis and described logic control element, output MDCT operation result.

21. the coded system of audio digital signals according to claim 20 is characterized in that:

Described Operations Analysis is used to also judge that the digital signal that described IO interface receives is long piece or short block;

When judging that described digital signal is short block, described arithmetic element is carried out short block MDCT pre-treatment under the control of described Operations Analysis and described logic control element, described short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing;

When judging that described digital signal is long piece, described arithmetic element is executive chairman's piece MDCT pre-treatment under the control of described Operations Analysis and described logic control element, and described long piece MDCT pre-treatment utilizes symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing; And further to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing.

22. the coded system of audio digital signals according to claim 20 is characterized in that, described short block MDCT pre-treatment or long piece MDCT pre-treatment are carried out according to following formula:

a(k)＝X(k-N/4)-X((3N/4-1)-k)，k＝N/4～(N/2-1)

a(k)＝-X(3N/4+k)-X((3N/4-1)-k)，k＝0～(N/4-1)

In the short block MDCT pre-treatment, N is 12;

In the long piece MDCT pre-treatment, N is 36.

23. the coded system of audio digital signals according to claim 20 is characterized in that, described long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\&prime;})\&CenterDot;\sin {\mathrm{\&theta;}}_k+({2f}_k+g_k^{\&prime;}+h_k)\cos {\mathrm{\&theta;}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\&prime;}+{(-1)}^n{g}_k-h_k+)\&CenterDot;{\cos \mathrm{\&theta;}}_k+({(-1)}^{(n+1)}{f}_k^{\&prime;}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\&theta;}}_k,$ K=0,1... (N/6-1) _NBe 36.

24. the coded system of audio digital signals according to claim 20 is characterized in that:

Described Operations Analysis is used to also judge that the digital signal that described IO interface receives is long piece or short block;

When judging that described digital signal is short block, with the DCT-IV operation result of described short block, promptly export by the MDCT operation result under the control of described Operations Analysis and described logic control element for described arithmetic element;

When judging that described digital signal is long piece, described arithmetic element under the control of described Operations Analysis and described logic control element with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results, i.e. MDCT operation result output.

25. the coded system of audio digital signals according to claim 24 is characterized in that, described long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

N is 36.

26. the coded system according to each described audio digital signals of claim 21 to 25 is characterized in that, described Operations Analysis comprises:

Length piece judgment sub-unit is used to judge that the digital signal of input is long piece or short block;

Counter;

The main control state machine is connected with described length piece judgment sub-unit, described counter, is used to judge calculation mode, and the state exchange of control calculating;

The arithmetic element control signal generates subelement, is connected with described main control state machine, described counter, is used to generate the s operation control signal; And

Coefficient generates subelement, generates subelement with described arithmetic element control signal and is connected, and is used for generating the access signal of calculating process fixed coefficient.

27. the coded system of audio digital signals according to claim 26 is characterized in that, described Operations Analysis also comprises:

Auxiliary control signal generates subelement, and it is connected with the control signal generation unit of described arithmetic element, is used to generate the auxiliary operation control signal, and described auxiliary operation control signal comprises the length block mark.

28. the coded system according to each described audio digital signals of claim 21 to 25 is characterized in that, described logic control element comprises:

The state exchange logic is used for controlling the state exchange of calculating process between each nonidentity operation stage;

MDCT pre-treatment control circuit is used for the described arithmetic element of the common control of described Operations Analysis the encoded data stream of importing being carried out the MDCT pre-treatment;

Long piece pre-treatment control circuit is used for and the long piece long piece pre-treatment of the described arithmetic element of the common control of described Operations Analysis to input;

Multiplexing arithmetic element control circuit is used to control multiplexing to described arithmetic element;

Long piece aftertreatment control circuit is used for and the long piece long piece aftertreatment of the described arithmetic element of the common control of described Operations Analysis after to computing.

29. the coded system according to each described audio digital signals of claim 21 to 25 is characterized in that, described arithmetic element comprises:

RAM is used to store the digital signal and the intermediate operations result of the computing to be encoded of input;

ROM is used to store operation coefficient;

First register, its input end is connected with described RAM;

Second register, its input end is connected with described ROM;

Multiplier, two input end are connected with the output terminal of described first register and the output terminal of described second register respectively;

The 3rd register, its input end is connected with the output terminal of described multiplier;

First selector, its first data input pin is connected with the output terminal of described first register;

Second selector, its first data input pin is connected with the output terminal of described first register, and second data input pin is connected with the output terminal of described the 3rd register;

Add/subtracter, two input end is connected with the output terminal of described first selector and the output terminal of described second selector respectively;

The 4th register, its input end is connected with the output terminal of described adding/subtracter, and its output terminal is connected with second data input pin of described first selector;

Address control unit, it is connected with described ROM with described RAM, is used to generate the address of access data;

The register selected cell, it is connected with described first register, second register, the 3rd register, the 4th register and described registers group, is used to select to participate in the register of computing;

The multiplier control module, it is connected with described multiplier, is used to control the computing of described multiplier;

The selector switch control module, it is connected with described second selector with described first selector, is used for from the data selection suitable data output of two inputs of described first selector and described second selector;

Add/the subtracter control module, it is connected with described adding/subtracter, is used to control the computing of described adding/subtracter.

30. the decode system of audio digital signals is characterized in that, this decode system comprises:

IO interface is used to obtain at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for long piece digital signal long piece IMDCT computing that described IO interface is received or the short block digital signal is carried out short block IMDCT computing, described long piece IMDCT computing or short block IMDCT computing convert discrete cosine transform four type DCT-IV computings to.

31. the decode system of audio digital signals according to claim 30 is characterized in that, this decode system also comprises:

Operations Analysis is used to generate operation coefficient and s operation control signal;

Logic control element is used to control the conversion between the computing flow process;

Described arithmetic element is done pre-treatment to described digital signal under the control of described Operations Analysis and described logic control element, described pre-treatment converts long IMDCT computing or short block IMDCT computing to discrete cosine transform four type DCT-IV computings; And will be input to execution DCT-IV computing in the arithmetic element through the digital signal of pre-treatment, and when described digital signal is short block, carry out a DCT-IV computing, when described digital signal is long piece, carry out three DCT-IV computings;

Described arithmetic element is carried out aftertreatment to described DCT-IV operation result under the control of described Operations Analysis and described logic control element, output IMDCT operation result.

32. the decode system of audio digital signals according to claim 31 is characterized in that:

Described Operations Analysis is used to also judge that the digital signal that described IO interface receives is long piece or short block;

When judging that described digital signal is short block, do not do pre-treatment;

When judging that described digital signal is long piece, described arithmetic element is the pre-treatment of executive chairman's piece under the control of described Operations Analysis and described logic control element, and described long piece pre-treatment is the IMDCT computing of long piece is converted to 6 DCT-IV computing.

33. the coded system of audio digital signals according to claim 32 is characterized in that, described long piece pre-treatment is carried out according to following formula:

am _k＝f _k-g′ _k-h _k，k＝0，1...(N/6-1)

${\mathrm{bm}}_k=\sqrt{3}(h_k-g_k^{\&prime;})\&CenterDot;\sin {\mathrm{\&theta;}}_k+({2f}_k+g_k^{\&prime;}+h_k)\cos {\mathrm{\&theta;}}_k,$ k＝0，1...(N/6-1)

${\mathrm{cm}}_k=\sqrt{3}({(-1)}^n{f}_k^{\&prime;}+{(-1)}^n{g}_k-h_k+)\&CenterDot;{\cos \mathrm{\&theta;}}_k+({(-1)}^{(n+1)}{f}_k^{\&prime;}+{(-1)}^n{g}_k+h_k)\sin {\mathrm{\&theta;}}_k,$ K=0,1... (N/6-1) _NBe 36.

34. the decode system of audio digital signals according to claim 30 is characterized in that:

Described Operations Analysis is used to also judge that the digital signal that described IO interface receives is long piece or short block;

When judging that described digital signal is short block, described arithmetic element is carried out the IMDCT aftertreatment with the DCT-IV operation result of described short block under the control of described Operations Analysis and described logic control element, described IMDCT aftertreatment converts the DCT-IV operation result of short block the output of to short block IMDCT operation result;

When judging that described digital signal is long piece, described arithmetic element under the control of described Operations Analysis and described logic control element with the long piece aftertreatment of three DCT-IV operation results of described long piece, described long piece aftertreatment converts three DCT-IV operation results of described long piece to 18 DCT-IV operation results, and described 18 DCT-IV operation results are carried out the IMDCT aftertreatment, described IMDCT aftertreatment is the output of 18 DCT-IV operation results conversion growth piece IMDCT operation results.

35. the decode system of audio digital signals according to claim 34 is characterized in that, described long piece aftertreatment is carried out according to following formula:

$c\left(3n\right)=\frac{B\left(n\right)+C\left(n\right)}{2},$ n＝0～(N/6-1)

c(3n+1)＝A(n)，n＝0～(N/6-1)

$c(3n+2)=\frac{B\left(n\right)-C\left(n\right)}{2},$ n＝0～(N/6-1)

N is 36.

36. the decode system of audio digital signals according to claim 34 is characterized in that, described IMDCT aftertreatment is carried out according to following formula:

$y\left(n\right)=\left\{\begin{array}{c}y\left(n\right)=c(n+\frac{N}{4})\\ y(\frac{N}{2}-n-1)=-c(n+\frac{N}{4})\\ y(\frac{3N}{4}-n-1)=-c\left(n\right)\\ y(\frac{3N}{4}+n)=-c\left(n\right)\end{array}\right.,n=0~\frac{N}{4}-1$

When carrying out short block IMDCT aftertreatment, N is 12;

When carrying out short block IMDCT aftertreatment, N is 36.

37. the decode system according to each described audio digital signals of claim 32 to 36 is characterized in that, described Operations Analysis comprises:

Length piece judgment sub-unit is used to judge that the digital signal of input is long piece or short block;

Counter;

The main control state machine is connected with described length piece judgment sub-unit, described counter, is used to judge calculation mode, and the state exchange of control calculating;

The arithmetic element control signal generates subelement, is connected with described main control state machine, described counter, is used to generate the s operation control signal; And

Coefficient generates subelement, generates subelement with described arithmetic element control signal and is connected, and is used for generating the access signal of calculating process fixed coefficient.

38. the decode system according to the described audio digital signals of claim 37 is characterized in that, described Operations Analysis also comprises:

Auxiliary control signal generates subelement, and it is connected with the control signal generation unit of described arithmetic element, is used to generate the auxiliary operation control signal, and described auxiliary operation control signal comprises the length block mark.

39. the decode system according to each described audio digital signals of claim 32 to 36 is characterized in that, described logic control element comprises:

The state exchange logic is used for controlling the state exchange of calculating process between each nonidentity operation stage;

Long piece pre-treatment control circuit is used for and the long piece long piece pre-treatment of the described arithmetic element of the common control of described Operations Analysis to input;

Multiplexing arithmetic element control circuit is used to control multiplexing to described arithmetic element;

Long piece aftertreatment control circuit is used for and the long piece long piece aftertreatment of the described arithmetic element of the common control of described Operations Analysis after to computing; And

IMDCT aftertreatment control circuit is used for the described arithmetic element of the common control of described Operations Analysis result of decoding operation being carried out the IMDCT aftertreatment.

40. the decode system according to each described audio digital signals of claim 32 to 36 is characterized in that, described arithmetic element comprises:

RAM is used to store the digital signal and the intermediate operations result of the computing to be decoded of input;

ROM is used to store operation coefficient;

First register, its input end is connected with described RAM;

Second register, its input end is connected with described ROM;

Multiplier, two input end are connected with the output terminal of described first register and the output terminal of described second register respectively;

The 3rd register, its input end is connected with the output terminal of described multiplier;

First selector, its first data input pin is connected with the output terminal of described first register;

Second selector, its first data input pin is connected with the output terminal of described first register, and second data input pin is connected with the output terminal of described the 3rd register;

Add/subtracter, two input end is connected with the output terminal of described first selector and the output terminal of described second selector respectively;

The 4th register, its input end is connected with the output terminal of described adding/subtracter, and its output terminal is connected with second data input pin of described first selector;

Address control unit, it is connected with described ROM with described RAM, is used to generate the address of access data;

The register selected cell, it is connected with described first register, second register, the 3rd register, the 4th register and described registers group, is used to select to participate in the register of computing;

The multiplier control module, it is connected with described multiplier, is used to control the computing of described multiplier;

The selector switch control module, it is connected with described second selector with described first selector, is used for from the data selection suitable data output of two inputs of described first selector and described second selector;

Add/the subtracter control module, it is connected with described adding/subtracter, is used to control the computing of described adding/subtracter.

41. the coding/decoding system of audio digital signals is characterized in that, this coding/decoding system comprises:

IO interface is used to receive at least one audio digital signals, and described digital signal is long piece or short block;

Arithmetic element, be used for digital signal encoding and decoding that described IO interface is received, the discrete cosine transform MDCT computing that when coding, described digital signal is improved, the discrete cosine transform IMDCT computing that when decoding described digital signal is oppositely improved, described MDCT computing or IMDCT computing convert discrete cosine transform four type DCT-IV computings to.

42. the coding/decoding system according to the described audio digital signals of claim 41 is characterized in that, this coding/decoding system also comprises:

Operations Analysis is used to generate operation coefficient and s operation control signal;

Logic control element is used to control the conversion between the computing flow process;

Described arithmetic element converts described MDCT computing or IMDCT computing to discrete cosine transform four type DCT-IV computings under the control of described Operations Analysis and described logic control element.

43. the coding/decoding system according to the described audio digital signals of claim 42 is characterized in that:

Under the control of described Operations Analysis and described logic control element, described arithmetic element is done pre-treatment to described digital signal, and described pre-treatment converts described MDCT computing or described IMDCT computing to discrete cosine transform four type DCT-IV computings;

The digital signal of described arithmetic element after to pre-treatment carried out the DCT-IV computing, when described digital signal is short block, carries out a DCT-IV computing, when described digital signal is long piece, carries out three DCT-IV computings;

Described arithmetic element is carried out aftertreatment to the result of described DCT-IV computing, and when carrying out the MDCT computing, described aftertreatment converts the DCT-IV operation result output of to MDCT operation result; When carrying out the IMDCT computing, described aftertreatment converts the DCT-IV operation result output of to IMDCT operation result.

44. the coding/decoding system according to the described audio digital signals of claim 42 is characterized in that:

It need execution MDCT computing still be the IMDCT computing that described Operations Analysis also is used to judge current, judges that simultaneously the digital signal that described IO interface receives is long piece or short block;

When described Operations Analysis is judged as current when need carrying out short block MDCT computing, described arithmetic element is carried out short block MDCT pre-treatment under the control of described Operations Analysis and described logic control element, described short block MDCT pre-treatment utilizes symmetry the MDCT computing of short block is converted to 6 DCT-IV computing;

When described Operations Analysis is judged as current when needing executive chairman's piece MDCT computing, described arithmetic element is executive chairman's piece MDCT pre-treatment under the control of described Operations Analysis and described logic control element, and described long piece MDCT pre-treatment utilizes symmetry the MDCT computing of long piece is converted to 18 DCT-IV computing; And to the long piece pre-treatment of the data after the described long piece MDCT pre-treatment, described long piece pre-treatment converts 18 DCT-IV computing to 6 DCT-IV computing;

When described Operations Analysis is judged as current when needing executive chairman's piece IMDCT computing, described arithmetic element is carried out long piece IMDCT pre-treatment under the control of described Operations Analysis and described logic control element, described long piece pre-treatment is the IMDCT computing of described digital signal is converted to 6 DCT-IV computing.

45. the coding/decoding system according to the described audio digital signals of claim 42 is characterized in that:

What described Operations Analysis also was used to judge current execution is MDCT computing or IMDCT computing, judges that simultaneously the digital signal that described IO interface receives is long piece or short block;

When described Operations Analysis be judged as current execution be short block MDCT computing the time, described arithmetic element under the control of described Operations Analysis and described logic control element with short block DCT-IV operation result, i.e. short block MDCT operation result output;

When described Operations Analysis be judged as current execution be long piece MDCT computing the time, described arithmetic element is the aftertreatment of executive chairman's piece under the control of described Operations Analysis and described logic control element, described long piece aftertreatment will long piece three DCT-IV operation results convert 18 DCT-IV operation result to, promptly long piece MDCT operation result output;

When described Operations Analysis be judged as current execution be long piece IMDCT computing the time, described arithmetic element is the aftertreatment of executive chairman's piece under the control of described Operations Analysis and described logic control element, and three DCT-IV operation results that described long piece aftertreatment will long piece convert 18 DCT-IV operation result to; And carry out the IMDCT aftertreatment, described IMDCT aftertreatment converts described DCT-IV operation result the output of to IMDCT operation result at 18;

When described Operations Analysis be judged as current execution be short block IMDCT computing the time, described arithmetic element is carried out the IMDCT aftertreatment under the control of described Operations Analysis and described logic control element, described IMDCT aftertreatment converts short block DCT-IV operation result the output of to IMDCT operation result.

46. the coding/decoding system according to claim 44 or 45 described audio digital signals is characterized in that, described Operations Analysis comprises:

Length piece judgment sub-unit is used to judge that the digital signal of input is long piece or short block;

The encoding and decoding judgment sub-unit, what be used to judge current execution is MDCT computing or IMDCT computing;

Counter;

The main control state machine is connected with described length piece judgment sub-unit, described encoding and decoding judgment sub-unit, described counter, is used to judge calculation mode, and the state exchange of control calculating;

The arithmetic element control signal generates subelement, is connected with described main control state machine, described counter, is used to generate the s operation control signal; And

Coefficient generates subelement, generates subelement with described arithmetic element control signal and is connected, and is used for generating the access signal of calculating process fixed coefficient.

47. the coding/decoding system according to the described audio digital signals of claim 46 is characterized in that, described Operations Analysis also comprises:

Auxiliary control signal generates subelement, and it is connected with the control signal generation unit of described arithmetic element, is used to generate the auxiliary operation control signal, and described auxiliary operation control signal comprises length block mark and/or encoding and decoding sign.

48. the coding/decoding system according to the described audio digital signals of claim 46 is characterized in that, described logic control element comprises:

The state exchange logic is used for controlling the state exchange of calculating process between each nonidentity operation stage;

MDCT pre-treatment control circuit is used for the described arithmetic element of the common control of described Operations Analysis the encoded data stream of importing being carried out the MDCT pre-treatment;

Long piece pre-treatment control circuit is used for and the long blocks of data stream long piece pre-treatment of the described arithmetic element of the common control of described Operations Analysis to input;

Multiplexing arithmetic element control circuit is used to control multiplexing to described arithmetic element;

Long piece aftertreatment control circuit is used for and the long blocks of data stream long piece aftertreatment of the described arithmetic element of the common control of described Operations Analysis after to computing; And

IMDCT aftertreatment control circuit is used for the described arithmetic element of the common control of described Operations Analysis result of decoding operation being carried out the IMDCT aftertreatment.

49. the decode system according to the described audio digital signals of claim 46 is characterized in that, described arithmetic element comprises:

RAM is used to store the digital signal for the treatment of the encoding and decoding computing and the intermediate operations result of input;

ROM is used to store operation coefficient;

First register, its input end is connected with described RAM;

Second register, its input end is connected with described ROM;

Multiplier, two input end are connected with the output terminal of described first register and the output terminal of described second register respectively;

The 3rd register, its input end is connected with the output terminal of described multiplier;

First selector, its first data input pin is connected with the output terminal of described first register;

Second selector, its first data input pin is connected with the output terminal of described first register, and second data input pin is connected with the output terminal of described the 3rd register;

Add/subtracter, two input end is connected with the output terminal of described first selector and the output terminal of described second selector respectively;

The 4th register, its input end is connected with the output terminal of described adding/subtracter, and its output terminal is connected with second data input pin of described first selector;

Address control unit, it is connected with described ROM with described RAM, is used to generate the address of access data;

The register selected cell, it is connected with described first register, second register, the 3rd register, the 4th register and described registers group, is used to select to participate in the register of computing;

The multiplier control module, it is connected with described multiplier, is used to control the computing of described multiplier;

The selector switch control module, it is connected with described second selector with described first selector, is used for from the data selection suitable data output of two inputs of described first selector and described second selector;

Add/the subtracter control module, it is connected with described adding/subtracter, is used to control the computing of described adding/subtracter.

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