CN102238776B - Calibration device and method, multichannel driving circuit and current balancing method thereof - Google Patents
Calibration device and method, multichannel driving circuit and current balancing method thereof Download PDFInfo
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- CN102238776B CN102238776B CN201010170188.6A CN201010170188A CN102238776B CN 102238776 B CN102238776 B CN 102238776B CN 201010170188 A CN201010170188 A CN 201010170188A CN 102238776 B CN102238776 B CN 102238776B
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- 238000013519 translation Methods 0.000 description 4
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Abstract
The invention discloses a calibration method which is used for adjusting an offset voltage of a unit to be calibrated. The unit to be calibrated comprises a first input end, a second input end and an output end and can be operated in a calibration mode and a normal mode. The calibration method comprises the following steps of: switching the unit to be calibrated into the calibration mode; providing a programmable voltage to the first input end; providing a fixed voltage to the second input end; monotonously adjusting the programmable voltage when the output state of the output end is not changed; latching the programming voltage value when the output state is changed; and switching the unit to be calibrated into the normal mode when the output state is changed.
Description
Technical field
The present invention relates to a kind of calibrating installation and method thereof.
Background technology
For a light-emitting diode (Light Emitting Diode, LED) drive unit, current balance type (Current Balance) is a critical specifications.The general specification requirement uniformity need be in 1%.Yet the electronic building brick using in LED drive unit, may cause reaching the requirement of current balance type specification because of the variation of Fabrication parameter in manufacture process.
The existing multichannel LED drive circuit 100 of Fig. 1 illustration one.Input voltage V
inby power switch M
1and boosting unit 11 progressively boosts to luminescence unit 13 and the required voltage of luminescence unit 14.Multichannel drive circuit 12 is controlled the transistor M of corresponding flow through luminescence unit 13 and luminescence unit 14 by current driving circuit 15 and 16
3and M
4channel current.Current driving circuit 15 and 16 is self check measuring resistance R relatively
1and R
2the voltage signal of institute's feedback and a reference voltage V
rEF, dynamically control corresponding channel current, and then stable flow is through resistance R
1and R
2electric current.Ideally, as long as resistance R
1and R
2have the same resistance value, the electric current of that flow through luminescence unit 13 and luminescence unit 14 will be the same, reaches current balance type.
Yet, the error amplifier OPA in multichannel LED drive circuit 100
1and OPA
2it may not desirable assembly.Because of the relation on manufacturing, error amplifier OPA
1and OPA
2may there is different offset voltage (Offset Voltage).This different offset voltage may cause this multichannel LED drive circuit cannot meet the requirement of current balance type specification.
Summary of the invention
The invention provides a kind of calibrating installation and method thereof.Of the present invention one implements example discloses a kind of calibrating installation, and it can be in order to compensate an offset voltage of a unit to be calibrated.This unit to be calibrated includes a first input end, one second input and an output.This calibrating installation includes a counter, a programmable voltage generation unit and a latch cicuit.This counter is in order to provide and to change monotonously a digital signal.This programmable voltage generation unit, according to one first input voltage and this digital signal, produces a programmable voltage in this first input end.This latch cicuit, when the output state of this output changes, latchs this digital signal and produces one and latch rear digital signal, so that this programmable voltage is affected by this counter no longer.The second above-mentioned input receives one second input voltage, and the difference of this first and second input voltage is approximately a fixed value.
Of the present invention another implemented example and disclosed a kind of calibration steps, and it is in order to adjust the offset voltage (Offset Voltage) of a unit to be calibrated.This unit to be calibrated includes the first and second input, and an output, and it can operate in a calibration mode and a normal mode.This calibration steps comprises the following step: switch this unit to be calibrated in this calibration mode; Provide a programmable voltage, to this first input end; Provide a fixed voltage to this second input; When the output state of this output does not change, adjust monotonously this programmable voltage; When this output state changes, latch this program voltage value; And when this output state changes, switch this unit to be calibrated in this normal mode.
An enforcement example more of the present invention discloses a kind of multichannel drive circuit, and it can reach current balance type (Current Balancing) effect.This multichannel drive circuit includes a plurality of current driving circuits.Every one drive circuit is controlled voltage according to a channel current, controls a corresponding channel current.Every one drive circuit includes a comparator, a latch cicuit and a bucking voltage generator.This comparator has first and second input, and an output.This output can be controlled this respective channel electric current.This latch cicuit is in order to provide one to latch rear digital signal.This bucking voltage generator latchs rear digital signal according to this, produces a bucking voltage.This first and second input one of them, receive the summation of this bucking voltage and one first input voltage.Wherein another of this first and second input, receives one second input voltage.This first with this second input voltage one of them, to should respective channel electric current.This first with wherein another of this second input voltage, be that this channel current is controlled voltage.
An enforcement example more of the present invention discloses a kind of current balance type (Current Balancing) method, is applicable to drive a plurality of channels.The method comprises and changes monotonously a digital signal.For each passage is carried out to following action: according to this digital signal, change one bucking voltage; By this bucking voltage and one first input voltage and, input one comparator a first input end; One second input voltage is inputted to one second input of this comparator, wherein this first is approximately a fixed value with the difference of this second input voltage; When the output state of an output of this comparator changes, latch this digital signal, to produce one, latch rear digital signal; And according to this latch rear digital signal, a channel current is controlled voltage and a corresponding feedback voltage, controls this comparator, to drive a respective channels, wherein, this correspondence feedback voltage is to should respective channels electric current.
Above sketch out technical characterictic of the present invention, is obtained better understanding so that the present invention below describes in detail.Other technical characterictic that forms claim target of the present invention will be described in below.Those skilled in the art should understand, and the concept below disclosing can be used as basis with particular implementation example and revised quite easily or design other structure or technique and realize the object identical with the present invention.Those skilled in the art also should understand, and the construction of this class equivalence also cannot depart from the spirit and scope of the present invention that claim of the present invention proposes.
Accompanying drawing explanation
The existing multichannel LED drive circuit of Fig. 1 illustration one;
Fig. 2 illustration is according to an embodiment of a multichannel drive circuit of the present invention;
Fig. 3 illustration is according to an embodiment of a calibrating installation of the present invention; And
Fig. 4 illustration is according to a flow chart of a calibration steps of the present invention.
Reference numeral explanation
11 boosting units
12,22 multichannel drive circuits
13,14 luminescence units
15,16,201,202 current driving circuits
203 counters
204 pattern control units
301 latch cicuits
302 programmable voltage generation units
303,304 displacement units
305,32 adders
211,222 calibration circuits
31 digital to analog converters
L
1inductance
D
1diode
M
1～M
8transistor
C
1electric capacity
R
1～R
6resistance
X
1～X
4driver element
OAP
1～OAP
4amplifying unit
IOPA
1desirable amplifying unit
I
1～I
5, I
fcurrent source
S
1～S
9switch
301-308 step
Embodiment
Fig. 2 illustration one is according to multichannel LED drive circuit 200 of the invention process.The part that Fig. 2 is same as in figure 1, can be implemented with the same or functionally similar assembly, for those skilled in the art can know by inference easily, at this, does not repeat.As shown in Figure 2, this multichannel LED drive circuit 200 comprises a counter 203 and a pattern control unit 204, and current driving circuit 201 and 202 respectively comprises calibration circuit 211 and 222 and switch S
1and S
2.Pattern control unit 204 controllable current drive circuits 201 and 202 operate in a calibration mode or a normal mode.Take current driving circuit 201 below as example explanation, and same operation can be extrapolated to this current driving circuit 202.
When normal mode, switch S
1conducting.211 couples of reference voltage V of calibration circuit
rEF, feedback voltage V
3(for detecting resistance R
3voltage signal) or both, provide the function of fixed voltage translation (level shift), with reference to voltage V
rEFand feedback voltage V
3, be transformed into two input voltage V
i1with V
i2, export to error amplifier OPA
3.Error amplifier OPA
3control according to this transistor M
5control end, use and control the resistance R of flowing through
3electric current.So calibration circuit 211 is with error amplifier OPA
3can be considered together one and be equal to error amplifier OPA
x, its two input signal is respectively reference voltage V
rEFwith feedback voltage V
3.Reference voltage V now
rEFcan be considered as channel current and control voltage.The fixed voltage translational movement that calibration circuit 211 provides can determine when calibration mode.
When calibration mode, switch S
1open circuit.In one embodiment, calibration circuit 211 is with reference to voltage V
rEFtranslation becomes two input voltage V
i1with V
i2export to error amplifier OPA
3.In one embodiment, reference voltage V
rEFto input voltage signal V
i1voltage translational movement V
shift1can change reference voltage V according to the output of counter 203
rEFto input voltage V
i2voltage translational movement V
shift2immobilize.After calibration mode starts, counter 203 is dull rise/fall in proper order just, and the voltage translational movement V that calibration circuit 211 provides
shift1can, along with the exporting change of counter 203, increase gradually/reduce.Once error amplifier OPA
3output V
tR1change, mean and be equal to error amplifier OPA
xoffset voltage approximately to a desired value, so calibration circuit 211 latchs voltage translational movement V
shift1, make it no longer be subject to the exporting change of counter 203 and change.The exporting change of counter 203, can continue to adjust the voltage translational movement in other calibration circuit (as calibration circuit 222), until each current driving circuit just finishes after latching voltage translational movement wherein afterwards.And be latched voltage translational movement V
shift1and fixing voltage translational movement V
shift2, be just used in normal mode.So, the offset voltage that is equal to error amplifier in each current driving circuit will be approximately an identical desired value, and multichannel LED drive circuit 200 is just than the requirement that is easier to meet current balance type specification.
A kind of execution mode and the periphery associated component of the current driving circuit 201 in Fig. 2 described by the thin portion of Fig. 3.Error amplifier OPA
3imperfect amplifier, compared to ideal amplifier IOPA
1, it has an offset voltage V
os1, it is not limit and betides which input, and for ease of explanation, the present embodiment is shown in error amplifier OPA
3first input end In
1.
When calibration mode, switch S
1open circuit, switch S
9with reference to voltage V
rEFprovide to transistor M
8control end, and disconnect feedback voltage V
6(be R
6voltage signal) to transistor M
8the path of control end.
Transistor M
8and 305 couples of reference voltage V of adder
rEFtranslation becomes input voltage V
i2(at this error amplifier OPA
3the second input In
2), voltage translational movement V
shift2can draw with following formula (1):
V
shift2＝V
th8+I
f*R
R6 ------(1)
Wherein, V
th8for transistor M
8threshold value (threshold voltage), I
ffor the resistance R of flowing through
6current value, and R
r6for resistance R
6resistance value.In this embodiment, these are all constants, so voltage translational movement V
shift2for changeless constant.
Numeral is to analog circuit 31 foundation one digital signal L
d, select current source I
1-5one of them or combination are with generation analog signal current I (L
d) resistance R of flowing through
5.With transistor M
8and the similar reason of adder 305, reference voltage V
rEFtranslation becomes input voltage V
i1(at error amplifier OPA
3first input end In
1) voltage translational movement V
shift1can draw with following formula (2):
V
shift1＝V
th7+I(L
D)*R
R5 ------(2)
Wherein, V
th7for transistor M
7threshold value, and R
r5for resistance R
5resistance value.In this embodiment, because digital signal L
dthe resistance R of flowing through of having programmed
5electric current, also make input voltage V
i1it is a programmable voltage.
While entering calibration mode at the beginning, latch cicuit 301 does not latch, digital signal L
dwith digital signal S
dthe same, along with the upper number/lower number of counter 203 dullnesses, increase/reduce.Along with digital signal L
dvariation, voltage translational movement V
shift1also change, also changed input voltage V
i1.Once input voltage V
i1with V
i2difference large to enough making error amplifier OPA
3output signal V
tR1change, this output signal V
tR1change can be touched and be made latch cicuit 301 start to latch.When latch cicuit 301 latchs, digital signal L
dremain unchanged, no longer with digital signal S
dvariation and change.So, digital signal L now
dcan be considered and latch rear digital signal.
When normal mode, digital signal L
dstill keep being latched state, be not subject to output signal V
tR1impact; Switch S
1conducting; Switch S
9by feedback voltage V
6(be R
6voltage signal) deliver to transistor M
8control end.
In Fig. 3, assumption error amplifier OPA
3offset voltage V
os1equal 0.03V; Voltage translational movement V
shift1equal (0.8+L
d* 0.001) V; Voltage translational movement V
shift2for 0.85V; The digital signal S that counter 203 is exported
dthere are 5, can count to 32 from 0; Reference voltage V
rEFfor 0.5V.
In order to make those skilled in the art implement the present invention by the instruction of this enforcement example, the another enforcement example that proposes a calibration steps of above-mentioned calibrating installation 211 of below arranging in pairs or groups.Fig. 4 illustration is according to the flow chart of a calibration steps of the present invention.In the step 401 of Fig. 4, start this flow process.In step 402, by pattern control unit 204 diverter switch S
1, S
9make current driving circuit 201 enter a calibration mode.
In step 403, first input end In
1input voltage V
i1will be V
rEF+ V
shift1=1.3+L
d* 0.001 volt is one can be by digital signal L
dthe voltage of programming.The second input In
2input voltage V
i2will be V
rEF+ V
shift2=1.35 volts is a fixed voltage.Because the initial value of counter 203 is 0, so input voltage V now
i1for 1.3V, ideal amplifier IOPA
1positive and negative both end voltage poor be (1.3+0.03-1.35)=-0.02V, so output signal V
tR1for in logic 0.
In step 404, dull make on counter 203 several 1, so digital signal S
dwith L
dbecome 1, programmable input voltage V
i1the 0.001V that will rise, becomes 1.301V, and ideal amplifier IOPA
1positive and negative both end voltage poor becoming-0.019V, output signal V
tR1be still in logic 0.
In step 405, because output signal V
tR1be still in logic 0, so get back to step 404, continue to allow on counter 202 several 1.Can find, while passing through step 404 at every turn, ideal amplifier IOPA
1the poor 0.001V that just increased of positive and negative both end voltage.Can expect, step 404 and 405 the circulation meeting forming execution always, until digital signal S
dbe increased to 21, ideal amplifier IOPA
1the poor 0.001V that equals of positive and negative both end voltage, output signal V
tR1change transition become in logic 1, just enter step 406.
In step 406, latch cicuit 301 has latched digital signal L instantly
d(=21), have fixed switch S
1～S
5on off state, also equal to have latched input voltage V
i1.Subsequently, even if the upper number that counter 203 continues does not affect the digital signal L in current driving circuit 201 yet
d.Now, the voltage translational movement V in current driving circuit 201
shift1be fixed as exactly (0.8+21*0.001)=0.821V, and voltage translational movement V
shift2still 0.85V.Be equal to error amplifier OPA
xthe offset voltage of two inputs, be approximately now 0.001V (=V
shift1+ V
os1-V
shift2=0.821+0.03-0.85).
In step 407, by pattern control unit 204 diverter switch S
1, S
9, make this unit OPA to be calibrated
3get back to if the state in the current driving circuit 15 and 16 of Fig. 1 is to operate in a normal mode.
Finally, process ends in step 408.The current driving circuit of the above step of every process, the offset voltage that is equal to error amplifier wherein, can be desirably between 0 to 0.001V, very approach 0V.Also therefore, than the requirement that is easier to meet current balance type specification.
In the embodiment of Fig. 3, programmable voltage translational movement is to provide in error amplifier OPA
3anode.In another embodiment, programmable voltage translational movement is to provide in error amplifier OPA
3negative terminal.In the embodiment of Fig. 3, during normal running, reference voltage V
rEFwith feedback voltage V
3be couple to respectively error amplifier OPA
3positive and negative terminal; In another embodiment, can exchange.
In the embodiment of Fig. 3, when calibration mode, transistor M
7with M
8control end all receive same reference voltage V
rEF.In another embodiment, transistor M
7with M
8control end receive respectively different two voltages, but the difference of this two voltage is approximately a fixed value.
General drive circuit, has so-called slow start-up routine (soft start procedure).Take Fig. 2 as example, and slow start-up routine may progressively increase V
outoperating voltage, to luminescence unit 13 and the required voltage of luminescence unit 14.During slow start-up routine step, luminescence unit 13 and luminescence unit 14 are not supplied to induced current.And calibration mode in Fig. 4, during may operate in the step of carrying out slow start-up routine.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to implement the content that example discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by claim of the present invention.
Claims (7)
1. a calibration steps, it is in order to adjust the offset voltage of a unit to be calibrated, wherein, this unit to be calibrated can operate in a calibration mode and a normal mode, include the first and second input, and an output, this calibration steps comprises the following step:
Switch this unit to be calibrated in this calibration mode;
Provide a programmable voltage, to this first input end;
Provide a fixed voltage to this second input;
When the output state of this output does not change, adjust monotonously this programmable voltage;
When this output state changes, latch this program voltage value; And
When this output state changes, switch this unit to be calibrated in this normal mode.
2. calibration steps according to claim 1, wherein adjusts the step of this programmable voltage monotonously, comprises:
One digital signal is provided;
Gradually reduce or increase this digital signal; And
This digital signal is converted to this programmable voltage.
3. calibration steps according to claim 2, wherein latchs the step of this program voltage value, includes to latch this digital signal and produce one and latchs rear digital signal, so that this programmable voltage is no longer subject to the variation of this digital signal and affects.
4. calibration steps according to claim 1, it also comprises carries out a slow start-up routine, progressively to increase supply voltage to one operational voltage value of a load unit, during wherein this calibration mode operates in the step of carrying out this slow start-up routine.
5. a calibrating installation, can be in order to compensate an offset voltage of a comparator, and this comparator includes a first input end, one second input and an output, and this calibrating installation includes:
One counter, provides and changes monotonously a digital signal;
One programmable voltage generation unit, according to one first input voltage and this digital signal, produces a programmable voltage in this first input end; And
One latch cicuit, when the output state of this output changes, latchs this digital signal and produces one and latch rear digital signal, so that this programmable voltage is affected by this counter no longer;
Wherein, this second input receives one second input voltage, and the difference of this first and second input voltage is a fixed value.
6. calibrating installation according to claim 5, wherein this second input voltage equals this first input voltage.
7. calibrating installation according to claim 5, wherein this programmable voltage generation unit includes:
One digital to analog converter, according to this digital signal, produces a corresponding analog signal; And
One adder, is added this correspondence analog signal and this first input voltage, to produce this programmable voltage.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010170188.6A CN102238776B (en) | 2010-04-21 | 2010-04-21 | Calibration device and method, multichannel driving circuit and current balancing method thereof |
| CN201310564181.6A CN103547047B (en) | 2010-04-21 | 2010-04-21 | Calibrating installation, method and multichannel drive circuit thereof and current balance method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010170188.6A CN102238776B (en) | 2010-04-21 | 2010-04-21 | Calibration device and method, multichannel driving circuit and current balancing method thereof |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310564181.6A Division CN103547047B (en) | 2010-04-21 | 2010-04-21 | Calibrating installation, method and multichannel drive circuit thereof and current balance method |
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| Publication Number | Publication Date |
|---|---|
| CN102238776A CN102238776A (en) | 2011-11-09 |
| CN102238776B true CN102238776B (en) | 2014-04-23 |
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| CN201310564181.6A Expired - Fee Related CN103547047B (en) | 2010-04-21 | 2010-04-21 | Calibrating installation, method and multichannel drive circuit thereof and current balance method |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014009861A2 (en) * | 2012-07-09 | 2014-01-16 | Koninklijke Philips N.V. | Method of controlling a lighting device |
| KR102066604B1 (en) * | 2012-12-26 | 2020-02-11 | 에스케이하이닉스 주식회사 | Comparator circuit and method for comparating signals |
| US9385695B2 (en) * | 2014-06-06 | 2016-07-05 | Qualcomm Incorporated | Offset calibration for low power and high performance receiver |
| CN107040249B (en) * | 2017-03-29 | 2021-01-12 | 湖南汇德电子有限公司 | Circuit for trimming and judging reverse voltage threshold of comparator |
| CN107196629B (en) * | 2017-05-04 | 2020-10-23 | 深圳大学 | Discrete threshold voltage comparator with zero static power consumption |
| CN107134990B (en) * | 2017-05-04 | 2020-09-15 | 深圳大学 | Discrete threshold voltage comparator with zero static power consumption |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6687169B2 (en) * | 2000-05-31 | 2004-02-03 | Hyundai Electronics Industries Co., Ltd. | Semiconductor memory device for providing address access time and data access time at a high speed |
| CN101286697A (en) * | 2007-04-10 | 2008-10-15 | 沛亨半导体股份有限公司 | Signal generating device and related method |
| CN101686057A (en) * | 2008-09-28 | 2010-03-31 | 扬智科技股份有限公司 | Digital analogue converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6631338B2 (en) * | 2000-12-29 | 2003-10-07 | Intel Corporation | Dynamic current calibrated driver circuit |
| CN101060731A (en) * | 2006-04-17 | 2007-10-24 | 硕颉科技股份有限公司 | LED current balancing circuit |
| TW200826737A (en) * | 2006-12-01 | 2008-06-16 | Delta Electronics Inc | Muti-lamp drive system and current balance circuit thereof |
-
2010
- 2010-04-21 CN CN201010170188.6A patent/CN102238776B/en not_active Expired - Fee Related
- 2010-04-21 CN CN201310564181.6A patent/CN103547047B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6687169B2 (en) * | 2000-05-31 | 2004-02-03 | Hyundai Electronics Industries Co., Ltd. | Semiconductor memory device for providing address access time and data access time at a high speed |
| CN101286697A (en) * | 2007-04-10 | 2008-10-15 | 沛亨半导体股份有限公司 | Signal generating device and related method |
| CN101686057A (en) * | 2008-09-28 | 2010-03-31 | 扬智科技股份有限公司 | Digital analogue converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102238776A (en) | 2011-11-09 |
| CN103547047A (en) | 2014-01-29 |
| CN103547047B (en) | 2015-11-04 |
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