CN102223490B - Digital switching matrix supporting synchronic switching and synchronic switching method of digital image - Google Patents
Digital switching matrix supporting synchronic switching and synchronic switching method of digital image Download PDFInfo
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Abstract
The invention discloses a digital switching matrix supporting synchronic switching, which comprises an input card, an output card, a switching backplate and a control interface plate, wherein the input card comprises a receiving module and an input interface, the input of the receiving module is connected with the input interface, and the output end of the receiving module is connected with the input of the switching chip of the switching backplate; the output card comprises an image optimization module, a transmission module and an output interface; the input of the transmission module is connected with the output end of the image optimization module, and the output end of the transmission module is connected with the output interface; the switching backplate comprises the switching chip, a CPU (Central Processing Unit) chip, an FPGA (Field Programmable Fata Array) chip and a synchronic separation chip, the output end of the switching chip is connected with the input end of the image optimization module, and is also connected to the serdes interface of an FPGA, the output of the synchronic separation chip is connected with the FPGA; and the control interface plate comprises an RS485 synchronic signal receiving chip, an external BNC (Bayonet Nut Connector) interface and an RS232 and/or RS485 receiving chip. By the invention, the problem that during the video image switching process, the transmission is delayed and the images are not stable can be solved, and the visual impact to a user during the image switching process can be avoided.
Description
Technical field
The present invention relates to the video technique field, relate in particular to a kind of digital switching matrix of synchronously switching and method for synchronously switching of digital picture supported.
Background technology
At present, the core exchange chip that the image exchange matrix on the market adopts has the schemes such as FPGA, Crosspoint Switch chip, and wherein, the FPGA scheme need to be gone here and there and conversion and encoding and decoding to video data, can bring delay to the transmission of video.
Simultaneously, the switching mode of video image is directly finished handover operation according to switching command mostly at present, so, image unsure state may occur in the process of switching, even of short duration blank screen phenomenon can appear, thus bring visual impact, affect viewing effect.
In addition, the switching matrix product that in the market minority support is switched synchronously, basically be based on the FPGA handover scheme, such scheme one is to bring time-delay, the 2nd, the synchronisation source of the type is from interiors of products, can only be used for the inter-sync of single product, be difficult to and external other Realization of Product simultaneous operations, have significant limitation.
Summary of the invention
The purpose of the embodiment of the invention is the defective that exists for existing digital video image handoff technique, a kind of high bandwidth digital switching matrix of synchronously switching and method for synchronously switching of digital picture supported is provided, to solve the problems such as the image time-delay that brings in the image switching process, judder, and provide the method for synchronous of the digital switching matrix that switches synchronously based on above support, in actual applications, described digital switching matrix can be supported different synchronous modes according to different applied environments.
In order to reach the foregoing invention purpose, the embodiment of the invention has proposed a kind of synchronously digital switching matrix of switching of supporting, the digital switching matrix that described support is switched synchronously is to realize by following technical scheme:
A kind of synchronously digital switching matrix of switching of supporting, described digital switching matrix comprises: input card, output card, switching backplane, control interface plate, wherein,
Described input card comprises receiver module, input interface, and the input of described receiver module links to each other with input interface, and output links to each other with the input of the exchange chip of described switching backplane;
Described output card comprises image optimization module, sending module and output interface, and the input of described sending module links to each other with the output of image optimization module, and output links to each other with output interface;
Described switching backplane comprises exchange chip, cpu chip, fpga chip, Sync Separator Chip, the output of described exchange chip links to each other with the input of image optimization module, the output of exchange chip also connects one road to FPGA serdes interface, and the output of described Sync Separator Chip links to each other with FPGA;
Described control interface plate comprises RS485 interface, external bnc interface, and RS232 and/or RS485 interface.
Further preferably, described receiver module comprises and receives optical module and/or cable equalizer chip.
Further preferably, described input interface comprises BNC input interface and/or LC/PC light input interface.
Further preferably, described sending module comprises and sends optical module and/or driver chip.
Further preferably, described output interface comprises BNC output interface and/or LC/PC light output interface.
Further preferably, described exchange chip comprises specialized high-speed Crosspoint Switch exchange chip.
In order to realize aforementioned goal of the invention, the embodiment of the invention has also proposed a kind of method for synchronously switching based on the synchronous digital switching matrix that switches of above support, and described method is achieved through the following technical solutions:
A kind of method for synchronously switching of digital picture of the digital switching matrix that switches synchronously based on above support, described method is achieved through the following technical solutions:
A kind of method for synchronously switching of digital picture said method comprising the steps of:
When needs carried out the handover operation of digital picture, CPU received operational order, sent into FPGA after the described operational order that receives is resolved;
The FPGA that is in pending coomand mode detects the synchronisation source signal, and judges the current territory, place that is in of described synchronisation source after receiving operational order after the parsing;
When detecting the vertical blanking period arrival, FPGA sends out fill order to exchange chip;
Exchange chip is carried out handover operation in vertical blanking period, finish the handover operation of described digital picture.
Further preferably, described method also comprises:
According to the needs of practical application, select the synchronous mode of described digital picture in advance.
Further preferably, described synchronous mode comprises:
The synchronisation source input of external RS485 electrical characteristic, described synchronisation source comprises row, field sync signal, through directly entering FPGA behind the RS485 receiving chip, separates trip, field sync signal by FPGA;
Or external simulation synchronisation source input, separate trip, field sync signal by Sync Separator Chip, input FPGA;
Or switch one road input video to the serdes of FPGA input by exchange chip, decompose trip, field signal by FPGA.
Compared with prior art, the high bandwidth digital switching matrix that the support that the embodiment of the invention provides is switched synchronously and the method for synchronously switching of digital picture, transmission delay when having solved the video image switching and the problem of judder, avoid the visual impact that in the image switching process user caused, prolonged to a certain extent the life-span of back equipment; Support that simultaneously the multiple synchronization pattern is optional, guaranteed the image synchronization handoff functionality; In addition, embodiment of the invention technical scheme is supported optical fiber access and optical fiber output, can conveniently be applied to long-distance transmissions; Simultaneously, the embodiment of the invention adopts the card insert type design, but different interface type and the switching capacities of flexible configuration.
Description of drawings
By the description of its exemplary embodiment being carried out below in conjunction with accompanying drawing, the above-mentioned feature and advantage of the present invention will become apparent and understand easily.
Fig. 1 is that 1 one kinds of the embodiment of the invention are supported the synchronously system construction drawing of the digital switching matrix of switching;
Fig. 2 is that 2 one kinds of the embodiment of the invention are supported the synchronously System Implementation figure of the digital switching matrix of switching;
Fig. 3 is that 3 one kinds of the embodiment of the invention are supported synchronously system's rearview of the digital switching matrix of switching;
Fig. 4 is the method for synchronously switching flow chart of 4 one kinds of digital pictures of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail.
As shown in Figure 1, support the synchronously system construction drawing of the digital switching matrix of switching for 1 one kinds of the embodiment of the invention, the digital switching matrix that described support is switched synchronously can adopt the card insert type design, with flexible configuration different interface type and switching capacity.
Specifically comprise:
A kind of synchronously digital switching matrix of switching of supporting, described digital switching matrix comprises: input card, output card, switching backplane, control interface plate, wherein,
Described input card comprises receiver module, input interface, and the input of described receiver module links to each other with input interface, and output links to each other with the input of the exchange chip of described switching backplane;
Described output card comprises image optimization module, sending module and output interface, and the input of described sending module links to each other with the output of image optimization module, and output links to each other with output interface;
Described switching backplane comprises exchange chip, cpu chip, fpga chip, Sync Separator Chip, the output of described exchange chip links to each other with the input of image optimization module, the output of exchange chip also connects one road to FPGA serdes interface, and the output of described Sync Separator Chip links to each other with FPGA;
Described control interface plate comprises RS485 interface, external bnc interface, and RS232 and/or RS485 interface.
Further preferably, described receiver module comprises and receives optical module and/or cable equalizer chip.
Further preferably, described input interface comprises BNC input interface and/or LC/PC light input interface.
Further preferably, described sending module comprises and sends optical module and/or driver chip.
Further preferably, described output interface comprises BNC output interface and/or LC/PC light output interface.
Further preferably, described exchange chip comprises specialized high-speed Crosspoint Switch exchange chip.
Further preferably, described image optimization module comprises the Reclock chip.
Thereby avoided the problems such as picture delay that adopt the FPGA scheme to cause, simultaneously, the handoff response time is also a lot of soon than FPGA scheme.
As shown in Figure 2, support the synchronously digital switching matrix implementation figure of switching for the embodiment of the invention 2, support the synchronous high bandwidth digital switching matrix that switches, adopt card insert type design, comprise input card, output card, switching backplane, control interface plate.
Described input card comprises two types of bnc interface input card and optical interface input cards, and wherein the bnc interface input card comprises BNC input interface 1, cable equalizer chip 2;
The optical interface input card comprises LC/PC light input interface 3, receives optical module 4.
Described output card comprises two types of bnc interface output card and optical interface output cards, and wherein the bnc interface output card comprises Reclock chip 5, driver chip 6, BNC output interface 7; The optical interface output card comprises Reclock chip 5, sends optical module 8, LC/PC light output interface 9.
Described switching backplane comprises exchange chip 10, cpu chip 16, fpga chip 15, synchronisation source input bnc interface 11, synchronisation source input difference interface 13, Sync Separator Chip 12, RS485 receiving chip 14;
According to System Implementation figure shown in Figure 2, BNC input interface 1 on the input card or LC/PC light input interface 3 link to each other with the input of cable equalizer chip 2 or reception optical module 4, the input of exchange chip 10 links to each other on equalizer chip 2 or the output that receives optical module 4 and the switching backplane, the input of the Reclock chip 5 on the output of exchange chip 10 and the output card links to each other, the output of the Reclock chip 5 on the output card links to each other with the input of driver chip 6 or transmission optical module 8, and the output of driver chip 6 or transmission optical module 8 links to each other with BNC output interface 7 or LC/PC light output interface 9;
Outside RS485 synchronisation source input interface 13 links to each other with RS485 receiving chip 14, then is input to FPGA15; Outside input synchronisation source bnc interface 11 links to each other with Sync Separator Chip 12, and the output of Sync Separator Chip 12 links to each other with FPGA15; The output of exchange chip 10 also connects one road to FPGA15 serdes interface; Line ball stand 26 and line ball stand 28 are respectively RS232 and RS485 communication interface, link to each other with RS485 receiving chip 27 with RS232 receiving chip 25; The output of RS232 receiving chip 25 and RS485 receiving chip 27 links to each other with CPU16 respectively; The chip that needs to control in CPU16 and the system links to each other.
As shown in Figure 3, be the product rearview of this inventive embodiments 3, communication interface 17 comprises two types, is respectively RS232 and RS485 interface, and two interfaces are separate, can use simultaneously; Power interface 18 is supported 220V AC access; Synchronisation source difference input interface 19 supporting rings go out; Synchronisation source BNC input interface 20 supporting rings go out; Optical interface input card 21, bnc interface input card 22 can access use simultaneously; Optical interface output card 23, bnc interface output card 24 can access use simultaneously; Increased the flexibility of interface configuration, more convenient to use.
According to System Implementation figure shown in Figure 2, described equalizer chip 2 models can be that LMH0344, M21324 or LMH0394 support maximum 200m cable access; Exchange chip 10 models can be M21121; Reclock chip 5 models can be M21250; Driver chip 6 models can be M21328, LMH0303; Described reception optical module 4, transmission optical module 8 can be the 3.2Gbps optical module, and wavelength is 1470-1610nm; FPGA15 is Lattice ECP2 Series FPGA chip; CPU16 can select the STM32 family chip; Sync Separator Chip 12 can be selected LMH1981; RS485 receiving chip 1427 models can be ISL83075; The RS232 receiving chip is MAX3232; Bnc interface 1711 can be 75 ohm of BNC female seats; Differential interface 13 can be 3pin straight cutting junction block; Line ball stand 2628 can be 3pin straight cutting junction block.
In order better to realize synchronous handoff functionality, guarantee can not bring unnecessary visual impact to the user in the image switching process, and the problem of judder, the embodiment of the invention requires video source and the complete field synchronization of synchronisation source of input.
The digital switching matrix that the support that the technical scheme of the above embodiment of the present invention provides is switched synchronously can be supported three kinds of synchronous modes:
1 outer synchronisation source is inputted by differential interface, through entering fpga chip after the conversion of RS485 receiving chip;
2 outer synchronisation sources are inputted by bnc interface, behind Sync Separator Chip LMH1981, with the synchronizing signal input fpga chip of LMH1981 output;
3 switch one tunnel serdes that outputs to FPGA with the video source of input by exchange chip, then solve synchronizing signal by FPGA, use as synchronisation source; When the handover operation order is arranged, FPGA will finish at vertical blanking period the execution of switching command.
According to above-mentioned synchronous requirement, the video source field synchronization that the outer synchronisation source of input must and be inputted, the video source of all inputs also must field synchronizations.
According to above-mentioned scheme, this supports maximum 4 input cards of high bandwidth digital switching matrix product support, 32 road video inputs of synchronously switching, supports maximum 4 output cards, the output of 32 road videos; Support bnc interface card and optical interface card to mix simultaneously use.
Compared with prior art, the high bandwidth digital switching matrix that the support that the embodiment of the invention provides is switched synchronously, transmission delay when having solved the video image switching and the problem of judder, avoid the visual impact that in the image switching process user caused, prolonged to a certain extent the life-span of back equipment; Support that simultaneously the multiple synchronization pattern is optional, guaranteed the image synchronization handoff functionality; In addition, embodiment of the invention technical scheme is supported optical fiber access and optical fiber output, can conveniently be applied to long-distance transmissions; Simultaneously, the embodiment of the invention adopts the card insert type design, but different interface type and the switching capacities of flexible configuration.
As shown in Figure 4, the embodiment of the invention 4 also provides a kind of method for synchronously switching of digital picture, said method comprising the steps of:
S101. in the time need to carrying out the handover operation of digital picture, CPU receives operational order, sends into FPGA after the described operational order that receives is resolved;
S102. the FPGA that is in pending coomand mode detects the synchronisation source signal, and judges the current territory, place that is in of described synchronisation source after receiving operational order after the parsing;
S103. when detecting the vertical blanking period arrival, FPGA sends out fill order to exchange chip;
S104. exchange chip is carried out handover operation in vertical blanking period, finishes the handover operation of described digital picture.
Further preferably, described method also comprises:
According to the needs of practical application, select the synchronous mode of described digital picture in advance.
Further preferably, described synchronous mode comprises:
The synchronisation source input of external RS485 electrical characteristic, described synchronisation source comprises row, field sync signal, through directly entering FPGA behind the RS485 receiving chip, separates trip, field sync signal by FPGA;
Or external simulation synchronisation source input, separate trip, field sync signal by Sync Separator Chip, input FPGA;
Or switch one road input video to the serdes of FPGA input by exchange chip, decompose trip, field signal by FPGA.
The digital switching matrix that the support that above embodiment provides according to the present invention is switched synchronously, its workflow is as follows:
32 road input videos at first are input to equalizer chip 2 by the bnc interface 1 on the input card or LC/PC optical interface 3 or receive optical module 4 and carry out equilibrium amplification processing or opto-electronic conversion processing;
Enter again the exchange chip 10 of switching backplane through the video data after balanced amplification processing or the opto-electronic conversion processing, 32 road videos of 10 pairs of inputs of exchange chip carry out 32 * 32 synchronous handover operation, and the video image after will switching outputs to the Reclock chip 5 of output card by corresponding output pin;
Carry out de-jitter by the 5 pairs of images that will export of Reclock chip, the video index of output image is optimized;
And then be sent to driver chip 6 or send optical module 8 and drive or opto-electronic conversion, at last by the bnc interface 7 on the output card or LC 9 outputs of PC optical interface.
According to System Implementation figure shown in Figure 2, Reclock chip 5 on the output card has the self adaptation lock function, can 270Mbps, 1.485Gbps, the 2.97Gbps data transfer rate video of input automatically be detected and lock, and different forms made different configurations, to adapt to the index request of different-format.
According to system construction drawing shown in Figure 2, the embodiment of the invention comprises three kinds of synchronous modes:
1, the synchronisation source of external RS485 electrical characteristic input, this synchronisation source comprises row, field synchronization information, through directly entering FPGA15 behind the RS485 receiving chip 14, separates trip, field signal by FPGA15;
2, external simulation synchronisation source input separates trip, field sync signal by Sync Separator Chip 12LMH1981, and sends into FPGA15;
3, switch one road input video to the serdes input of FPGA15 by exchange chip 10, then separate trip, field signal by FPGA15.
According to System Implementation figure shown in Figure 2, the synchronous switching implementation of this inventive embodiments 3 is as follows:
At first according to actual application environment, and actual demand is selected arbitrarily a kind of in three kinds of synchronous modes;
When having handover operation to carry out, at first upper layer software (applications) says the word to CPU16, and the operational order after CPU16 will resolve is sent into FPGA15;
At this moment, FPGA15 is in pending coomand mode, then begins the field sync signal, and judges the current territory, place that is in of video;
When detecting the vertical blanking period arrival, FPGA15 at once says the word and carries out handover operations to exchange chip 10; This exchange chip 10 carries out that the time of handover operations is very short, and all operations is all finished at vertical blanking period, has avoided the loss of image data that might bring in the handoff procedure and the problem of judder.
Compared with prior art, the embodiment of the invention provides the digital picture method for synchronously switching based on the high bandwidth digital switching matrix of supporting to switch synchronously, transmission delay when having solved the video image switching and the problem of judder, avoid the visual impact that in the image switching process user caused, prolonged to a certain extent the life-span of back equipment; Support that simultaneously the multiple synchronization pattern is optional, guaranteed the image synchronization handoff functionality; In addition, embodiment of the invention technical scheme is supported optical fiber access and optical fiber output, can conveniently be applied to long-distance transmissions; Simultaneously, the embodiment of the invention adopts the card insert type design, but different interface type and the switching capacities of flexible configuration.
One of ordinary skill in the art of the present invention are appreciated that; the above embodiment of the present invention only is one of the preferred embodiments of the present invention; be the length restriction; here can not all execution modes of particularize; any enforcement that can embody claim technical scheme of the present invention is all in protection scope of the present invention.
It should be noted that; above content is the further description of the present invention being done in conjunction with concrete execution mode; can not assert that the specific embodiment of the present invention only limits to this; under above-mentioned guidance of the present invention; those skilled in the art can carry out various improvement and distortion on the basis of above-described embodiment, and these improvement or distortion drop in protection scope of the present invention.
Claims (7)
1. support the synchronously digital switching matrix of switching for one kind, it is characterized in that described digital switching matrix comprises: input card, output card, switching backplane, control interface plate, wherein,
Described input card comprises receiver module, input interface, and the input of described receiver module links to each other with input interface, and output links to each other with the input of the exchange chip of described switching backplane;
Described output card comprises image optimization module, sending module and output interface, and the input of described sending module links to each other with the output of image optimization module, and output links to each other with output interface;
Described switching backplane comprises exchange chip, cpu chip, fpga chip, Sync Separator Chip, the output of described exchange chip links to each other with the input of image optimization module, the output of exchange chip also connects one road to FPGA serdes interface, and the output of described Sync Separator Chip links to each other with FPGA;
Described control interface plate comprises RS485 interface, external bnc interface, and RS232 and/or RS485 interface;
Described digital switching matrix is realized three kinds of synchronous modes:
A, outer synchronisation source are inputted by differential interface, through entering fpga chip after the conversion of RS485 receiving chip;
B, outer synchronisation source are inputted by bnc interface, through after the Sync Separator Chip, with the synchronizing signal input fpga chip of Sync Separator Chip output;
C, the video source of input is switched one tunnel serdes that outputs to FPGA by exchange chip, then solve synchronizing signal by FPGA, use as synchronisation source; When the handover operation order is arranged, FPGA will finish at vertical blanking period the execution of switching command.
2. digital switching matrix according to claim 1 is characterized in that, described receiver module comprises reception optical module and/or cable equalizer chip.
3. digital switching matrix according to claim 2 is characterized in that, described input interface comprises BNC input interface and/or LC/PC light input interface.
4. digital switching matrix according to claim 1 is characterized in that, described sending module comprises transmission optical module and/or driver chip.
5. digital switching matrix according to claim 4 is characterized in that, described output interface comprises BNC output interface and/or LC/PC light output interface.
6. according to claim 1 to the described digital switching matrix of 5 any one, it is characterized in that described exchange chip comprises specialized high-speed Crosspoint Switch exchange chip.
7. the method for synchronously switching of a digital picture is characterized in that, said method comprising the steps of:
When needs carried out the handover operation of digital picture, CPU received operational order, sent into FPGA after the described operational order that receives is resolved;
The FPGA that is in pending coomand mode detects the synchronisation source signal, and judges the current territory, place that is in of described synchronisation source after receiving operational order after the parsing;
When detecting the vertical blanking period arrival, FPGA sends out fill order to exchange chip;
Exchange chip is carried out handover operation in vertical blanking period, finish the handover operation of described digital picture;
According to the needs of practical application, select the synchronous mode of described digital picture in advance;
Described synchronous mode comprises:
The synchronisation source input of external RS485 electrical characteristic, described synchronisation source comprises row, field sync signal, through directly entering FPGA behind the RS485 receiving chip, separates trip, field sync signal by FPGA;
Or external simulation synchronisation source input, separate trip, field sync signal by Sync Separator Chip, input FPGA;
Or switch one road input video to the serdes of FPGA input by exchange chip, decompose trip, field signal by FPGA.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107645638A (en) * | 2017-09-22 | 2018-01-30 | 北京嗨动视觉科技有限公司 | Video processor and backplane communication method |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102752543A (en) * | 2012-07-27 | 2012-10-24 | 北京威泰嘉业科技有限公司 | Seamless switching method and seamless switching system of high-definition hybrid matrix |
| CN104702860B (en) * | 2015-03-19 | 2017-12-05 | 深圳市载德光电技术开发有限公司 | Video image switching system based on FPGA |
| CN107666580B (en) * | 2017-09-22 | 2020-06-09 | 北京嗨动视觉科技有限公司 | Backboard device and video processor |
| CN110351509B (en) * | 2018-04-03 | 2021-12-14 | 北京小鸟科技股份有限公司 | Multi-channel high-bandwidth data exchange method based on FPGA (field programmable Gate array) stack |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1102489A1 (en) * | 1999-05-24 | 2001-05-23 | Matsushita Electric Industrial Co., Ltd. | Image switching device and image outputting devices |
| EP1178699A2 (en) * | 2000-07-31 | 2002-02-06 | Alcatel | Transport interface for time division frames |
| CN101426127A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院沈阳自动化研究所 | Video target generating device |
| CN101568018A (en) * | 2008-04-22 | 2009-10-28 | 中兴通讯股份有限公司 | Rotational-free panoramic photography device and monitoring system comprising same |
| CN101668209A (en) * | 2009-09-14 | 2010-03-10 | 杭州中威电子技术有限公司 | EPON video encoder |
| CN101854487A (en) * | 2009-03-30 | 2010-10-06 | 深圳市朗科科技股份有限公司 | Video signal switching system and method |
-
2011
- 2011-06-22 CN CN 201110170618 patent/CN102223490B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1102489A1 (en) * | 1999-05-24 | 2001-05-23 | Matsushita Electric Industrial Co., Ltd. | Image switching device and image outputting devices |
| EP1178699A2 (en) * | 2000-07-31 | 2002-02-06 | Alcatel | Transport interface for time division frames |
| CN101426127A (en) * | 2007-10-31 | 2009-05-06 | 中国科学院沈阳自动化研究所 | Video target generating device |
| CN101568018A (en) * | 2008-04-22 | 2009-10-28 | 中兴通讯股份有限公司 | Rotational-free panoramic photography device and monitoring system comprising same |
| CN101854487A (en) * | 2009-03-30 | 2010-10-06 | 深圳市朗科科技股份有限公司 | Video signal switching system and method |
| CN101668209A (en) * | 2009-09-14 | 2010-03-10 | 杭州中威电子技术有限公司 | EPON video encoder |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107645638A (en) * | 2017-09-22 | 2018-01-30 | 北京嗨动视觉科技有限公司 | Video processor and backplane communication method |
| CN107645638B (en) * | 2017-09-22 | 2019-10-11 | 北京嗨动视觉科技有限公司 | Video processor and backplane communication method |
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|---|---|
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