CN102223173B - Method and device for coarse synchronizing sub-frame - Google Patents
Method and device for coarse synchronizing sub-frame Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
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- H04L27/2673—Details of algorithms characterised by synchronisation parameters
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Abstract
The invention discloses a method and a device for coarse synchronizing sub-frame, comprising the following steps: conducting hard decision on the sampled signal by terminal sampling digital base band signals, thus obtaining the sign bits of the sampling signal; intercepting the virtual sub-frame in the sign bit of the sampled signal by the terminal; carrying out the differential operation on the adjacent sample points in each intercepted virtual sub-frame, thus obtaining the differential hard decision virtual sub-frame data; carrying out accumulation on a plurality of differential hard decision virtual sub-frames and removing the sign bit at each sample point of the accumulated result by the terminal; and searching the position with downlink synchronous code characteristic in the accumulated result by terminal. In the invention, based the design of hard decision data accumulation, AGC (Automatic Gain Control) attempt is avoided; the differential operation is carried out so as to eliminate the influence of phase and channel, thus eliminating the dependency of the coarse synchronization of district searching on a plurality of factors such as radio frequency devices, ADC (Analog to Digital Converter) bit-width and dynamic scope of downlink signal and the like, thereby obviously improving the stability during the coarse synchronization process of district searching.
Description
Technical field
The present invention relates to TD SDMA access (Time Division-Synchronized CodeDivisionMultiple Access, TD-SCDMA) system, relate in particular to a kind of method and device of coarse synchronizing sub-frame.
Background technology
TD-SCDMA is one of three large mainstream standard of 3G (third generation mobile technology), is with a wide range of applications.
In TD-SCDMA system, terminal (UE) needs to search the community that may exist after initially powering on, and select suitable community to login, only at UE, sign in to behind community, just can obtain the more detailed information in this community and obtain the information of adjacent cell, also only after signing in to community, just can monitor paging or make a call, conventionally by searching from start the procedure definition that signs in to suitable cell, be cell initial searching process, be called for short ICS.
TD-SCDMA cell initial searching process comprises the rough position of knowing synchronous code (DwPTS), namely the step of synchronizing sub-frame.The base station signal of TD-SCDMA be take 5ms (millisecond) as cycle transmission, the signal of each 5ms is called 1 subframe, the same position cycle of descending synchronous code (Sync-DL) in each subframe occurs, the terminal that refers to coarse synchronizing sub-frame finds the descending synchronous code in subframe, complete roughly and base station signal synchronizing sub-frame the process that subframe original position is roughly alignd.
The method that has at present two kinds of coarse synchronizing sub-frames, a kind of is according to the energy window method of the power distribution characteristics search of TD-SCDMA subframe; Another kind is to make relevant correlation method to 32 Sync-DL codes within the scope of whole subframe.
Correlation method, because the environment performance that operand is huge and disturb in multipath and co-frequency cell is obviously degenerated, therefore, lacks practical value.
For energy window method, consider in the frame structure of TD-SCDMA, please refer to Fig. 1, there is the protection interval (GP) of 32 chips (chips) on the left side of Sync-DL, base station is not transmitting during this period of time, there is the GP of 96 chips on the right, Sync-DL is originally as 64 chips, because the power of GP is very little, therefore the time distribution from received power, the power of comparing Sync-DL section with GP is larger, when 64 chips of using Sync-DL section power sum divided by both sides (each 32 chips of both sides) power sum, can obtain the larger estimation factor, by the method, judge the approximate location of DwPTS, therefore the approximate location that the method that can utilize the power shape that receives signal to set up power " Window " is searched for DwPTS.
Due to when carrying out the process of initial cell search, synchronizing sub-frame is not yet set up, AGC (automatic gain control) cannot enter synchronous mode, and be subject to the impact of contiguous UE, power between uplink and downlink timeslot may exist huge difference, for on digital baseband, obtain reasonable quantification down-going synchronous coded signal and near GP, existing method has to attempt multiple possible AGC gain, and under every kind of AGC gain scene, all carry out Window search, using the Window optimal value obtained under all AGC gain scenes estimated position as synchronizing sub-frame code position.
There is following problem in the Window synchronous method of attempting based on AGC:
1) when AGC gain is lower and actual signal power hour, most of data all do not obtain effectively many quantization bits, and cross small data and are divided by and cause the frequent appearance of characteristic value, this null result to affect normal characteristic value estimating.
2) too much AGC attempts the probability that kind has increased timing position erroneous judgement, has reduced the overall performance of Cell searching.
3) many factors such as dynamic range that the interval that AGC attempts and scope depend on radio-frequency devices, ADC bit wide and downstream signal, increase the crosslinked coupling between a plurality of modular design.
4) in order to ensure the performance of thick timing, the reliability under especially low speed of a motor vehicle environment, often single AGC gain just must be experienced abundant subframe, and repeatedly AGC attempts significantly increasing the processing time of Cell searching.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of cell search coarse synchronization method and device, solves problems such as adopting AGC exceptional value, probability of miscarriage of justice rise, the associated increase of intermodule, realizes a kind of method and device of coarse synchronizing sub-frame of the AGC of evading trial.
For solving the problems of the technologies described above, the method for a kind of coarse synchronizing sub-frame of the present invention, comprising:
Terminal sampling digital baseband signal, carries out hard decision to sampled signal, obtains the sign bit of sampled signal;
Terminal intercepts empty subframe from the sign bit of sampled signal, and adjacent sampling point in each intercepted empty subframe is carried out to calculus of differences, obtains the empty sub-frame data of difference hard decision;
Terminal adds up to the empty sub-frame data of a plurality of difference hard decisions, and each sampling point of accumulation result is removed to sign bit;
Terminal is searched the position with descending synchronous code feature in accumulation result.
Further, terminal is also got the imaginary part of the empty sub-frame data of this difference hard decision as data estimator before the empty sub-frame data of a plurality of difference hard decisions is added up;
The empty sub-frame data of a plurality of difference hard decisions is accumulated as the data estimator of the empty sub-frame data of a plurality of difference hard decisions is added up.
Further, terminal is also got the data filling of m chip in the end position of accumulation result after the empty sub-frame data of a plurality of difference hard decisions is added up from the original position of accumulation result, wherein, and m > 0.
Further, the method also comprises:
Terminal is opened the low noise amplifier in radio-frequency devices in cell search process, and the programmable gain amplifier in radio-frequency devices is configured to maximum gain;
Low noise amplifier and programmable gain amplifier amplify the signal of antenna output, and the signal after amplifying is sent to analog-digital converter, and this analog-digital converter is converted to digital baseband signal by the signal after amplifying.
Further, the position that has a descending synchronous code feature is: in accumulation result, amplitude is higher than the position of adjacent signal.
Further, when terminal is searched the position with descending synchronous code feature in accumulation result, adopt the mode of Window.
Further, when terminal intercepts empty subframe from the sign bit of sampled signal, 6400 chips of take are unit, and the data of every 6400 chips are as an empty subframe.
Further, a kind of device of coarse synchronizing sub-frame, comprising: successively connected hard decision module, difference block, accumulating operation module, remove sign bit module and position of downlink synchronous code determination module;
Hard decision module, for the digital baseband signal of sampling, carries out hard decision to sampled signal, obtains the sign bit of sampled signal, and the sign bit of this sampled signal is sent to difference block;
Difference block, intercepts empty subframe for the sign bit of the sampled signal from received, and adjacent sampling point in each intercepted empty subframe is carried out to calculus of differences, obtains the empty sub-frame data of difference hard decision, sends to accumulating operation module;
Accumulating operation module, adds up for the empty sub-frame data of a plurality of difference hard decisions to received, and accumulation result is sent to sign bit module;
Go sign bit module, for each sampling point of the accumulation result to received, remove sign bit, and send to row position of downlink synchronous code determination module;
Position of downlink synchronous code determination module, for searching the position with descending synchronous code feature at received accumulation result.
Further, accumulating operation module, also, for before empty sub-frame data adds up to a plurality of difference hard decisions, gets the imaginary part of the empty sub-frame data of this difference hard decision as data estimator;
Accumulating operation module is accumulated as the data estimator of the empty sub-frame data of a plurality of difference hard decisions is added up the empty sub-frame data of a plurality of difference hard decisions.
Further, go sign bit module, also for the original position from accumulation result, get the data filling of m chip in the end position of accumulation result, wherein, m > 0.
In sum, the present invention is based on the cumulative design of hard decision data to avoid AGC to attempt, introduced the impact of calculus of differences elimination phase place and channel, thereby eliminated the dependence of cell search coarse synchronization to the factors such as dynamic range of radio-frequency devices, ADC bit wide and downstream signal, obviously improved the stability of cell search coarse synchronization process.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of descending synchronous code;
Fig. 2 is the flow chart of the method for embodiment of the present invention coarse synchronizing sub-frame;
Fig. 3 is the schematic diagram of coarse synchronizing sub-frame performance under awgn channel;
Fig. 4 is the schematic diagram of sampled value position deviation on the thick net synchronization capability impact of subframe;
Fig. 5 is the schematic diagram of 3ppm crystal oscillator frequency deviation on the thick net synchronization capability impact of subframe;
Fig. 6 is the schematic diagram of coarse synchronizing sub-frame performance under case1 channel;
Fig. 7 is the schematic diagram of coarse synchronizing sub-frame performance under case2 channel;
Fig. 8 is the schematic diagram of coarse synchronizing sub-frame performance under case3 channel;
Fig. 9 is that the schematic diagram on the thick net synchronization capability impact of subframe is disturbed in homogeneous-frequency adjacent-domain;
Figure 10 is the structure chart of device of the coarse synchronizing sub-frame of embodiment of the present invention.
Embodiment
The principle of existing Window method based on the projecting Gp section of judgement synchronous code power power, must use the input of soft-decision, the baseband signal of radio frequency output itself is analog signal, A/D (analog/digital) conversion is translated into the digital signal of multi bit quantization, the quantification is here exactly soft-decision, and the meaning is except outer symbol, also has the information of data amplitude, for example 107.152 become 107 ,-13.87 after being quantized and become-14 after being quantized.
For on digital baseband, obtain reasonable quantification down-going synchronous coded signal and near GP, have to introduce the method for designing that AGC attempts, but a series of new problems such as exceptional value, probability of miscarriage of justice rise, the associated increase of intermodule that the introducing that AGC attempts has caused, cause system rather responsive, sane not for operative scenario.
In view of adopting AGC to have above-mentioned many inherent shortcomings, for this reason, be necessary to consider a kind of more sane method, avoid AGC and attempt, to avoid the series of problems of its initiation, reduce the crosslinked coupling with peripheral modules, within acceptable search time, reduce the false dismissal probability under low speed of a motor vehicle scene.
The principle that present embodiment occurs based on the every period of sub-frame of descending synchronous code, because descending synchronous code be take subframe as unit period appearance, and each subframe of other data sends at random, after a plurality of subframes are cumulative, the signal amplitude at position of downlink synchronous code place is higher than other data, based on this principle judgement descending synchronous code position, the problems referred to above of having avoided soft-decision to bring.
Below in conjunction with accompanying drawing, present embodiment is elaborated.
Fig. 2 is the method for the coarse synchronizing sub-frame of present embodiment, comprising:
201: terminal is opened all the time the LNA (low noise amplifier) in radio-frequency devices in cell search process, and be maximum gain by the VGA in radio-frequency devices (programmable gain amplifier) fixed configurations;
LNA and VGA are the amplifier of cascade, LNA has opening and closing two states, the gain of VGA is configurable, VGA is configured to maximum gain, guaranteed no matter the actual power of input signal is how many, through ADC (analog digital conversion) conversion, all can obtain digital signal, to carry out hard decision, produce the sign bit of digital signal.Sign bit refers to the sign symbol of signal, and for example 107.152 sign bit is that+1 ,-13.87 sign bit is-1.
Method due to present embodiment employing hard decision data, also only retain the sign bit of data, amplifier gain itself does not affect the variation of sign bit, but there are enough amplitudes in order to ensure output signal, the impact on data of step-down amplifier noise and minimum quantization interval, being configured to maximum gain is the most convenient effective mode, also can be configured to the certain gain of non-maximum gain, but at least need to be under this certain gain, during sensitivity minimization input signal, the amplitude of amplifier output signal is higher than the minimum quantization interval of ADC transducer.
202:LNA and VGA amplify the signal of antenna output, and the signal after amplifying is sent to ADC (analog-digital converter), and ADC carries out analog-to-digital conversion, and the signal after amplifying is converted to digital baseband signal output;
203: terminal sampling digital baseband signal, sampled digital baseband signal (sampled signal) is carried out to hard decision, obtain the sign bit of sampled signal;
Hard decision refers to that the sign bit only fetching data is as output, except outer symbol, there is no other information, and for example 107.152 become 1 ,-13.87 after being quantized and become-1 after being quantized.Signal is only retained to sign symbol position, do not retain amplitude information and be defined as hard decision process.
Adopt the strategy of hard decision, avoided in existing method in the situation that possible interval, ADC bit wide and the dynamic range of signals etc. of different received power there are differences the process of carrying out AGC trial, this process and parameter correlation; For example, the possible range that existing method receives signal power in terminal is-110dBm～+ 10dBm, in ADC bit wide, be in 6 bit situations, typical case need to attempt 90dB, 80dB, 70dB ... numerous yield values such as 0dB, to obtain suitable synchronous code, quantize judgement power difference.The parameter of other modules such as gain ranging of the process of present embodiment and relevant parameter value and ADC bit wide, input signal sensitivity demand and AGC does not all have direct relation, therefore, has reduced the coupling between module.
Because present embodiment is only paid close attention to the feature that the synchronous code cycle occurs, therefore, sample rate can adopt single times of chip speed, also can adopt many times of chip speed, the data that single times of chip speed need to be stored are less, and operand is also minimum, therefore can preferentially adopt single times of chip speed sampling.
Signal=(real (Signal) >=0) * 2-1+ ((imag (Signal) >=0) * 2-1) * sqrt (1); This formula is hard decision process, Signal is sampled signal, real is the real part of the number of winning the confidence, imag is the imaginary part of the number of winning the confidence, the meaning of whole formula is, the sign bit that the plural number of input is only retained to real part and imaginary part is as output, and assignment is given this signal again, 107.152-13.87j is for example+1-j after this formula is calculated.
204: terminal from the sign bit of sampled signal data intercept as empty subframe;
Terminal be take 6400 chip as unit data intercept, and the data of every 6400 chip are as an empty subframe.The length of each subframe is 6400 chip, and owing to also not determining the original position of subframe herein, the original position that is therefore subframe at certain chip of this place's arbitrary assumption is fetched data, and often gets 6400 chip, is defined as an empty subframe.
205: terminal is carried out the computing of difference to sampling point adjacent in each empty subframe, obtaining length is the empty sub-frame data of difference hard decision of L (L=6400chip);
Take the time as unit, and the signal definition that time relationship differs 1 chip is adjacent.
Because the time interval between adjacent chip only has 0.78125us, on this time interval, can be similar to and think that channel does not change, frequency deviation does not cause enough phase rotatings yet, and the phase effect that differentiated result causes channel and frequency deviation etc. is eliminated substantially, and the data of each subframe can be added up.
Signal=conj (Signal) .*[Signal (2:end); Signal (1)]; Wherein, Signal is empty subframe, and conj is conjugate operation, and this formula has completed the difference correlation computing of adjacent chip.
206: get the imaginary part of the empty sub-frame data of difference hard decision as data estimator;
Because the producing method of local synchronization code is that a sequence of real numbers is multiplied by (j)
itherefore, should only there is imaginary part in the differentiated signal of synchronous code of adjacent two chip, do not retain the impact that real part can reduce Noise and Interference, half that can also only get imaginary part, as data estimator, because differentiated result amplitude is 2 under noise-free case, is 1 divided by 2 rear amplitudes, more be convenient to describe, whether get half to implementing there is no impact.
Signal=imag (Signal)/2; Signal is the empty sub-frame data of difference hard decision, and imag gets plural imaginary-part operation.
207: the data estimator to the empty sub-frame data of the individual difference hard decision of N continuous (N >=2) adds up;
Because descending synchronous code be take subframe as unit period appearance, and each subframe of other data sends at random, after a plurality of subframes are cumulative, position of downlink synchronous code place is all the same data, for example N the cumulative postamble of subframe place amplitude is N, but different the cancelling out each other of each subframe of other position datas, after cumulative, amplitude is less than N, therefore cumulative postamble position signal amplitude is higher than other data, based on this principle judgement descending synchronous code position, this step realizes separates synchronous code and other data fields.
208: after completing data estimator cumulative of the empty sub-frame data of N difference hard decision, each sampling point of accumulation result is removed to sign bit, and afterbody sequence is supplied in circulation;
Removing sign bit method comprises: ask amplitude (taking absolute value) and get power etc.
It is in order to prevent that actual synchronization code position from appearing at empty subframe original position or end position, exceeds empty subframe scope that afterbody sequence is supplied in circulation.
SignalR=abs (SignalR); Abs is the computing that takes absolute value.
SignalRC=[SignalR; SignalR (1:144-1)]; This formula is supplied afterbody sequence for circulating, get the data of m chip of accumulation result original position and mend the end position at accumulation result, m can determine according to the parameter of Window, m > 0, as get 144, also can rule of thumb determine, to prevent that actual synchronization code position from appearing at empty subframe original position or end position, exceeds empty subframe scope.
209: terminal adopts the mode of Window in accumulation result, to search the position with descending synchronous code feature.
Can select Window parameter to be: the width 32 of P1 and P3, P2 width 64, P2 both sides respectively retain the Gap of width 8.
There is the signal amplitude of 64 chip synchronous code position higher than the feature of adjacent signal, to find 64 chip amplitudes higher than the mode of 32 chip amplitudes of 32, left side chip and the right below, due to this Window method and prior art basic identical, description is below comparatively simple.
Be to adopt the mode of Window in the amplitude of accumulation result, to find the process of the position with descending synchronous code feature below, comprise:
2091: the amplitude to accumulation result is asked for characteristic value;
Owing to there being 6400 chip in empty subframe, each chip may be all the original position of actual descending synchronous code, therefore has 6400 possible synchronous code original positions, is described as virtual synchronous code original position here.
The computational methods of the characteristic value of original position are:
P1Pow=max (P1Pow, P3Pow); P1Pow be P1 section amplitude and, P3Pow be P3 section amplitude and, max asks for maximum operation, this step be ask for P1 section amplitude and with P3 section amplitude and the greater as the amplitude of P1 section and.
DfPow=P2Pow-2*P1Pow; P2Pow be P2 section amplitude and, DfPow is amplitude difference, this step is to calculate P2 section amplitude and the P1 section amplitude than 2 times and large how many.
The amplitude of considering hard decision data is all identical, does not have Scaling Problem, therefore, adopts the subtraction of P2Pow and 2*P1Pow to replace traditional division to reduce implementation complexity.
2092: search maximum DfPow, retain value and the position of DfPow maximum in empty subframe;
[DefEsti, PosEsti]=max (DfPow); , DfPow is each virtual synchronous code original position characteristic of correspondence value, max is searching eigenvalue of maximum, and the size that DefEsti is eigenvalue of maximum, PosEsti is the location index that eigenvalue of maximum is corresponding.
2093: according to maximum DfPow position, extrapolate descending synchronous code position;
PosEsti=PosEsti+P2Pos-1; What previous step found is the position that in subframe, descending synchronous code has shifted to an earlier date P1 length place, and this step has been deducted the length that P1 shifts to an earlier date.
IfPosEsti > 6400, PosEsti=PosEsti-6400; Because the data of afterbody are that start position data cyclic shift obtains, exceed 6400 sync bit, actual is by the data acquisition before 6400 chip, therefore, the 6400chip of should take is sync bit before, because subframe occurred with the 6400chip cycle, whether deduct 6400chip actual synchronization result be there is no to direct impact again, herein deduction be only for range of results represent more reasonable.
In the situation that the empty sub-frame number N of present embodiment employing canonical parameter is 32, to cell search coarse synchronization method, the performance under various scenes has been carried out emulation comparison, work that all can be comparatively sane under multiple severe scene with proved execution mode.
First, analyze the performance based on hard decision cell search coarse synchronization under AWGN (additive white Gaussian noise) channel, the signal to noise ratio that in Fig. 3, abscissa is descending synchronous code, ordinate is the probability (surpassing 16chip with ideal position skew) that thick sync bit result makes a mistake, and the emulation quantity of each sampling point is 32000 subframes.Visible, the method can obtain good performance under awgn channel, and signal to noise ratio is-during 5dB, error probability is roughly 10, and signal to noise ratio is during higher than-3dB, and error probability is reduced to below one of percentage.
In order to reduce memory space, in method, used single times of chip sampling, therefore, sampled value position deviation can form certain influence to thick net synchronization capability, three curve corresponding ideal timings respectively in Fig. 4,1/4 sampled value position deviation and 1/2chip sampled value position deviation, as seen from the figure, 1/4chip sampled value position deviation is to performance impact not obvious, the performance degradation that this worst situation of 1/2chip sampled value position deviation causes is in 2dB left and right, and actual performance in this case also can meet system requirements.
Because this method is operated in cell search first step, now not yet obtain position of downlink synchronous code, AFC (automatic frequency control) cannot carry out, consider when local crystal oscillator frequency and expected frequency are when incomplete same, can cause on base band data the impact of two aspects: the base-band signal frequency skew that (1) local oscillator frequency deviation causes; (2) the sampled value position that ADC sampling frequency offset causes adds up in time and moves.
Fig. 5 emulation when crystal oscillator frequency deviation reaches 3ppm, the impact of above-mentioned two kinds of factors on this method performance.Owing to having introduced calculus of differences, therefore, baseband signal frequency deviation itself to thick net synchronization capability almost without visible influences, but each subframe of crystal oscillator frequency deviation of 3ppm can cause the movement of the sampled value position of 0.0192 chip, in the interval of 32 subframes, sampled value position accumulative total has moved 0.6144 chip, in figure emulation the performance in initial subframe sampled value position deviation 1/2chip and crystal oscillator frequency deviation 3ppm situation, its performance has degenerated to 1/2chip sampled value position deviation and has approached as seen.
Assess the impact of multidiameter fading channel on cell search coarse detector timing properties b below, Fig. 6～Fig. 8 emulation cell search coarse performance regularly under Case1～Case3 channel circumstance of minimum performance standard definition.
Case1 and Case2 channel are a kind of low speed fading channel environment, the speed of a motor vehicle of 3km/h will cause maximum doppler frequency to only have 5.6Hz in the carrier frequency of 2GHz, that is to say and will reach about 180ms or 36 subframes fading period, coarse synchronization method based on hard decision is owing to not needing to carry out AGC trial, therefore sufficient span is provided in time, largely, ensured the performance under the low speed of a motor vehicle environment in class list footpath of low speed of a motor vehicle environment, especially Case1.Because calculus of differences has been eliminated the impact of the characteristic of channel substantially, under this high velocity environment of Case3, thick net synchronization capability is also comparatively desirable.
Consider that the co-frequency neighbor cell that may exist disturbs, Fig. 8 emulation the scene that simultaneously exists co-frequency neighbor cell to disturb, the adjacent cell of wherein seeing at travelling carriage is respectively 0dB with respect to the power ratio of this community, 1 chip has lagged behind the time of advent.
Visible in Fig. 9, disturb the co-frequency neighbor cell that time delay is more or less the same not only can not cause performance degradation, also performance is had to castering action to a certain degree, this is because hard decision Window method itself has just utilized each period of sub-frame of same descending synchronous code to occur this characteristic, the synchronous code of local area and the synchronous code of adjacent area all meet this feature, can in estimating the factor, be embodied.
Figure 10 is the device of the coarse synchronizing sub-frame of present embodiment, comprising: successively connected hard decision module, difference block, accumulating operation module, remove sign bit module and position of downlink synchronous code determination module, wherein:
Hard decision module, for the digital baseband signal of sampling, carries out hard decision to sampled digital baseband signal (sampled signal), obtains the sign bit of sampled signal, sends to difference block;
Difference block, be used for the sign bit data intercept of the sampled signal from receiving as empty subframe, sampling point adjacent in each empty subframe is carried out to calculus of differences, obtaining length is the empty sub-frame data of difference hard decision of L (L=6400chip), and the empty sub-frame data of difference hard decision is sent to accumulating operation module;
Accumulating operation module,, adds up to the data estimator of the empty sub-frame data of the individual difference hard decision of N continuous (N >=2) as data estimator for the imaginary part of getting the empty sub-frame data of difference hard decision, and accumulation result is sent to sign bit module;
Go sign bit module, for each sampling point to accumulation result, remove sign bit, and afterbody sequence is supplied in circulation, that is: the data of getting m chip of accumulation result original position are mended the end position at accumulation result, m > 0, and send to position of downlink synchronous code determination module;
Position of downlink synchronous code determination module, for adopting the mode of Window to search the position with descending synchronous code feature at accumulation result.
Claims (10)
1. a method for coarse synchronizing sub-frame, comprising:
Terminal sampling digital baseband signal, carries out hard decision to sampled signal, obtains the sign bit of described sampled signal;
Described terminal intercepts empty subframe from the sign bit of described sampled signal, and adjacent sampling point in each intercepted empty subframe is carried out to calculus of differences, obtains the empty sub-frame data of difference hard decision;
Described terminal adds up to the empty sub-frame data of a plurality of described difference hard decisions, and each sampling point of accumulation result is removed to sign bit;
Described terminal is searched the position with descending synchronous code feature in described accumulation result.
2. the method for claim 1, is characterized in that:
Described terminal is also got the imaginary part of the empty sub-frame data of this difference hard decision as data estimator before the empty sub-frame data of a plurality of described difference hard decisions is added up;
Described the empty sub-frame datas of a plurality of described difference hard decisions are accumulated as the data estimator of the empty sub-frame datas of a plurality of described difference hard decisions is added up.
3. method as claimed in claim 1 or 2, it is characterized in that: after described terminal adds up to the empty sub-frame data of a plurality of described difference hard decisions, also from the original position of accumulation result, get the data filling of m chip in the end position of accumulation result, wherein, m > 0.
4. the method for claim 1, is characterized in that, the method also comprises:
Described terminal is opened the low noise amplifier in radio-frequency devices in cell search process, and the programmable gain amplifier in described radio-frequency devices is configured to maximum gain;
Described low noise amplifier and programmable gain amplifier amplify the signal of antenna output, and the signal after amplifying is sent to analog-digital converter, and this analog-digital converter is converted to described digital baseband signal by the signal after described amplification.
5. the method for claim 1, is characterized in that:
The described position with descending synchronous code feature is: in described accumulation result, amplitude is higher than the position of adjacent signal.
6. method as claimed in claim 5, is characterized in that: when described terminal is searched the position with descending synchronous code feature in described accumulation result, adopt the mode of Window.
7. the method for claim 1, is characterized in that: when described terminal intercepts empty subframe from the sign bit of described sampled signal, 6400 chips of take are unit, and the data of every 6400 chips are as an empty subframe.
8. a device for coarse synchronizing sub-frame, comprising: successively connected hard decision module, difference block, accumulating operation module, remove sign bit module and position of downlink synchronous code determination module;
Described hard decision module, for the digital baseband signal of sampling, carries out hard decision to sampled signal, obtains the sign bit of described sampled signal, and the sign bit of this sampled signal is sent to described difference block;
Described difference block, intercepts empty subframe for the sign bit of the described sampled signal from received, and adjacent sampling point in each intercepted empty subframe is carried out to calculus of differences, obtains the empty sub-frame data of difference hard decision, sends to described accumulating operation module;
Described accumulating operation module, adds up for the empty sub-frame data of a plurality of described difference hard decision to received, described in accumulation result is sent to, goes sign bit module;
The described sign bit module of going, removes sign bit for each sampling point of the accumulation result to received, and sends to described position of downlink synchronous code determination module;
Described position of downlink synchronous code determination module, for searching the position with descending synchronous code feature at received accumulation result.
9. device as claimed in claim 8, is characterized in that:
Described accumulating operation module, also, for before the empty sub-frame data of a plurality of described difference hard decisions is added up, gets the imaginary part of the empty sub-frame data of this difference hard decision as data estimator;
Described accumulating operation module is accumulated as the data estimator of the empty sub-frame data of a plurality of described difference hard decisions is added up the empty sub-frame data of a plurality of described difference hard decisions.
10. device as claimed in claim 8, is characterized in that:
The described sign bit module of going is also got the data filling of m chip in the end position of accumulation result for the original position from described accumulation result, wherein, and m > 0.
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| CN110400570B (en) * | 2019-06-24 | 2021-08-31 | 成都航天通信设备有限责任公司 | Multi-channel digital audio mixing implementation method |
| CN115079217A (en) * | 2022-07-20 | 2022-09-20 | 中国人民解放军国防科技大学 | Large dynamic high sensitivity short burst signal loop steady tracking method |
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| CN101170534A (en) * | 2007-10-31 | 2008-04-30 | 中兴通讯股份有限公司 | A timing rough synchronization capturing method for mobile multimedia broadcast system |
| WO2008069512A1 (en) * | 2006-12-04 | 2008-06-12 | Electronics And Telecommunications Research Institute | Apparatus and method for acquiring frame synchronization and frequency synchronization simultaneously in communication system |
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| WO2008069512A1 (en) * | 2006-12-04 | 2008-06-12 | Electronics And Telecommunications Research Institute | Apparatus and method for acquiring frame synchronization and frequency synchronization simultaneously in communication system |
| CN101170534A (en) * | 2007-10-31 | 2008-04-30 | 中兴通讯股份有限公司 | A timing rough synchronization capturing method for mobile multimedia broadcast system |
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