CN102215078A

CN102215078A - Method for realizing hardware timestamp based on FPGA (field programmable gate array)

Info

Publication number: CN102215078A
Application number: CN2011101524513A
Authority: CN
Inventors: 吴维宁; 奚后玮; 蒋元晨; 范志刚; 吴军民; 吴鹏; 张小建; 黄治; 王向群; 黄在朝; 孙洪雷; 吴明
Original assignee: State Grid Electric Power Research Institute
Current assignee: State Grid Electric Power Research Institute
Priority date: 2011-06-09
Filing date: 2011-06-09
Publication date: 2011-10-12

Abstract

The invention relates to a method for realizing hardware timestamp based on an FPGA (field programmable gate array), for realizing the acquirement of timestamp with high accuracy of network data, and belongs to the innovation of the IEEE1588 synchronous system aspect of internet time. The method is characterized in that the acquirement of IEEE1588 timestamp and the frequency adjustment of adjustable crystal oscillator are realized for FPGA programming by utilizing the VHDL (hardware description language), wherein the timestamp accuracy reaches 8ns; and a processor takes the timestamp acquired by the FPGA and inserts a corresponding IEEE1588 data frame, and further all network accuracy clock synchronization is realized.

Description

A kind of hardware timestamping implementation method based on FPGA

Technical field

The invention belongs to the communication of power system technical field, relate to a kind of hardware timestamping implementation method based on FPGA, this method can be used to realize the network time communication system based on IEEE1588.

Background technology

Along with the construction of intelligent grid, clock synchronization system becomes more and more important.Conventional substation need be set up one and overlap independently clock synchronization system.Adopting the GPS or the Big Dipper is time source, by the time allocation units time signal further is dispensed to each automation equipment at interval, and data acquisition is synchronous in the realization transformer station.Intelligent substation adopts IEC61850 to unify communication protocol, adopts the Industrial Ethernet technology to set up communication network, realizes the intellectuality of transformer station.Employing then can be simplified the system configuration of transformer station greatly based on the network time synchronization system of IEEE1588, reducings the construction costs, and reduces maintenance workload, is the developing direction of transformer station's clock synchronization system.

The network time synchronization system that sets up high-precision IEEE1588 must realize catching of high precision time stamp, and the subnetwork exchange chip provides catching of hardware timestamping at present, and part physical layer interface chip also provides catching of hardware timestamping.But in actual use, which kind of mode no matter all exists and uses dumbly, and the cost problem of higher presses for flexible, economic, practical, the high performance hardware timestamping implementation method of a kind of use.

Summary of the invention

In order to overcome the deficiencies in the prior art, realize that a kind of use is flexible, economical, high performance hardware timestamping catching method, the invention provides a kind of hardware timestamping catching method based on field-programmable.Utilize this method can realize based on IEEE1588 master clock, from the clock and the network switching equipment, and then form high-accuracy network clock synchronization system based on IEEE1588.

In order to realize the foregoing invention purpose, the present invention adopts following technical scheme:

(1) FPGA is between exchange chip and the ethernet physical layer chip, and FPGA is connected with physical chip with exchange chip respectively by the MII interface.

(2) the built-in elapsed time clock module of FPGA is used to provide real-time clock output.

(3) the built-in IEEE1588 bag of FPGA parsing module is used to resolve the Ethernet data bag.This module only is responsible for resolving the Ethernet bag, the bag data is not made any modification.

When (4) IEEE1588 bag parsing module is judged current data stream for the SYNC of IEEE1588 or Delay_Req message, the bag parsing module reads the real-time clock data of elapsed time clock output, and adds the on-chip memory that information such as corresponding ports, IP deposit FPGA in.

Beneficial effect of the present invention is, adopt the FPGA field programmable logic device, software by autonomous Design is realized the communication of algorithms, overcome the drawback of special chip on flexibility and practicality, satisfied the realization demand of IEEE1588 network time synchronization system, boundless application prospect will have been arranged.

Description of drawings

Fig. 1 is based on the hardware timestamping implementation method block diagram of FPGA.

Embodiment

Be on the FPGA hardware between exchange chip and the physical chip, it is connected with physical chip with exchange chip respectively by the MII interface.

IEEE1588 bag parsing module is responsible for resolving MII interface transmitting-receiving data flow, and it does not change the legacy data content.This bag parsing module is at first judged the 62nd byte of message, if " 0x01 " judges that this message is SYNC or Delay_Req message; When message the 62nd byte content is " 0x01 ", continue the 74th byte of analytic message, if " 0x00 " judges that then message is the SYNC message, if " 0x01 " judges that then message is the Delay_Req message.

When IEEE588 bag parsing module thinks that these data are the SYNC of IEEE1588 or Delay_Req message, read the real-time clock data of elapsed time clock module output, and add contents such as IP address, port address and deposit relevant on-chip memory in.

The on-chip memory capacity:

SYNC_IN: capacity is 1.Require to have only a main equipment in the network, switch has only a port to receive the SYNC message.When receiving next SYNC message, the value of updated stored device empties the SYNC_OUT register simultaneously.

SYNC_OUT: capacity equals the switch ports themselves number.This programme is set at 64.In case data are read by CPU, then memory is no longer preserved these data.When receiving the SYNC message, this on-chip memory will be cleared at every turn.

Delay_Req_IN: capacity supports that with local area network terminal the number of devices of IEEE1588 is relevant.This programme preliminary definition is that 5k(promptly supports 5k IEEE1588 terminal equipment in the local area network (LAN) at most).In case data are read by CPU, then memory is no longer preserved these data.When receiving the SYNC message, this on-chip memory will be cleared at every turn.

Delay_Req_OUT: capacity supports that with local area network terminal the number of devices of IEEE1588 is relevant.This programme preliminary definition is that 5k(promptly supports 5k IEEE1588 terminal equipment in the local area network (LAN) at most).In case data are read by CPU, then memory is no longer preserved these data.When receiving the SYNC message, this on-chip memory will be cleared at every turn.

According to the definition of IEEE1588 about time stamp point, the time that IEEE1588 samples to the bag parsing module must just can report CPU through calibration.The calibration value of input and output needs to measure by experiment, now lacks concrete typical data.

Can draw the time difference Offset of switch and standard time according to the computing of CPU.If switch need carry out time calibration, then need in elapsed time clock and 4 memories all time values all with the addition of Offset value.

By CPU according to the Offset value of repeatedly measuring calculate toggle speed adjustment amount (be the ratio reference clock that runs of exchange clock fast what or slowly how much), according to this adjustment amount, FPGA can adjust timing circuit (can select to use adjustable crystal oscillator or change two kinds of methods of timing system of timing circuit) make own clock try one's best with reference clock walk the same fast, thereby make the clock of switch itself reach a very accurate value.

Claims

1. hardware timestamping implementation method based on FPGA, it is characterized in that: FPGA is between exchange chip and the physical chip, and it is connected with the phy chip layer with exchange chip respectively by Media Independent Interface MII.

2. a kind of hardware timestamping implementation method according to claim 1 based on FPGA, it is characterized in that: IEEE1588 bag parsing module is responsible for resolving MII interface transmitting-receiving data flow, judges whether this packet is the time-delay request message of SYNC message (sync message of IEEE1588 definition) or Delay _ Req(IEEE1588 definition) message.

3. a kind of hardware timestamping implementation method according to claim 2 based on FPGA, it is characterized in that: if receive message is SYNC or Delay _ Req message, then read the output of elapsed time clock module, the real-time clock data are inserted in SYNC or the Delay _ Req message, be transmitted to ppu, otherwise, be left intact directly to deliver and change chip and carry out exchanges data.