CN102214315A - Flash memory card used for differential data transmission - Google Patents
Flash memory card used for differential data transmission Download PDFInfo
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Abstract
A flash memory card used for differential data transmission comprises a differential data path which can be used for communication between the flash memory card and a host device, a differential signal is used for execution, the differential data path can be used for translation between differential signals and specific storage card signals so as to control reading/writing-in operations of a memory bank array of the flash memory card, the specific memory card signals can be signals of standard multimedia memory cards, safety digital memory cards, memory stick memory cards or compact flash memory cards and the like, the host device can contain a similar differential data path so as to provide the differential data transmission capability; and the differential data transmission is utilized instead of non-known clock data transmission, so that the integral data bandwidth between the flash memory card and the host device can be greatly increased, and the energy consumption and pin demands can be reduced.
Description
Technical field
The present invention is about a kind of packaged type memory card interface, and more particularly, the present invention is about the high speed that is used for flash memory cards and the interface of low power consuming.
Background technology
Flash memory cards is widely used for storing the digitized video that utilizes digital camera captured.Secure digital storage card (Secure Digital; SD) form is a kind of storage card formats of great use, is multimedia storage card (the Multi Media Card that early develops; MMC) expansion of form, secure digital storage card (SD) be approach and have a area as postage-stamp-sized.Another kind of digital document storage card formats is memory stick storage card (the Memory Stick that company released of Sony (Sony); MS), its outward appearance similarly is a little a slice chewing gum.And tight flash memory cards (Compact Flash; CF) be another kind of flash Card Type, summary is square, and more media store card of its size (MMC) and secure digital storage card (SD) are more greatly.
Flash memory cards also can be used as the additional memory card (add-on memory cards) of other devices, and these devices can be portable music player (portable music players), personal digital assistant (personal digital assistants for example; PDA), mobile phone or even notebook computer.Flash memory cards possesses hot plug (hot swappable) function, thereby makes the user can insert and remove flash memory cards easily, and need not to restart or the power supply start.Because the flash memory cards volume is little, durable again, and easy to carry, can utilize data file is copied to flash memory cards, makes data file to be transmitted between the electronic equipment at an easy rate.It should be noted that some storage card formats (for example, secure digital storage card (SD) and tight flash memory cards (CF)), be not limited in, also can be used for other application, as the communication receiving/transmission device as flash memory cards.
Traditionally, flash memory cards is to transmit data via one or more clock serial data lines (clocked serial datalines), anticipates promptly, and serial data is to transmit by each data line according to the clock signal that the single clock line is provided.Therefore, the message transmission rate of traditional flash memory cards can be subject to host clock speed (host clock rate).For example, Figure 1A shows a kind of interface between traditional multimedia storage card (MMC) 110 and legacy hosts device 130 (being electronic installation, as digital camera or MP3 player).Host apparatus 130 comprises socket 131 and host stores card controller 120, in order to multimedia storage card 110 communications.Host stores card controller 120 comprises multimedia storage card data routing 121, multimedia storage card protocol controller (processor) 122 and uses converter 123.Meanwhile, multimedia storage card 110 comprises multimedia storage card data routing 111, multimedia storage card protocol controller (processor) 112 and bank array 113.
Multimedia storage card data routing 121 and 111 provides identical basic function to host stores card controller 120 and multimedia storage card 110 respectively, that is, with respectively from the multimedia storage card of multimedia storage card protocol controller 122 and 112 exclusive control signal CTRL and data-signal DAT, be converted to clock command signal CMD and serial data signal SDAT respectively, these signals can be transmitted between host stores card controller 120 and the multimedia storage card 110 by multimedia storage card bus 150.Serial data signal SDAT and clock command signal CMD carry out clock control by the clock signal clk that multimedia storage card data routing 121 is produced.Multimedia storage card data routing 121 and 111 also is converted to exclusive data-signal DAT of multimedia storage card and status signal ST respectively with serial data signal SDAT and the clock command signal CMD that receives.In the process of these data-switching, the serial data signal SDAT that multimedia storage card data routing 121 and 111 provides input and clock command signal CMD are by serial conversion become to walk abreast (serial to parallel), and provide the conversion that forwards serial (parallel to serial) to by walking abreast to produce the serial data signal SDAT and the clock command signal CMD of output, go to carry out frame detecting (framedetection), guaranteeing the read of correct bank array 113, and carry out bug check (typical Cyclical Redundancy Check (CRC) is checked serial data signal SDAT and clock command signal CMD).
Multimedia storage card protocol controller 122 and 112 in host stores card controller 120 and multimedia storage card 110 is then carried out suitable operation respectively, responds the exclusive control signal CTRL of multimedia storage card, status signal ST and data-signal DAT.And the key distinction of multimedia storage card protocol controller 122 in host stores card controller 120 and the multimedia storage card protocol controller 112 in multimedia storage card 110 is, multimedia storage card protocol controller 122 is based under the control of using converter 123 and operates, go for and ask reading and write operation of multimedia storage card 110, multimedia storage card protocol controller 112 then to utilize control store volume array 113 to respond those to read and write request.In the multimedia storage card standard of version 3 .31, more detailed description is arranged about the multimedia storage card communications protocol.
In order to carry out the data transmission between host stores card controller 120 and multimedia storage card 110, multimedia storage card 110 at first will insert socket 131 (describing content so Figure 1A does not show this insertion process for clear) with initialization multimedia storage card 110.Use the exclusive control signal CTRL of multimedia storage card that converter 123 indication multimedia storage card protocol controllers 122 go to provide suitable (for example, carry out read operation) with by formative data-signal DAT suitably (for example, read the address) give multimedia storage card data routing 121, thus produce exclusive command signal CMD and the serial data signal SDAT (carrying out clock control) of multimedia storage card by clock signal clk.Use converter 123 and can be regarded as bridge between the exclusive communication of the exclusive communication of main frame and storage card usually.
Multimedia storage card data routing 111 on multimedia storage card 110 can receive command signal CMD and serial data signal SDAT, and these conversion of signals are returned suitable status signal ST (for example, read operation) and data-signal (for example, reading the address).At these signals, multimedia storage card protocol controller 112 can be carried out read or write operation on bank array 113, and produce a suitable response via control signal CTRL (for example, reading success) and data-signal DAT (for example, reading of data).Multimedia storage card data routing 111 can become clock command signal CMD and serial data signal SDAT with these conversion of signals, and be sent to multimedia storage card data routing 121 on host stores card controller 120, then (for example convert clock command signal CMD and serial data signal SDAT to a suitable status signal ST, effective reading of data) and data-signal DAT (for example, reading of data).At last, multimedia storage card protocol controller 122 can provide from the affirmation information of status signal ST and data-signal DAT with and/or data-signal to host apparatus 130 (directly or by using converter 123).
In this manner, data transmission is provided between host apparatus 130 and the multimedia storage card 110.The execution speed of this communication operation is fast more, and then multimedia storage card just can be handled bigger data file (for example, the image file of high pixel digital camera or film file) more.Because multimedia storage card has used clock data host-host protocol (clocked data transfer protocol), the data frequency range between host apparatus 130 and multimedia storage card 110 (data bandwidth) is determined by the frequency of clock signal clk and the data line quantity of transmitting serial data SDAT.
For example, the mechanical appearance specification of the multimedia storage card 110A of Figure 1B version of display 3.31 (anticipate promptly, multimedia storage card 110A meets the multimedia storage card standard of version 3 .31).Multimedia storage card 110A comprises 7 contact mats (pin), and pin allocation table as shown in the following Table 1.
Table 1
| The pin numbering | |
| 1 | |
| 2 | |
| 3 | |
| 4 | VDD |
| 5 | |
| 6 | |
| 7 | DAT0 |
As shown in table 1, pin 3,4 and 6 is power pins, and prepares to receive operating voltage VSS1, VDD and VSS2 respectively.Pin 2 is an I/O (I/O) pins, be used for receiving and response clock command signal CMD, and pin 5 is to be used for receive clock signal CLK.At last, pin 7 is an I/O (I/O) pins, is used to transmit data turnover multimedia storage card 110A (pin 1 is not used in the multimedia storage card standard of version 3 .31).Therefore, because multimedia storage card 110A only comprises single data pin (pin 7), the unique method that improves message transmission rate is to utilize the frequency that increases the clock signal clk that is provided in pin 5.Yet, because the propagation delay (propagation delays) of signal and ghost effect (parasitics) are (for example, stray capacitance and contact resistance), make the signal that is sent to the multimedia storage card bus decay, the maximum clock frequency of multimedia storage card console controller generally only limits to 20 megahertzes (MHz).Therefore, the maximum data transfer rate of multimedia storage card is 2.5MB/ second.
In order to overcome the restriction of this data frequency range, up-to-date multimedia storage card standard 4.0 has increased the pin number in the mechanical appearance specification.Fig. 1 C shows the mechanical appearance specification of the multimedia storage card 110B of multimedia storage card standard 4.0, and it has traditional pin distribution, is shown in following table 2.
Table 2
| The pin numbering | |
| 1 | |
| 2 | |
| 3 | |
| 4 | VDD |
| 5 | CLK |
| 6 | VSS2 |
| 7 | DAT0 |
| 8 | DAT1 |
| 9 | DAT2 |
| 10 | DAT4 |
| 11 | DAT5 |
| 12 | DAT6 |
| 13 | DAT7 |
Yet, it should be noted that this utilization increases the method that data I/O (I/O) pin count improves the data frequency range, for generally causing minus effect on the trend minimizing flash card size.In addition, increase the power attenuation that the data pin has also improved flash memory cards relatively, particularly on the battery powdered device that uses flash memory cards, can throw into question.
Secure digital storage card and multimedia storage card have complementary memory card interface; therefore regular meeting is called secure digital/multimedia storage card (SD/MMC cards) with its merger together the time; the multimedia storage card of a version 3 .31 has 7 metal contact pads, and a secure digital storage card then has 9 metal contact pads.Therefore, multimedia storage card goes for the secure digital storage card slot, (secure digital storage card normality is slightly thicker than multimedia storage card and the secure digital storage card goes for the multimedia storage card slot sometimes, therefore might can't be applicable to multimedia storage card slot partly), yet, main frame must determine which kind of storage card the storage card of the slot that inserts is, when multimedia storage card inserts, have only 7 metal contact pads to be used, other extra two metal contact pads then just can be used to when the secure digital storage card inserts slot in detecting.
Fig. 2 A illustrates the schematic flow sheet that known main frame is carried out the detecting of routine storage card, and main frame is a personal host computer for example, detects when storage card inserts slot, as step 200, for example utilizes detecting storage card detecting (card detect; CD) pin, it utilizes the resistance of secure digital storage card to give drawing (pullhigh), or utilizes the mechanical switch actuation characteristic on multimedia/secure digital storage card to detect.Main frame sends a sequence command that includes the CMD55 instruction and arrives the storage card that inserts, and as step 202, if storage card is suitably responded this CMD55 instruction, as step 204, then the storage card of this insertion is a multimedia storage card, rather than the secure digital storage card.In this example, a sequence command that includes the CMD1 instruction is sent to multimedia storage card, as step 206, then, multimedia storage card can be given initialization by a sequence command, and this sequence command can be for example for main frame reads the Configuration Registrar that is positioned on the multimedia storage card, as step 208, then, main frame can use 7 pins that multimedia storage card shares to carry out communication with multimedia storage card.
If the storage card that inserts is suitably responded the CMD55 instruction, as step 204, then this storage card that inserts may be the secure digital storage card, the further transmission that continues includes the into order of rank instruction ACMD41 and arrives the storage card that inserts, as step 210, if this storage card can not suitably be responded into rank instruction ACMD41, as step 212, then this storage card is a malfunction and failure, as step 214.
If this storage card has suitably been responded the ACMD41 instruction, as step 212, then this storage card is the secure digital storage card, then, utilize a sequence command to give with the initialization of secure digital storage card, for example can be main frame and read Configuration Registrar (configuration registers) on the secure digital storage card, as step 216, main frame has used 9 pins of secure digital memory card interface to link up with the secure digital storage card, main frame can digital memory card interface safe in utilization a data signal line or how to link up to four data signal lines, it decides (such as data structure according to the environment of linking up, the qualities that storage card slot connects etc.), the data that are stored in the secure digital storage card can utilize the high-order security protocol to be encrypted (encrypted).
Fig. 2 B is the schematic flow sheet that the known routine detecting that utilizes the secure digital storage card to carry out is responded, after inserting host slot and energising, the secure digital storage card utilizes metal contact pad to be powered, as step 220, the storage card initialization routine starts then, as step 222, wherein may include various inside oneselfs and detect, the controller of secure digital storage card inside will be carried out these routines, start external interface, then and wait for that (with responding) comes from the instruction of main frame.Secure digital memory card controller in the storage card is waited for the instruction CMD55 that comes from main frame, as step 224, and the instruction ACDM41 that comes from main frame, as step 226, respond mode of operation Register (Operating Conditions Register then; OCR) give main frame, as step 228.At this moment, the secure digital storage card is then waited for the further instruction that comes from main frame, and as step 230,9 all pins of secure digital memory card interface all can be used to.
It should be noted that therefore, the transfer rate of secure digital storage card can be higher than the multimedia storage card of version 3 .31 because the secure digital storage card has the pin more than the multimedia storage card of version 3 .31.At present the transfer rate of the highest 100Mb/ of secure digital memory card interface support second is quite enough for many applications.Yet application partly is full-motion video (full motion video for example; FMV) storage or transmission then need higher transfer rate, and following application also only can become and uses greater amount frequency range (bandwidth intensive).Therefore, the secure digital memory card interface certainly will face the subject under discussion of frequency range (and energy), be similar to corresponding 1B, 1C and scheme described multimedia storage card interface, other flash memory cards agreement is all used clock data transmission method opinion, therefore also can face similar frequency range restricted problem.
Other non-uses also can provide higher transfer rate sometimes in the bus interface of flash memory cards, for instance, and USB (universal serial bus) (Universal Serial Bus; USB) reach as high as the 480Mb/ transfer rate of second, and the peripheral device element connects express delivery (Peripheral Component Interconnect Express; PCIE) transfer rate and the string type that reaches as high as 2.5Gb/ second advances rank supplementary technology (Serial AdvancedTechnology Attachment; SATA) can reach the transfer rate of 1.5Gb/ second and 3.0Gb/ second, then be time two examples of the high-speed serial bus interface of generation device, yet because the demand of its big interface size, so PCIE and SATA are nearly all as the inside extended interface of PC, for instance, the SATA interface needs two connectors that separate, and the connector of 7 pins is in order to carrying signal, the connector of another 15 pins is used to provide required electric power.
Two often are used as the employed bus interface of PC external peripheral device, are respectively IEEE1394 (Firewire; Live wire) and system for serial small computer interface (Serial Attached SmallComputer System Interface; Serial Attached SCSI), can provide the high-speed data frequency range, Firewire supports the highest 3.2Gb/ message transmission rate of second, and SCSI supports 1.5Gb/ second or the message transmission rate of 3.0Gb/ second; It is fast that the speed of these data transmission is all 5 to 32 times of maximum data transfer rate of secure digital storage card.
A kind of new packaged type storage card Dimensions is the ExpressCard that knows, and it is by international personal computer memory card (the Personal Computer Memory Card International Association of association; PCMCIA), peripheral device element connection (PCI) and USB (universal serial bus) (USB) standard group develop, the ExpressCard summary is 75 millimeters long, 34 mm wides and 5 millimeters thick, and has the ExpressCard connector, and provide the interface of USB and PCIE simultaneously with the card connector of same 26 pins, yet, the connector of 26 bigger pins of ExpressCard has but limited his purposes on the contrary, and has increased the overall dimensions that uses the device of ExpressCard connector.
Therefore, partly bus interface can provide the message transmission rate more much higher than known flash memory cards, yet, the bigger connector size of these bus interface (also having increased simultaneously the demand of power supply) make its can't with general small appearance specification and compatible than the flash memory cards of low power consuming, therefore, need a kind of flash memory cards and agreement at present badly, allow to increase the frequency range of data transmission, the size that need not increase interface simultaneously with and/or the consumption of electric energy.
Summary of the invention
The objective of the invention is to, solve the technical matters of existing flash memory cards frequency range restriction.
For achieving the above object, the invention provides a kind of flash memory cards, comprise:
One pin configuration is predetermined based on the pin count of this flash memory cards, and this pin configuration packet contains a group of pins, and in order to connect two pairs of differential serial data lines, each carries a positive signal and a negative signal to the differential serial data line;
One flash volume array;
One protocol controller is in order to this flash volume array of access; And
One differential data path, have an input differential signal is converted to the function that a status signal and an input data signal give this protocol controller, and the function that will be converted to an output differential signal from a control signal and an outputting data signals of this protocol controller, wherein this differential data path includes:
One difference transceiver is in order to change this input differential signal be an input multi-usage serial signal and an output multi-usage serial signal is converted to this output differential signal; And
One difference serial interface engine, be converted to this output multi-usage serial signal at least one status signal with this input data signal and with at least one control signal and this outputting data signals in order to change this input multi-usage serial signal, wherein this difference serial interface engine includes:
One demoder, it is according to a predetermined coding protocol this input multi-usage serial signal of decoding, and is converted to an input serial Bit String and flows;
One first converter was changed to one first sets of signals in order to should import the circulation of serial Bit String;
One synchronous detector is in order to carry out identification one synchronous message block and when detecting this synchronizing information group, to utilize generation one initial signal to begin the reception of package at this first sets of signals;
One writes the first in first out memory bank, responding this start signal, and exports this at least one status signal and this input data signal in order to the content that stores this first sets of signals;
One Cyclical Redundancy Check detector is in order to carry out a Cyclical Redundancy Check to respond this start signal at this first sets of signals;
One command detector, whether this first sets of signals is a command signal or a data-signal in order to decision, responding this start signal, and provides this decision to give this Cyclical Redundancy Check detector;
One start frame detector responding this start signal, and when detecting, triggers the generation of a local clock in order to a plurality of start frame message block of detecting this first sets of signals;
One package ending detector responding this start signal, and when detecting, is issued the reception that a termination signal finishes package in order to the package ending message block of detecting this first sets of signals;
One reads the first in first out memory bank, in order to the content that stores this at least one control signal and this outputting data signals by the output of this protocol controller and export a secondary signal group;
One synchronous generator is in order to produce a synchronous message block at this secondary signal group;
One Cyclical Redundancy Check generator is in order to produce a Cyclical Redundancy Check message block at this secondary signal group;
One command initialization circuit is a command signal or a data-signal in order to determine this secondary signal group, and provides this decision to give this Cyclical Redundancy Check generator;
One package ending generator is in order to produce package ending message block at this secondary signal group;
One second converter is converted to an output serial data crossfire in order to this secondary signal group, this Cyclical Redundancy Check message block, this synchronizing information group and this package ending message block with parallel receive; And
One scrambler applies this predetermined coding protocol to this output serial data crossfire, and is converted to this output multi-usage serial signal;
Wherein this flash memory cards includes one of them of a multimedia storage card, a secure digital storage card, a tight flash memory cards and a memory stick storage card.
The present invention also provides a kind of electronic installation, comprises:
One host stores card adapter, in order to connect a flash memory cards, this host stores card adapter includes:
One pin configuration, it is predetermined based on the pin count of this flash memory cards, and this pin configuration packet contains a group of pins, and in order to connect two pairs of differential serial data lines, each carries a positive signal and a negative signal to the differential serial data line;
One protocol controller;
One uses breakout box, and in order to controlling this protocol controller, and this application breakout box provides the bridge between specific device communication and the particular memory card communication; And
One differential data path, have an input differential signal is converted to the function that a status signal and an input data signal give this protocol controller, and the function that will be converted to an output differential signal from a control signal and an outputting data signals of this protocol controller, wherein this differential data path includes:
One difference transceiver is in order to change this input differential signal be an input multi-usage serial signal and an output multi-usage serial signal is converted to this output differential signal; And
One difference serial interface engine, be converted to this output multi-usage serial signal at least one status signal with this input data signal and with at least one control signal and this outputting data signals in order to change this input multi-usage serial signal, wherein this difference serial interface engine includes:
One demoder, it is according to a predetermined coding protocol this input multi-usage serial signal of decoding, and is converted to an input serial Bit String and flows;
One first converter was changed to one first sets of signals in order to should import the circulation of serial Bit String;
One synchronous detector is in order to carry out identification one synchronous message block and when detecting this synchronizing information group, to utilize generation one initial signal to begin the reception of package at this first sets of signals;
One reads the first in first out memory bank, responding this start signal, and exports this at least one status signal and this input data signal in order to the content that stores this first sets of signals;
One Cyclical Redundancy Check detector is in order to carry out a Cyclical Redundancy Check to respond this start signal at this first sets of signals;
One command detector, whether this first sets of signals is a command signal or a data-signal in order to decision, responding this start signal, and provides this decision to give this Cyclical Redundancy Check detector;
One package ending detector responding this start signal, and when detecting, is issued the reception that a termination signal finishes package in order to the package ending message block of detecting this first sets of signals;
One writes the first in first out memory bank, in order to the content that stores this at least one control signal and this outputting data signals by the output of this protocol controller and export a secondary signal group;
One synchronous generator is in order to produce a synchronous message block at this secondary signal group;
One Cyclical Redundancy Check generator is in order to produce a Cyclical Redundancy Check message block at this secondary signal group;
One command initialization circuit, whether this secondary signal group is a command signal or a data-signal in order to decision, and provides this decision to give this Cyclical Redundancy Check generator;
One start frame and package ending generator are in order to produce an initial frame information group and package ending message block at this secondary signal group;
One second converter is converted to an output serial data crossfire in order to this secondary signal group, this Cyclical Redundancy Check message block, this synchronizing information group, this start frame message block and this package ending message block with parallel receive; And
One scrambler applies this predetermined coding protocol to this output serial data crossfire, and is converted to this output multi-usage serial signal;
Wherein this flash memory cards includes one of them of a multimedia storage card, a secure digital storage card, a tight flash memory cards and a memory stick storage card.
The present invention also provides a kind of method of operating of carrying out in a flash memory cards, this operation is by the requirement of unique host institute, and this main frame and this flash memory cards interconnect by indivedual pin configurations of pairing, wherein this manipulates one group of pin that is used for connecting two pairs of differential serial data lines, each carries a positive signal and a negative signal to the differential serial data line, and this method includes the following step:
To be sent to this flash memory cards from a plurality of orders of this main frame;
This flash memory cards of identification;
One agreement of this flash memory cards of initialization;
Control this initialization and the specific device communication is provided and the particular memory card communication between bridge;
Conversion is the multi-functional serial signal of an input from an input differential signal of this main frame, and changes this and import multi-functional serial signal and offer a flash body in this flash memory cards at least one status signal and an input data signal; And
Conversion is the multi-functional serial signal of an output from an at least one control signal of the flash body in this flash memory cards and an outputting data signals, and changing this, to export multi-functional serial signal be that an output differential signal offers this main frame.
In one embodiment, flash memory cards (is a multimedia storage card for example, the secure digital storage card, tight flash memory cards, or the memory stick storage card or the like) can include the flash volume array, be used for the protocol controller of access flash bank array, and differential data path (differential datapath), wherein the differential data path gives protocol controller in order to input differential signal is converted to input data and/or status signal, and will be converted to the output differential signal from the outputting data signals and/or the control signal of agreement controller.
In another embodiment, set the host apparatus that receives flash memory cards and can include the host stores card adapter, and the host stores card adapter includes the protocol controller of carrying out the particular memory card communication, the application breakout box of bridge between application-specific communication and the protocol controller is provided, and differential data path, wherein, the differential data path gives protocol controller in order to input differential signal is converted to input data and/or status signal, and the output data and/or the control signal that will come from protocol controller are converted to the output differential signal.
In another embodiment, flash memory cards and/or be positioned at host apparatus the host stores card adapter can more include old (legacy) data routing, give protocol controller in order to input clock data and command signal are converted to input data and/or status signal respectively, and will come from the output data of protocol controller and/or control signal is converted to output clock data and/or command signal respectively, the existence of old data routing can allow flash memory cards and/or host apparatus can be respectively with known (just based on clock data) host apparatus and or flash memory cards carries out communication.
In another embodiment, the protocol controller that is positioned at flash memory cards and/or host stores card adapter can be the protocol controller of standard (such as multimedia storage card, secure digital storage card or memory stick storage card protocol controller), as long as the differential data path can suitably be converted to differential communication with the communication from particular memory card, therefore, the function of differential data transmission can in existing host apparatus, easily be achieved (for example, changing or the renewal of firmware) by hardware.
Beneficial effect of the present invention is, the flash memory cards agreement can be utilized provides differential data transmission to realize, when clock data transmission method opinion (methodologies) being substituted by differential data transmission and increasing the data frequency range and reduce power consumption, the existing physics of flash memory cards, electronics specification still can be continued reservation.The disclosed embodiment according to the present invention, the clock (CLK) of known flash memory cards interface protocol equally also can be kept with order (CMD) circuit, and the compatibility of recalling (just old (legacy)) and the initialization that storage card is provided are provided.
For making purpose of the present invention, feature and function thereof there are further understanding, cooperate graphic being described in detail as follows now:
Description of drawings
Figure 1A is the block schematic diagram of communication interface between known multimedia storage card and the host apparatus;
Figure 1B is the synoptic diagram of the pin configuration of known version 3 .31 multimedia storage card;
Fig. 1 C is the synoptic diagram of the pin configuration of known edition 4 .0 multimedia storage card;
Fig. 2 A illustrates the schematic flow sheet of the routine storage card detecting of known main frame execution;
Fig. 2 B is the schematic flow sheet that the known routine detecting that utilizes the secure digital storage card to carry out is responded;
Fig. 3 illustrates the synoptic diagram that secure digital storage card main frame receives multimedia storage card, secure digital storage card and hypervelocity secure digital storage card;
Fig. 4 illustrates the synoptic diagram that expansion type hypervelocity secure digital storage card main frame receives multimedia storage card, secure digital storage card and hypervelocity secure digital storage card;
Fig. 5 illustrates the schematic flow sheet of the routine storage card detecting of expansion type hypervelocity secure digital storage card main frame execution;
Fig. 6 is that the routine hypervelocity secure digital storage card that utilizes hypervelocity secure digital storage card to carry out is detected the schematic flow sheet of responding;
Fig. 7 is the block schematic diagram with main frame of secure digital card connector, and it supports the communication of augmented pattern;
Fig. 8 is the block schematic diagram with hypervelocity secure digital memory card device of secure digital card connector, and it supports the communication of hypervelocity secure digital storage card augmented pattern;
Fig. 9 is the functional schematic of signal multiplexer;
Figure 10 is the signal multiplex (MUX) tabulation that illustrates the secure digital card connector with 9 pins;
Figure 11 is the signal multiplex (MUX) tabulation that illustrates the multimedia storage card connector with 7 pins;
Figure 12 A is the signal multiplex (MUX) tabulation that illustrates the expansion type connector with 13 pins;
Figure 12 B is the signal multiplex (MUX) tabulation of drawing tools memory stick memory card system that 10 pins are arranged;
Figure 13 A illustrates the host apparatus with differential data transmission ability and the embodiment synoptic diagram of flash memory cards;
Figure 13 B illustrates the embodiment synoptic diagram of the communication of the host apparatus of activation differential data transmission and flash memory cards;
Figure 14 A, 14B, 14C, 14D illustrate the pin example arrangement synoptic diagram that various different flash memory cards can be combined with the differential data transmission function;
Figure 15 A is the embodiment synoptic diagram at the differential data path of flash memory cards;
Figure 15 B is the embodiment synoptic diagram at the differential data path of host apparatus;
Figure 16 A illustrates the difference serial interface engine and uses in flash memory cards the specific embodiment synoptic diagram that produces (and decoding) serial differential data-signal;
Figure 16 B illustrates the difference serial interface engine and uses in host apparatus the specific embodiment synoptic diagram that produces (and decoding) serial differential data-signal.
Description of reference numerals
10-and lock; The 110-multimedia storage card; The 110A-multimedia storage card; The 110B-multimedia storage card; 111-multimedia storage card data routing; 112-multimedia storage card protocol controller; The 113-bank array; The 12-output buffer; 120-host stores card controller; 121-multimedia storage card data routing; 122-multimedia storage card protocol controller; 123-uses converter; The 130-host apparatus; The 1301-flash memory cards; The compatible storage card of 1301A-multimedia storage card; The compatible storage card of 1301B-multimedia storage card; 1301C-secure digital storage card; 1301D-memory stick storage card; The 1302-host apparatus; The 1303-slot; The 131-socket; The 1310-bank array; The 1320-protocol controller; The 1321-core engine; 1322-buffer random access memory bank; 1323-bug check circuit; 1330-differential data path; The old data routing of 1330L-; 1331-difference serial interface engine; 1332-difference transceiver; 1340-host stores card controller; 1350-uses converter; The 1360-protocol controller; The 1361-core engine; 1362-buffer random access memory bank; 1363-bug check circuit; 1370-differential data path; The old data routing of 1370L-; 1371-difference serial interface engine; 1372-difference transceiver; The 1390-memory card bus; The 1391-Physical layer; The 1392-protocol layer; The 1393-application layer; The 14-input buffer; 150-multimedia storage card bus; 16-and lock; 1621-reads the first in first out memory bank; The parallel serial convertor that changes of 1622-; The 1623-scrambler; 1624-Cyclical Redundancy Check generator; 1625-command initialization circuit; The 1626-synchronous generator; 1627-package ending generator; 1631-writes the first in first out memory bank; 1632-transformation from serial to parallel converter; The 1633-demoder; 1634-Cyclical Redundancy Check detector; 1635-command detector; The synchronous detector of 1636-; 1637-package ending detector; 1638-start frame detector; The 1639-phase-locked loop; 1641-writes the first in first out memory bank; The parallel serial convertor that changes of 1642-; The 1643-scrambler; 1644-Cyclical Redundancy Check generator; 1645-command initialization circuit; The 1646-synchronous generator; 1647-start frame/package ending generator; 1651-reads the first in first out memory bank; 1652-transformation from serial to parallel converter; The 1653-demoder; 1654-Cyclical Redundancy Check detector; 1655-command detector; The synchronous detector of 1656-; 1657-package ending detector; The 1659-phase-locked loop; The 18-output buffer; The 20-input buffer; The 22-signal wire; 30-secure digital storage card; The 32-multimedia storage card; 34-hypervelocity secure digital storage card; 36-secure digital memory card bus; 38-secure digital storage card main frame; 39-secure digital storage card console controller; 40-hypervelocity secure digital memory card bus; 42-hypervelocity secure digital storage card main frame; 50-hypervelocity secure digital card connector slot; 50 '-secure digital memory card socket; 50 "-the multimedia storage card socket; The 51-main frame; 51 '-hypervelocity secure digital storage card host computer system; 52-multi-usage bus switch; 53-multi-usage bus interface system; 54-purposes selector switch; 56-multimedia storage card protocol processor; 58-multimedia storage card protocol processor; 60-universal serial bus protocol processor; The 62-PCI-Express protocol processor; The 64-SATA protocol processor; 66-IEEE 1394 protocol processors; The 68-host processor. system; 70-hypervelocity secure digital storage card plug; 71-hypervelocity secure digital memory card device; 72-multi-usage bus switch; 73-multi-usage bus interface system; 74-purposes selector switch; 75-secure digital storage card host computer system; 76-secure digital storage card protocol processor; 77-multimedia storage card host computer system; 78-multimedia storage card protocol processor; 80-universal serial bus protocol processor; The 82-PCI-Express protocol processor; The 84-SATA protocol processor; 86-IEEE 1394 protocol processors; 88-de-vice processor system; 900-signal multiplexer; 1～11-pin; P1～P9-pin; M1～M10-pin; S1～S9-pin.
Embodiment
Known flash memory cards and use the device of these flash memory cards to have relatively low message transmission rate, thereby can limit these flash and be stuck in execution on the application that uses a large amount of frequency ranges (bandwidth intensive).The differential data transmission agreement of utilizing activation to use for flash memory cards, the message transmission rate of these flash memory cards of output/input can improve significantly, and does not need the extra pin or the size of increase global storage card.
The differential data transmission function can increase the compatibility of flash memory cards in conjunction with old (legacy) function (clock data transmission).For instance, an adjustment uses the secure digital storage card of high-speed serial bus can be called as hypervelocity secure digital storage card (Very-high-speed SD card; VSD card), the main frame that can link up with hypervelocity secure digital storage card then is a hypervelocity secure digital storage card main frame, hypervelocity secure digital storage card with old function, can be used as the secure digital storage card when inserting old secure digital storage card main frame uses, hypervelocity secure digital storage card main frame with old function also can read the secure digital storage card of insertion, therefore, hypervelocity secure digital storage card and main frame are backward compatibility (backward compatible).
For instance, Fig. 3 illustrates secure digital storage card main frame 38 and receives multimedia storage card (MMC card) 32, secure digital storage card (SD card) 30 or hypervelocity secure digital storage card (VSD card) 34, main frame 38 comprises old secure digital storage card console controller 39, can detect and receive secure digital storage card 30 or multimedia storage card 32.And when hypervelocity secure digital storage card 34 inserts, it is a secure digital storage card that secure digital storage card console controller 39 can be detected, and hypervelocity secure digital storage card 34 is set at the secure digital storage card of 9 pins of the standard of operating in and secure digital memory card bus 36.
Fig. 4 illustrates expansion type hypervelocity secure digital storage card main frame 42, and can receive multimedia storage card 32, secure digital storage card 30 or hypervelocity secure digital storage card 34.Expansion type hypervelocity secure digital storage card main frame 42 is the hypervelocity safe memory card main frames that can detect and can receive multimedia storage card 32, secure digital storage card 30 or hypervelocity secure digital storage card 34.When multimedia storage card 32 inserted, expansion type hypervelocity secure digital storage card main frame 42 utilized 7 pins of hypervelocity secure digital memory card bus 40, used multimedia storage card pin and agreement to link up; And when secure digital storage card 30 inserted, expansion type hypervelocity secure digital storage card main frame 42 utilized 9 pins of hypervelocity secure digital memory card bus 40, and digital memory card pin safe in utilization and agreement are linked up.
When hypervelocity secure digital storage card 34 inserts, it is a hypervelocity secure digital storage card that the hypervelocity secure digital storage card console controller 41 that is positioned at expansion type hypervelocity secure digital storage card main frame 42 can be detected, and hypervelocity secure digital storage card 34 is set operates in augmented pattern (extended mode), for example transmit as the high-speed serial bus standard of USB (universal serial bus) (USB) and use by hypervelocity secure digital memory card bus 40.The higher bandwidth data transmission also can be used for example by hypervelocity secure digital memory card bus 40 and carry out as serial bus standards such as USB (universal serial bus), IEEE 1394, SATA or PCI Express.
Hypervelocity secure digital storage card 34 has the configuration of 9 metal gaskets identical with secure digital storage card 30, yet but comprise the internal controller (not shown), and can couple the internal serial bus controller, but not general secure digital memory card controller to metal gasket.For instance, when hypervelocity secure digital storage card 34 operated in expansion type hypervelocity secure digital storage card pattern, the USB controller of hypervelocity secure digital storage card 34 inside can be couple on these some metal gaskets.
Fig. 5 carries out the schematic flow sheet of routine detecting by hypervelocity secure digital storage card main frame for expansion type hypervelocity secure digital storage card.Main frame, be personal host computer for example, when inserting slot, storage card detects, as step 240, for example utilize detecting storage card detecting pin (card detect (CD) pin) to give drawing (pull high), or utilize detecting storage card switch to be started by the mechanical property on the storage card by the resistance on secure digital storage card or the hypervelocity secure digital storage card.Hypervelocity secure digital storage card main frame sends one and comprises the sequence command of CMD55 instruction to the storage card that is inserted, as step 242, if storage card is not suitably responded the CMD55 instruction, as step 244, then this storage card may be the multimedia storage card or the storage card of single-mode, but not secure digital storage card or hypervelocity secure digital storage card.Then, transmission includes a sequence command of CMD1 instruction to storage card, as step 246, if storage card has suitably been responded the CMD1 instruction, then this storage card is a multimedia storage card, then, utilize sequence command to give initialization multimedia storage card, for example main frame reads the Configuration Registrar (configuration registers) on the multimedia storage card, as step 248, main frame uses 7 shared pins to link up with multimedia storage card, if storage card is suitably responded, then main frame may try to utilize and switch to different patterns and link up with storage card.
If the storage card that is inserted has suitably been responded the CMD55 instruction, as step 244, then this storage card may be hypervelocity secure digital storage card or secure digital storage card, then further transmit and include the into order of rank hypervelocity secure digital storage card instruction ACMD1, as step 250, if storage card is not suitably responded the ACMD1 instruction, as step 252, then this storage card can not be hypervelocity secure digital storage card.The sequence command of the ACMD41 instruction that then will send the CMD55 instruction once more and continue, as step 254, wherein the ACMD1 instruction is that instruct on the specifically defined rank of advancing, only there is hypervelocity secure digital storage card to respond in mode as expected, for instance, hypervelocity secure digital storage card may be responded a unique coding (unique code) that is only used by hypervelocity secure digital storage card.
If storage card has suitably been responded CMD55 instruction and ACMD41 instruction, as step 256, then this storage card is the secure digital storage card, then, utilize sequence command to give with the initialization of secure digital storage card, for example main frame reads the Configuration Registrar (configuration registers) on the secure digital storage card, as step 258.Main frame has used 9 pins of secure digital memory card interface to link up with the secure digital storage card, main frame can digital memory card interface safe in utilization a data signal line or how to link up to four data signal lines, the data that are stored in the secure digital storage card can utilize the high-order security protocol to be encrypted (encrypted).
If storage card is not suitably responded CMD55 instruction and ACMD41 instruction, as step 256, then this storage card is the storage card of other kinds, can carry out further storage card identification then, or routine storage card detecting failure.
If storage card has suitably been responded the ACMD1 instruction, as step 252, then this storage card is a hypervelocity secure digital storage card, as step 262, the expansion type main frame can utilize storage card to be analyzed at this instruction or the response of other instructions, as step 264, and set up the purposes and the attribute (personality and capabilities) of hypervelocity secure digital storage card, as step 266.
Hypervelocity secure digital storage card is then given initialization by a sequence command, such as main frame reads the Configuration Registrar (configuration registers) on the hypervelocity secure digital storage card, as step 268.One of them expansion type serial bus protocol processor is activated, and is connected to 9 metal gaskets of hypervelocity secure digital storage card partly, and allows the data transmission under the augmented pattern.
Fig. 6 is that the hypervelocity secure digital storage card routine of utilizing hypervelocity secure digital storage card to carry out is detected the schematic flow sheet of responding.After inserting host slot and energising, hypervelocity secure digital storage card utilizes metal contact pad to be powered, as step 280, the storage card initialization routine starts then, as step 282, wherein, may include various inside oneselfs detects, the controller of hypervelocity secure digital storage card inside will be carried out these routines, start external interface, then and wait for the instruction that comes from main frame, if this is the storage card of single-mode, then storage card can wait for that main frame switches to model identical and links up, if be not the storage card of a single-mode, then wait is come from the CMD55 instruction of main frame, as step 284.
After the CMD55 command reception that comes from main frame, hypervelocity secure digital memory card controller comes from wait the ACMD1 instruction of main frame, as step 286, the mode that utilize to show storage card support and available expansion type serial bus protocol, hypervelocity secure digital storage card is responded the ACMD1 instruction that comes from hypervelocity secure digital storage card main frame, as step 288, main frame will be by selecting the allowed protocol that main frame is also supported in the tabulation, storage card changes its bus transfer device and is connected to 9 pins of one of them expansion type serial bus protocol processor to secure digital storage card partly, as step 290, for instance, may support USB (universal serial bus).
Main frame transmits one and instructs hypervelocity secure digital memory bank, indicate the agreement that is adopted, as step 292, hypervelocity secure digital storage card is then with the selected protocol processor of initialization, and it is couple to the suitable pin of hypervelocity secure digital memory card bus, then, hypervelocity secure digital storage card will receive the further instruction that comes from main frame, as step 294.
System block diagrams, Fig. 7, Fig. 8
Fig. 7 is main frame 51 systems with hypervelocity secure digital card connector slot 50, it supports the communication of augmented pattern, and can insert multimedia storage card 32, secure digital storage card 30 or hypervelocity secure digital storage card 34 hypervelocity secure digital card connector slot 50 to main frame 51, each storage card can be operated under mode standard separately.
The contact pin that is positioned at hypervelocity secure digital card connector slot 50 is connected to multi-usage bus switch 52, and secure digital storage card protocol processor 56.The forwarder (not shown) buffering that is positioned at multi-usage bus switch 52 for and from the data of the differential data signals line of the transmission of pairing and reception, this differential data signals line is positioned at expansion type agreement metallic contact, for example advances rank supplementary technology (SATA) or even multimedia storage card (Multi Media Card early for the peripheral device element connects express delivery (PCI Express), live wire (Firewire) IEEE 1394, system for serial small computer interface (SerialAttached SCSI) and string type; MMC).
When the routine initialization of carrying out when host processor. system 68 has determined that the storage card that inserts is multimedia storage card, multimedia storage card protocol processor 58 can be activated with the multimedia storage card 32 that inserts hypervelocity secure digital card connector slot 50 and link up, and secure digital storage card protocol processor 56 can be by anergy.And when the storage card of host processor. system 68 decision insertions was multimedia storage card, purposes selector switch 54 was set multi-usage bus switchs 52 and is connected hypervelocity secure digital card connector slot 50 media store card protocol processor 58 at the most; And when the storage card that inserts was secure digital storage card 30, after initialization was finished, secure digital storage card protocol processor 56 can continue to link up with storage card.
Carry out the routine initialization when utilizing host processor. system 68, and the storage card that inserts of decision is when being hypervelocity secure digital storage card 34, secure digital storage card protocol processor 56 can continue to link up with hypervelocity secure digital storage card 34, up to the performance that has determined hypervelocity secure digital storage card 34.Then, select one of them higher speed serial bus protocol to use, for instance, support PCI Express (PCIE) agreement when host processor. system 68 has determined hypervelocity secure digital storage card 34, purposes selector switch 54 is set multi-usage bus switch 52 and is connected hypervelocity secure digital card connector slot 50 to PCIE protocol processors 62.Then, after the PCIE augmented pattern started, host processor. system 68 can be linked up with PCIE protocol processor 62, rather than secure digital storage card protocol processor 56.
Carry out the routine initialization when utilizing host processor. system 68, and the storage card that inserts of decision is a hypervelocity secure digital storage card 34 and when supporting USB (universal serial bus), purposes selector switch 54 is set multi-usage bus switch 52 and is connected hypervelocity secure digital card connector slot 50 to universal serial bus protocol processor 60, then, after the USB (universal serial bus) augmented pattern starts, host processor. system 68 can be linked up with universal serial bus protocol processor 60, rather than secure digital storage card protocol processor 56.
Carry out the routine initialization when utilizing host processor. system 68, and the storage card that inserts of decision is a hypervelocity secure digital storage card 34 and when supporting SATA, purposes selector switch 54 is set multi-usage bus switch 52 and is connected hypervelocity secure digital card connector slot 50 to SATA protocol processors 64, then, after the SATA augmented pattern starts, host processor. system 68 can be linked up with SATA protocol processor 64, rather than secure digital storage card protocol processor 56.
Carry out the routine initialization when utilizing host processor. system 68, and the storage card that inserts of decision is a hypervelocity secure digital storage card 34 and when supporting Firewire, purposes selector switch 54 is set multi-usage bus switch 52 and is connected hypervelocity secure digital card connector slot 50 to IEEE 1394 protocol processors 66, then, after IEEE 1394 augmented patterns start, host processor. system 68 can be linked up with IEEE 1394 protocol processors 66, rather than secure digital storage card protocol processor 56.
Hypervelocity secure digital storage card 34 also can be supported the expansion type agreement more than, and host processor. system 68 also can be by being selected in the agreement of supporting then.For instance, host processor. system 68 can be selected the fastest available agreement, pays special attention at this, and host computer system 51 may not supported as the institute's protocols having that is illustrated among Fig. 7, still may only support the subclass (subset) of described agreement.
Fig. 8 is the calcspar with hypervelocity secure digital memory card device 71 of secure digital card connector, and supports the communication of hypervelocity secure digital storage card augmented pattern.In one embodiment, hypervelocity secure digital memory card device 71 can be the hypervelocity secure digital storage card 34 as Fig. 7 illustrated, in another embodiment, hypervelocity secure digital storage card 34 can be the subclass of all protocol processors of being had of hypervelocity secure digital memory card device 71, identical, hypervelocity secure digital storage card host computer system 51 ' also can be the host computer system 51 identical as Fig. 7, or the subclass of all protocol processors of being had of host computer system 51.
The hypervelocity secure digital storage card plug 70 of hypervelocity secure digital memory card device 71 can insert the hypervelocity secure digital memory card socket 50 of hypervelocity secure digital storage card main frame 51 ', the hypervelocity secure digital storage card plug 70 of hypervelocity secure digital memory card device 71 can insert the secure digital memory card socket 50 ' of secure digital storage card main frame 75, and it does not support hypervelocity secure digital storage card pattern; Or, the hypervelocity secure digital storage card plug 70 of hypervelocity secure digital memory card device 71 also can insert the multimedia storage card socket 50 of multimedia storage card host computer system 77 "; it is also for supporting hypervelocity secure digital storage card pattern, but supports multimedia storage card or serial circumference interface (SPI) pattern.
Hypervelocity secure digital memory card device 71 has de-vice processor system 88, be used for carrying out the formula that comprises storage card initialization and bus response, 73 of multi-usage bus interface systems use the data of variety of protocol processing from de-vice processor system 88,76 digital memory card protocol processes data safe in utilization of secure digital storage card protocol processor, and inputoutput data on the secure digital data signal line of hypervelocity secure digital storage card plug 70, the communication of other communications protocol processors and hypervelocity secure digital storage card plug 70, linked up by multi-usage bus switch 72, it selects one of them protocol processor to carry out.
Contact pin in the hypervelocity secure digital storage card plug 70 is connected to multi-usage bus switch 72 and secure digital storage card protocol processor 76, the forwarder (not shown) buffering that is positioned at multi-usage bus switch 72 for and from the data of the differential data signals line of the transmission of pairing and reception, this differential data signals line is positioned at expansion type agreement metallic contact, for example is PCI Express, Firewire IEEE 1394, SerialAttached SCSI and SATA or even multimedia storage card early.
The routine of carrying out when host processor. system 88 is initialized as the instruction of using the compatible serial circumference interface pattern of multimedia storage card and when main frame is multimedia storage card host computer system 77, multimedia storage card protocol processor 78 can be activated with the multimedia storage card host computer system 77 that is connected to hypervelocity secure digital storage card plug 70 and link up, and secure digital storage card protocol processor 76 can be by anergy.When de-vice processor system 88 uses the compatible pattern of multimedia storage card to give an order, purposes selector switch 74 is set multi-usage bus switch 72 and is connected hypervelocity secure digital storage card plug 70 to multimedia storage card protocol processor 78, when main frame is secure digital storage card host computer system 75, after initialization was finished, secure digital storage card protocol processor 76 can continue to link up with secure digital storage card protocol processor 76.
Carry out the routine initialization when utilizing main frame, and decision hypervelocity secure digital memory card device 71 and hypervelocity secure digital storage card host computer system 51 ' be when all supporting hypervelocity secure digital storage card pattern, and hypervelocity secure digital storage card host computer system 51 ' can send to instruct to de-vice processor system 88 and make it switch to hypervelocity secure digital storage card pattern by secure digital storage card protocol processor 76.Then, select one of them higher speed serial bus protocol to use, for instance, when processor system 88 is used PCIExpress by order, purposes selector switch 74 is set multi-usage bus switch 72 and is connected hypervelocity secure digital card connector plug 70 to PCI Express protocol processors 82, then, and after PCI Express augmented pattern starts, processor system 88 can be linked up with PCI Express protocol processor 82, rather than secure digital storage card protocol processor 76.
Carry out the routine initialization when utilizing main frame, and the decision storage card support of inserting is when having the hypervelocity secure digital storage card of USB (universal serial bus), de-vice processor system 88 can be switched to the USB (universal serial bus) pattern by order, purposes selector switch 74 is set multi-usage bus switch 72 and is connected hypervelocity secure digital card connector plug 70 to universal serial bus protocol processor 80, then, after the USB (universal serial bus) augmented pattern starts, processor system 88 can be linked up with universal serial bus protocol processor 80, rather than secure digital storage card protocol processor 76.
Carry out the routine initialization when utilizing main frame, and the decision storage card support of inserting is when having the hypervelocity secure digital storage card of SATA, de-vice processor system 88 can be switched to the SATA pattern by order, purposes selector switch 74 is set multi-usage bus switch 72 and is connected hypervelocity secure digital card connector plug 70 to SATA protocol processors 84, then, after the SATA augmented pattern starts, processor system 88 can be linked up with SATA protocol processor 84, rather than secure digital storage card protocol processor 76.
Carry out the routine initialization when utilizing main frame, and the decision storage card support of inserting is when having the hypervelocity secure digital storage card of Firewire, de-vice processor system 88 can be switched to the Firewire pattern by order, purposes selector switch 74 is set multi-usage bus switch 72 and is connected hypervelocity secure digital card connector plug 70 to IEEE 1394 protocol processors 86, then, after IEEE 1394 augmented patterns start, processor system 88 can be linked up with IEEE 1394 protocol processors 86, rather than secure digital storage card protocol processor 76.
Pay special attention to, hypervelocity secure digital memory card device 71 may not support that as the institute's protocols having that is illustrated among Fig. 8 in certain embodiments, hypervelocity secure digital memory card device 71 may only be supported the subclass (subset) of described various protocols.
Fig. 9 is the functional schematic of signal multiplexer 900, and it can be incorporated into the host computer system 51 of Fig. 7 or the hypervelocity secure digital memory card device 71 of Fig. 8.For instance, signal multiplexer 900 can be used to provide the hypervelocity secure digital card connector slot 50 of host computer system 51 or have the contact (pin) of hypervelocity secure digital card connector plug 70 of the hypervelocity secure digital memory card device 71 of multiple function (retouch in detail is please to consult following Figure 10,11,12A and 12B respectively).
Signal multiplexer 900 is set and provides/receive signal AIN/AOUT that comes by interface A (not shown) or the signal BIN/BOUT that comes by interface B (not shown).For instance, interface A and interface B can be respectively at the secure digital storage card protocol processor of hypervelocity secure digital storage card or host computer system and hypervelocity secure digital storage card protocol processor, multiplexing signal line 22 can be the connector that connects a metal contact pad on the storage card, or a signal wire of internal bus.
Input buffer 14 buffering signals lines 22 produce signal AIN and give interface A, and producing signal BIN, input buffer 20 buffering signals lines 22 give interface B, when input/output signal line 22 is output or drive signal, output enable signal OE will be started as high value.When interface A starts, signal ENA be logic-high value and and lock (AND gate) 10 drive a logic-high value and come activation output buffer 12, and driver enable signal AOUT is to signal wire 22.When interface B starts, signal ENB be logic-high value and and lock (AND gate) 16 drive a logic-high value and come activation output buffer 18, and driver enable signal BOUT is to signal wire 22.
It should be noted that extra (in other words, other communications protocol processors) such as interface C, D also can utilize increase and lock to carry out multiplex's processing with input, output buffer at identical signal wire 22.
Further, also can produce extra enable signal ENC, END etc., these a little interfaces can be specifications such as multimedia storage card, USB (universal serial bus), SATA, IEEE 1394, PCIE and secure digital storage card.
The interface pins allocation table
Figure 10 is the multiplexing signal allocation table with secure digital card connector of 9 pins.Power vd D is provided in pin 4, earth terminal then is provided in pin 3 (VSS1) and pin 6 (VSS2) respectively, clock is input to storage card in pin 5, and pin 7 is output/input serial data DAT0 of interfaces such as multimedia storage card, secure digital storage card, USB (universal serial bus), PCIE, STAT, IEEE 1394.
For the secure digital memory card interface, four data signal lines of as many as may be used simultaneously, although have only a data signal line between special communication short-term, to be used, for example, at the initialization procedure of storage card.Data signal line DAT0 is positioned at that pin 7, data signal line DAT1 are positioned at pin 8, data signal line DAT2 is positioned at pin 9 and data signal line DAT3 is positioned at pin 1.
When hypervelocity secure digital storage card pattern was activated the back and selects universal serial bus protocol, the USB (universal serial bus) data of serial will be transmitted two-wayly, and passed through differential data signals line D+, the D-of USB (universal serial bus).And cmd signal line, CLK signal wire and DAT0 signal wire will be connected in secure digital storage card processor, and can allow the secure digital media card communication of 1 Bit data DAT0 when the function of USB (universal serial bus) can't be used.
When hypervelocity secure digital storage card pattern was activated and selects the PCIE agreement, the serial pci data will be transmitted (in other words, transmission signal line Tp0, Tn0 and received signal line Rp0, Rn0) by two pairs of differential data signals lines.Be positioned at transmission signal line Tp0, Tn0 on the pin 2,1 and be the output of storage card and receive by main frame; Be positioned at received signal line Rp0, Rn0 on the pin 8,9 and be the output of main frame and receive by storage card.
After hypervelocity secure digital storage card pattern is activated, and when selecting the SATA agreement, the serial ATA data will be by by two pairs of differential data signals lines transmission (in other words, a-signal line A+, A-and B signal wire B+, B-).A data line A+, the A-that lays respectively at pin 2,1 is the output of main frame and being received by storage card; B data line B+, the B-that lays respectively at pin 8,9 is the output of storage card and being received by main frame.When SATA was used, the secure digital media card communication will interrupt.
After hypervelocity secure digital storage card pattern is activated, and when selecting the Firewire agreement, serial i EEE 1394 data will be by by two couples of transmission of differential data signals lines (in other words, a-signal line TPA, TPA
*And B signal wire TPB, TPB
*).Lay respectively at signal wire TPA, the TPA of pin 2,1
*For the output of storage card is received by main frame; Lay respectively at signal wire TPB, the TPB of pin 8,9
*For the output of main frame is received by storage card.When IEEE 1394 was used, the secure digital media card communication will interrupt.
Figure 11 is the multiplexing signal allocation table with multimedia storage card connector of 7 pins, old main frame may only be supported multimedia storage card, this embodiment supports USB (universal serial bus), secure digital storage card, serial circumference interface and multimedia storage card, but other for example are that SATA, IEEE 1394 are then unassisted with PCIE.Although have 6 multimedia storage card signal pins, at the entity interface of 7 pins, the multimedia storage card interface has extra, an obsolete pin.Power vd D is provided in pin 4, earth terminal VSS1, VSS2 then are provided in pin 3,6, the clock that is input into storage card is positioned at signal wire 5, pin 7 is the output/input serial data DAT0 at interfaces such as multimedia storage card, secure digital storage card and USB (universal serial bus), then is data DOUT at serial circumference interface.
After hypervelocity secure digital storage card pattern is activated, and select USB (universal serial bus), differential data signals line D+, the D-of the USB (universal serial bus) that the USB (universal serial bus) data of serial will be by being positioned at pin 2,1 are transmitted two-wayly.Therefore, but when 7 pin times spent are only arranged, USB (universal serial bus) still is supported.
Figure 12 A is the multiplex's pin allocation table that extends to the connector of 13 pins, pin 10～13 is used on the expansion type secure digital memory card interface as data pin DAT4～7, and can be kept at the serial bus interface of the multimedia storage card specification of the 4.0th version.
Figure 12 B is multiplex's pin allocation table of the memory stick memory card system of 10 pins, is different from digital memory card safe in utilization, and it is the agreement of benchmark that the expansion type interface also can design at other storage cards, is memory stick storage card (Memory Stick for example; MS).The memory stick storage card has the connector of 10 pins, power supply is positioned at pin 3,9, earth terminal is positioned at pin 1,10, pin 8 is system clock input SCLK, and pin 2 is bus state input BS, the data DAT0 that the data utilization is positioned at pin 4 carries with coming twocouese, and pin 6 is for inserting pin INS, can utilize the resistor of memory stick storage card to be drawn high to detect to point out the storage card that inserted.
At the augmented pattern that the memory stick storage card has USB (universal serial bus), a pair of differential data D+ of pin 4,3 load USB (universal serial bus), D-, other pins then are used for load memory stick storage card or the signal of MS Pro Duo; At the PCIE augmented pattern, a pair of PCI transmission of pin 4,3 loads differential data T+, T-, and a pair of PCI of pin 7,5 loads receives differential data R+, R-; Identical, at the SATA augmented pattern, a pair of SATA transmission of pin 4,3 loads differential data T+, T-, and a pair of SATA of pin 7,5 loads receives differential data R+, R-; At IEEE 1394 augmented patterns, a pair of 1394A differential data of pin 4,3 loads TPA, TPA
*, and a pair of 1394B differential data of pin 7,5 loads TPB, TPB
*
Noticeable, physical arrangement at storage card itself, it has used various material to form storage card substrate, circuit board, metallic contact, storage card shell etc., plastic shell can have multiple shape, and can be partly or the covering board or the different parts of connector fully, and also can form the part of connector, different shapes and pattern also can be substituted, and pin can be meant planar metal lead or the shape of other contact terminals rather than sharp-pointed ailhead (pointed spikes) shape.
The agreement of many expansions, for example can use as second interface for PCI Express, USB (universal serial bus), Serial ATA, SerialAttached SCSI or Firewire IEEE 1394, main frame also can be supported various serial bus interfaces, and the preferentially operation of test all-purpose universal serial bus, be IEEE1394, SATA, SA SCSI etc. in regular turn then, just switching to the comparison high-speed interface then at last, is PCI Express for example.
In addition, please pay special attention to, the description of secure digital storage card is mainly only as the example illustrative purposes, and the secure digital storage card also can be substituted by memory stick storage card (MS), MS Pro card, MS Duo card, mini secure digital storage card (mini SD card), lower size multimedia storage card (reduced sizeMMC) etc.; The switch of hardware also can replace the storage card detecting step of some routines, for instance, can have recess to engage the switch of storage card slot in the increase of storage card shell.
In addition, also can design special light emitting diode and notify the user, which electrical interface is to use at present, for instance, if the secure digital memory card interface of the standard of use, then light emitting diode can be opened, otherwise, light emitting diode then can be closed; Surpass 2 pattern if having, then can use the light emitting diode of multiple color to indicate various patterns, for example green expression PCI Express, yellow expression USB (universal serial bus).
In addition, also can adopt different power supply unit voltage, USB (universal serial bus) and SATA use 5 volts voltage, and secure digital storage card and multimedia storage card use 3.3 volts voltage, and PCIE uses 1.5 volts voltage.Utilization is supplied to power pin VCC with 3.3 volts of voltages, produce other voltage then by the electric pressure converter of hypervelocity secure digital storage card inside, for example use charge pump (charge pump) to produce 5 volts of voltages, use DC-DC transformer (DC to DC converter) to produce 1.5 volts of voltages.
PCI Express system bus management function can utilize two pairs of differential signals of the PCIE interface in the VSD to be reached, clock signal, be the signal that can use extra connection gasket to be increased for example for REFCLK+, REFCLK-, the sideband signal of PCIE (sideband signals) can utilize extra connection gasket to increase, for example be CPPE#, CPUSB#, CLKREQ#, PERST#, WAKE# ,+signals such as 3.3AUX, SMBDATA, SMBCLK.In addition, use the method for adjusted PCIE signal, also can be applied in the design of the serial buffer memory module of dynamic random access memory body.
Description in view of above-mentioned multi-usage flash memory cards, known as can be seen storage card is the restriction of the communications protocol (for example being secure digital storage card, multimedia storage card, tight flash memory cards) on basis, can utilize the performance in conjunction with the high speed communication protocol interface of second kind of standard to overcome, be USB (universal serial bus), SATA, Firewire or PCI Express for example.
Yet, according to another one embodiment, flash memory cards with and/or console controller also can include particular memory card differential data transmission logical circuit, come the transmission of activation differential data between flash memory cards and host apparatus.
For instance, Figure 13 A illustrates the embodiment synoptic diagram that host apparatus 1302 and flash memory cards 1301 utilize differential signal DDAT to link up, host apparatus 1302 can be the electronic installation of any kenel, and has an interface of flash memory cards, be digital camera, MP3 player or sound-track engraving apparatus etc. for example, flash memory cards 1301 may include any type of flash memory cards, comprises multimedia storage card, secure digital storage card, memory stick storage card or tight flash memory cards.Wherein it should be noted that, when flash memory cards 1301 inserts the slot 1303 of host apparatus 1302, link up between flash memory cards 1301 and the host apparatus 1302 when utilizing breakout box or expander to be coupled to slot 1303 (or flash memory cards 1301), for more clearly explanation, flash memory cards 1301 is to separate with host apparatus 1302 among Figure 13 A.
The similar data routing 111,121 that is illustrated in the known multimedia storage card of Figure 1A, differential data path 1330,1370 can provide transformation from serial to parallel input and parallel commentaries on classics serial output, the frame detecting is normal in order to the read of guaranteeing bank array 113, and bug check (the general crc check of signal SDAT and CMD).Yet differential data path 1330,1370 also can provide the encoding and decoding of differential data, but and the differential data communication of activation between flash memory cards 1301 and host stores card controller 1340.
Simultaneously, the protocol controller 1320,1360 that lays respectively at flash memory cards 1301 and host stores card controller 1340 can be operated as the multimedia storage card protocol controller 112,122 that is illustrated in Figure 1A haply.Especially the protocol controller 1320 of flash memory cards 1301 can be carried out suitably operation (such as the read of bank array 1310 and processing of utilizing the package value mistake that differential data path 1330 detected), respond the status signal ST and the data-signal DAT of input, and control signal CTRL and data-signal DAT (such as the indicated value of passing through or failing and data of read/write) are suitably exported in generation after finishing these a little operations.
Same, the protocol controller 1360 of host stores card controller 1340 can produce and suitably export control signal CTRL and data-signal DAT (such as the instruction of read/write and bank-address), respond from the instruction of using converter 1350, and carry out status signal ST and the data-signal DAT that input is responded in suitably operation (reading of data or the affirmation of write operation for example are provided).It should be noted that data-signal DAT and status signal ST can utilize protocol controller 1360 directly to provide to give host apparatus 1302, or it is converted to the particular host communications protocol by the particular memory card communications protocol by using converter 1350.As Figure 1A at the description of using converter 123, use converter 1350 and can be used as bridge between particular host communication and the particular memory card communication.
Communication between flash memory cards 1301 and the host apparatus 1302 gives initialization when utilizing flash memory cards 1301 to insert slot 1303, and start flash memory cards 1301, then, using converter 1350 can provide instruction (for example reading or write the life life) from host apparatus 1302 to protocol controller 1360, it is continued provides appropriate control signals CTRL, data-signal DAT to differential data path 1370.Continue control signal CTRL and data-signal DAT be converted into differential signal DDAT in differential data path 1370, and can transmit by the differential data path 1330 of flash memory cards 1301, differential data path 1330 is decoded as status signal ST and data-signal DAT with differential data DDAT, makes protocol controller 1320 to carry out desired operation (unless wrong transmission takes place to be pointed out by differential data path 1330) in bank array 1310.Protocol controller 1320 is replied one and is responded and any related data that comes from bank array 1310, be sent to differential data path 1330 by control signal CTRL and data-signal DAT, after differential data path 1330 is converted to differential signal DDAT with control signal CTRL, data-signal DAT, be back to the differential data path 1370 of host stores card controller 1340.Then, differential data path 1370 is decoded as status signal ST and data-signal DAT with the differential data signals DDAT of input, and the particular host signal uses for host apparatus 1302 and can be converted into suitably.
Communication between flash memory cards 1301 and the host apparatus 1302 can be considered as the affairs (1ayeredtransaction) of level, under extraction in various degree (at varying levels of abstraction), (across the different layers) comes transmission information when passing different levels, for instance, Figure 13 B illustrates the synoptic diagram of communication between flash memory cards 1301 and the host apparatus 1302, illustrate by forming the various levels that communication stacks, protocol layer 1392 and application layer 1393 are virtual connection (illustrate among the figure and be dotted line) between host apparatus 1302 and flash memory cards 1301, in application layer 1393, the flash volume array 1310 of the application converter 1350 meeting access flash storage cards 1301 of host apparatus 1302, the affairs of these the superiors can utilize protocol layer 1392 to be reached, and wherein protocol controller 1320 is crossed in the communication meeting of application-specific, 1360 are translated into the communication of particular memory card.The communication of protocol layer can utilize Physical layer 1391 to be achieved, wherein physical signal (in other words, differential signal DDAT and selectable old signal SDAT, CMD and CLK) will be transmitted by memory card bus 1390 between host apparatus 1302 and flash memory cards 1301.
Wherein, the function of the differential data transmission of host apparatus 1302 and flash memory cards 1301 can utilize Physical layer 1391 to realize, therefore allows to use any storage card agreement to realize protocol controller 1360,1320 respectively.For instance, in this embodiment, protocol controller 1360,1320 can include the specific multimedia storage card protocol signal (such as signal CTRL, ST and DAT) that standard multimedia storage card protocol controller uses standard.In the embodiment of other variations, protocol controller 1320,1360 can include secure digital storage card, memory stick storage card or the tight flash memory cards protocol controller of standard, use producing and specific secure digital storage card, specific memory stick storage card or the protocol signal of specific tight flash memory cards are responded in running, the use of known specific flash memory cards protocol controller has the realization of simplifying the high-speed-differential communication.
For instance, known host apparatus with known clock data and multimedia storage card communication can be reset to the differential data communication, only need to replace existing standard multimedia storing card data path (the multimedia storage card data routing 121 that for example replaces among Figure 1A is differential data path 1370) with the differential data path simply, if the multimedia storage card data routing is realized (or other re-programmable forms) in the firmware mode, then reset and become simplyr, only need firmware update is realized that the differential data path gets final product.
Also particularly point out at this, the use of standard particular memory card protocol controller (such as multimedia storage card protocol controller or secure digital storage card protocol controller), can allow host stores card controller 1340 with and/or flash memory cards 1301 (seeing Figure 13 A), according to the characteristic of interface arrangement/storage card, and optionally carry out differential data transmission and clock data transmission.For instance, protocol controller 1360 can include standard multimedia storage card protocol controller, and be coupled to differential data path 1370 and old data routing 1370L simultaneously, then, link up by standard time clock command signal CMD and serial data signal SDAT, old data routing 1370L can become standard multimedia storing card data path, according to this method, host stores card controller 1340 can utilize and use known clock data transmission to carry out communication with known multimedia storage card, also can use higher speed when utilizing the multimedia storage card of differential data activation, the differential data transmission of low power consuming.
Similarly, the protocol controller 1320 of flash memory cards 1301 also can include known multimedia storage card protocol controller, be coupled to differential data path 1330 and old data routing 1330L simultaneously, wherein old data routing 1330L can include known multimedia storage card data routing; According to this method, flash memory cards 1301 can utilize and use the next and known multimedia storage card of known clock data transmission to carry out communication as the host apparatus on basis, simultaneously also can be when utilization have the host apparatus of differential data activation, the differential data transmission of changeable use higher speed, low power consuming.
Figure 14 A illustrates mechanical appearance specification (the mechanical form factor diagram) synoptic diagram of the compatible storage card 1301A of multimedia storage card of version 3 .31, the function of differential data transmission is provided, and the pin of the compatible storage card 1301A of the multimedia storage card of version 3 .31 is allocated as follows shown in the tabulation 3.
Table 3
| The pin numbering | Title |
| P1 | D- |
| P2 | CMD (OPT.) |
| P3 | VSS1 |
| P4 | VDD |
| P5 | CLK(OPT.) |
| P6 | VSS2 |
| P7 | D+/DAT0 |
Storage card 1310A includes pin P1～P7, the multimedia storage card (such as multimedia storage card 110A that Figure 1B illustrated) that is equal to known version 3 .31, pin P3, P4, P6 are respectively in order to receive the power pin of voltage VSS1, VDD, VSS2, yet, be different from and only utilize pin P7 as data (DAT0) pin, storage card 1301A uses pin P1, P7 to transmit/receives signal D-, the D+ (in other words, as Figure 13 A differential signal DDAT) of the complementation of formation differential signal respectively.
If the compatible storage card 1301A of multimedia storage card also includes standard multimedia storing card data path (such as Figure 13 A illustrated old data routing 1330L), pin P2, P5, P7 can use at signal CMD according to prior art method, CLK, and serial data signal DAT0 (such as serial data signal SDAT of Figure 1A), wherein pin P7 is dual-purpose pin, when transmitting, clock data can provide serial data signal DAT0, and when differential data transmission, can provide differential signal D+, in this mode, the multimedia storage card of differential data transmission activation can be possessed Dimensions and pin configuration, and is compatible to the host apparatus of known multimedia storage card for the basis.
Figure 14 B illustrates mechanical appearance specification (the mechanical form factor diagram) synoptic diagram of the compatible storage card 1301B of multimedia storage card of edition 4 .0, the function of differential data transmission is provided, and the pin of the compatible storage card 1301B of the multimedia storage card of edition 4 .0 is allocated as follows shown in the tabulation 4.
Table 4
| The pin numbering | Title |
| P1 | D-/DAT3 |
| P2 | CMD(OPT.) |
| P3 | VSS1 |
| P4 | VDD |
| P5 | CLK(OPT.) |
| P6 | VSS2 |
| P7 | D+/DAT0 |
| P8 | A+/DAT1 |
| P9 | A-/DAT2 |
| P10 | B+/DAT4 |
| P11 | B-/DAT5 |
| P12 | C+/DAT6 |
| P13 | C-/DAT7 |
The compatible storage card 1301B of multimedia storage card summary is similar to the storage card 1301A of Figure 14 A, except extra pin P8～P13 at complementary signal A+, A-, B+, B-, C+, C-uses, pointed as above-mentioned pin allocation list, therefore can provide three extra differential data passage (A+/A-, B+/B-, and C+/C-), it should be noted that, compatibility for multimedia storage card device that known edition 4 .0 is provided, pin P8～P13 can be dual-purpose pin, and can when clock data transmits, provide clock serial data signal DAT1～DAT7 respectively.
Wherein, the flash memory cards at other various kenels also can not change under the Dimensions or the situation of pin compatibility modification approx.For instance, Figure 14 C illustrates mechanical appearance specification (the mechanical form factor diagram) synoptic diagram of secure digital storage card 1301C, and having the function of differential data transmission, the pin of secure digital storage card 1301C is allocated as follows shown in the tabulation 5.
Table 5
| The pin numbering | Title |
| S1 | D-/DAT3 |
| S2 | CMD(OPT.) |
| S3 | VSS1 |
| S4 | VDD |
| S5 | CLK(OPT.) |
| S6 | VSS2 |
| S7 | D+/DAT0 |
| S8 | A+/DAT1(OPT.) |
| S9 | A-/DAT2(OPT.) |
Secure digital storage card 1301C includes pin S1～S9, wherein pin S3, S4, S6 are respectively in order to receive the power pin of voltage VSS1, VDD, VSS2, pin S1, S7 transmit/receive signal D-, the D+ of the complementation that constitutes differential signal respectively, make to be utilized differential signal to come in addition communication between secure digital storage card 1301C and the host apparatus.In one embodiment, pin S8, S9 can provide other differential data path to give complementary signal A+ respectively, A-, if (in other words secure digital storage card 1301C also includes standard security digital memory card data routing, the old data routing 1330L that is illustrated as Figure 13 A), then secure digital storage card 1301C can be in pin S5 receive clock signal CLK, and pin S7, S8, S9, S1 then can be used to provide clock serial data signal DAT0 respectively, DAT1, DAT2, DAT3 uses (pin S1, S7 or possibility S8, S9 is all dual-purpose pin).
Illustrate for another example, Figure 14 D illustrates mechanical appearance specification (the mechanical form factor diagram) synoptic diagram of memory stick storage card 1301D, and having the function of differential data transmission, the pin of memory stick storage card 1301D is allocated as follows shown in the tabulation 6.
Table 6
| The pin numbering | Title |
| M1 | VSS |
| M2 | BS |
| M3 | D-/DAT1 |
| M4 | D+/DAT0 |
| M5 | A-/DAT2 |
| M6 | INS |
| M7 | A+/DAT3 |
| M8 | SCLK(OPT.) |
| M9 | VCC |
| M10 | VSS |
Memory stick storage card 1301D includes pin M1～M10, wherein pin M1, M9, M10 are respectively in order to receive the power pin of voltage VSS, VCC, VSS, pin M2, M6 provide respectively and give the needed bus state signal BS of memory stick storage card standard and insert signal INS, therefore, pin M3, M4 use at signal D-, the D+ of the complementation that constitutes differential signal respectively, make to be utilized differential signal to come in addition communication between memory stick storage card 1301D and the host apparatus.Selectively, pin M5, M7 can provide other differential data path to give complementary signal A+, A-respectively, if (in other words memory stick storage card 1301D also includes standard memory stick storing card data path, the old data routing 1330L that is illustrated as Figure 13 A), then memory stick storage card 1301D can be in pin M8 receive clock signal SCLK, and pin M4, M3, M5, M7 then can be used to provide clock serial data signal DAT0, DAT1, DAT2, DAT3 use (pin M3, M4 or possibility M5, M7 are all dual-purpose pin) respectively.
Figure 15 A illustrates the specific embodiment synoptic diagram of the flash memory cards 1301 of Figure 13 A.Protocol controller 1320 includes core engine (core engine) 1321, selectable buffer random access memory bank (bufferRAM) 1322 and selectable bug check circuit (error checking circuit; ECC) 1323, core engine 1321 is come control store volume array 1310 according to status signal ST and input data signal DAT, and produces control signal CTRL and outputting data signals DAT (as the description of the above-mentioned Figure 13 A of correspondence) conduct response.Buffer random access memory bank 1322 can comprise and cushions input, outputting data signals DAT and compensated at the 1310 slower access times of bank array, at last, bug check circuit (ECC) 1323 can be contained in protocol controller 1320 and confirms and suitably keep the signal integrity of signal CTRL, ST, DAT (integrity).
In one embodiment, differential data path 1330 includes difference serial interface engine 1331 and difference transceiver (transceiver) 1332, difference serial interface engine 1331 provides any coding/decoding, serialization/anti-serialization and the subpackage (packetization) of signal CTRL, ST, DAT, satisfies the demand (detailed description sees also following description corresponding to Figure 16 A) of suitable differential signal transmission.Difference serial interface engine 1331 generation/reception multi-usages (data with and/or command information) serial signal SERS, and be converted to differential data signals DDAT by difference transceiver 1332, therefore, the differential data transmission between storage card 1301 and the differential data transmission activation host apparatus is carried out.
Figure 15 B illustrates the specific embodiment synoptic diagram of the host apparatus 1302 among Figure 13 A, and it also can be connected with the flash memory cards 1301 among Figure 15 A.Protocol controller 1360 includes core engine (core engine) 1361, selectable buffer random access memory bank (buffer RAM) 1362 and selectable bug check circuit (error checking circuit; ECC) 1363, in response to using converter 1350, core engine 1361 produces the control signal CTRL and the data-signal DAT of suitably output, and handles the status signal ST and the data-signal DAT that import and use converter 1350 (as the description that is set forth in Figure 13 A on the correspondence).Buffer random access memory bank 1362 can comprise and cushions input, outputting data signals DAT and compensated at the data frequency range of data-signal DAT and the difference (differences) used between the data processing performance of converter 1350 (or host apparatus), at last, bug check circuit 1363 can be contained in protocol controller 1360 and confirms and suitably keep the signal integrity of signal CTRL, ST, DAT (integrity).
Simultaneously, differential data path 1370 includes difference serial interface engine 1371 and difference transceiver (transceiver) 1372, as the difference serial interface engine 1331 in flash memory cards 1301 (seeing Figure 15 A), difference serial interface engine 1371 provides any coding/decoding, serialization/anti-serialization and the subpackage (packetization) of signal CTRL, ST, DAT, satisfies the demand (detailed description sees also following description corresponding to Figure 16 B) of suitable differential signal transmission.Difference serial interface engine 1371 generation/reception multi-usage serial signal SERS, and be converted to differential data signals DDAT by difference transceiver 1372, therefore, the differential data transmission between host apparatus 1302 and the differential data transmission activation flash memory cards is carried out.
Figure 16 A illustrates the specific embodiment synoptic diagram of the difference serial interface engine 1331 among Figure 15 A.Difference serial interface engine 1331 includes and reads first in first out (first in first out; FIFO) memory bank 1621, parallel serial convertor 1622, scrambler 1623, Cyclical Redundancy Check (the cyclic redundancycheck of changeing; CRC) generator 1624, command initialization circuit 1625, synchronous generator 1626, package ending (end of packet; EOP) generator 1627, write first in first out memory bank 1631, transformation from serial to parallel converter 1632, demoder 1633, Cyclical Redundancy Check detector 1634, command detector 1635, detector 1636, package ending detector 1637, start frame (start of frame synchronously; SOF) detector 1638 and phase-locked loop (phase locked loop; PLL) 1639.Can come the activation serial data transmission by the data subpackage as the difference serial interface engine 1331 that is illustrated among Figure 16 A, thereby can eliminate the clock data transmission requirements, wherein need give special heed to, the storage card agreement of lower floor (such as multimedia storage card agreement) self may include the form of some subpackages, makes difference serial interface engine (SIE) 1331 to be carried out subpackage at lower floor's packet data simply.
The decoded signal that utilizes demoder 1633 to be produced can utilize transformation from serial to parallel converter 1632 to give parallelization (parallelized) to make its processing more efficient, then, data will be sent to and write first in first out memory bank 1631, Cyclical Redundancy Check detector 1634, command detector 1635, synchronous detector 1636, package ending detector 1637 and start frame detector 1638.Detector 1636 is distinguished the synchronizing information group at input signal synchronously, when detecting the synchronizing information group, can utilize provides start signal START to writing first in first out memory bank 1631, Cyclical Redundancy Check detector 1634, command detector 1635 and start frame (start of frame; SOF) detector 1638, begin the reception of package.
Respond start signal START, begin to write the content (from the signal of transformation from serial to parallel converter 1632) that first in first out memory bank 1631 stores input signal, Cyclical Redundancy Check detector 1634 can carry out the action of Cyclical Redundancy Check at the input data simultaneously.If different Cyclical Redundancy Check forms is used to check that (such as CRC7 is used for checking order for order and data-signal, and CRC16 is used for checking data), the block of whether being imported by 1635 decisions of command detector is order block or block, and use and indicate Cyclical Redundancy Check detector 1634, please note, if the testing result of Cyclical Redundancy Check is failure, can there be various error handler to carry out, and comprise terminator, require again transmission command/data etc.
Simultaneously, start frame detector 1638 carries out the detecting of start frame message block at the input data, and testing result frame clock frequency (frame timing frequency) provided give phase-locked loop 1639, and being responded, it produces local clock signal LCLK (the start frame message block can utilize host apparatus to be inserted in the input signal) in the time interval of rule.As a result, local clock signal LCKL can with in host apparatus, be used in the clock synchronisation of the former native system of input signal coding originally, and can be used as the answer clock of input signal.
At last, when package ending detector 1637 detects package ending message block, package ending detector 1637 can utilize issue termination signal STOP to writing first in first out memory bank 1631, Cyclical Redundancy Check detector 1634, command detector 1635, package ending detector 1637 and start frame detector 1638, finish the reception of package, then, protocol controller 1320 reads packet data (can be status signal ST or data-signal DAT) by writing first in first out memory bank 1631, just begins the reception of next package then.Utilize this mode, what write that first in first out memory bank 1631, Cyclical Redundancy Check detector 1634, command detector 1635, package ending detector 1637 and start frame detector 1638 can be used as difference serial interface engine 1331 separates subpackage (de-packetizing) logical circuit.
Control signal CTRL with and/or data-signal DAT utilize protocol controller 1320 to be replied, then and be stored into and read first in first out memory bank 1621, simultaneously, Cyclical Redundancy Check generator 1624 and synchronous generator 1626 can produce Cyclical Redundancy Check message block and synchronizing information group respectively at output signal, please note, if different Cyclical Redundancy Check forms uses at order and data packet, command initialization circuit 1625 will provide suitably to indicate and give Cyclical Redundancy Check generator 1624.The content that reads first in first out memory bank 1621 then can be sent to the parallel serial convertor 1622 that changes and give serialization, and when each package finishes, package ending generator 1627 will be issued package ending message block, utilize this mode, read subpackage (packetizing) logical circuit that first in first out memory bank 1621, Cyclical Redundancy Check generator 1624, command initialization circuit 1625, synchronous generator 1626 and package ending generator 1627 can be used as difference serial interface engine 1331.
Parallel commentaries on classics serial convertor 1622 then will be imported parallel data and be converted to serial data crossfire (bitstream), continue and encode by scrambler 1623, as above-mentioned description at demoder 1633, scrambler 1623 is also used predefined coding protocol to the bit crossfire from parallel commentaries on classics serial convertor 1622, and produce the crossfire signal SSER of output, then crossfire signal SSER can utilize difference transceiver 1332 to be converted into differential data signals DDAT.For instance, in one embodiment, scrambler 1623 can include bit and fill (bit stuffing) and reverse non-return-to-zero (NRZI) codimg logic circuit.
Figure 16 B illustrates the specific embodiment synoptic diagram of the difference serial interface engine 1371 among Figure 15 B.Difference serial interface engine 1371 includes and writes first in first out (first in first out; FIFO) memory bank 1641, parallel serial convertor 1642, scrambler 1643, Cyclical Redundancy Check (the cyclic redundancy check of changeing; CRC) generator 1644, command initialization circuit 1645, synchronous generator 1646, start frame (startof frame; SOF)/package ending (end of packet; EOP) generator 1647, read first in first out memory bank 1651, transformation from serial to parallel converter 1652, demoder 1653, Cyclical Redundancy Check detector 1654, command detector 1655, detector 1656, package ending detector 1657 and phase-locked loop (phase locked loop synchronously; PLL) 1659.Identical with the difference serial interface engine 1331 among Figure 16 A, the difference serial interface engine 1371 that is illustrated among Figure 16 B can be come activation serial differential data transmission by the data subpackage, thereby can eliminate the clock data transmission requirements.
Be stored in the control signal CTRL that writes first in first out memory bank 1641 and come from protocol controller 1360 with and/or data-signal DAT can begin to carry out communication with flash memory cards, simultaneously, Cyclical Redundancy Check generator 1644 and synchronous generator 1646 can produce Cyclical Redundancy Check message block and synchronizing information group respectively at output signal, please note, if different Cyclical Redundancy Check forms uses at order and data packet, command initialization circuit 1645 will provide suitably to indicate and give Cyclical Redundancy Check generator 1644.
The content that writes first in first out memory bank 1641 then can be sent to the parallel serial convertor 1642 that changes and give serialization, and initial at each frame, and start frame/package ending generator 1647 will release frame start information group; And in the end of each package, start frame/package ending generator 1647 will be issued package ending message block.Wherein please note, the clock signal of system SCLK that utilizes phase-locked loop 1659 to be produced will be used to provide the frame clock that gives start frame/package ending generator 1647, specifically, clock signal of system SCLK will be used for providing frame start information group at interval in appropriate time by start frame/package ending generator 1647.Utilize this mode, write first in first out memory bank 1641, Cyclical Redundancy Check generator 1644, command initialization circuit 1645, synchronous generator 1646 and start frame/package ending generator 1647 and can be used as subpackage (packetizing) logical circuit of difference serial interface engine 1371.
Parallel commentaries on classics serial convertor 1642 then will be imported parallel data and be converted to serial data crossfire (bitstream), continue and encode by scrambler 1643, scrambler 1643 is also used predefined coding protocol (for example filling coding or oppositely non-return-to-zero coding for bit) to coming from the parallel bit crossfire that changes serial convertor 1642, and produce the crossfire signal SSER of output, then crossfire signal SSER can utilize difference transceiver 1372 to be converted into differential data signals DDAT.
The serial signal SSER (being produced according to input differential signal DDAT by difference transceiver 1372) of input decodes decoded device 1653 according to predetermined coding protocol (for example filling coding or oppositely non-return-to-zero coding for bit), in one embodiment, demoder 1653 also can include clock and replys logical circuit and elasticity store buffer and come that (such as signal jitter (jitter)) compensated at local clock's problem.
The decoded signal that utilizes demoder 1653 to be produced can utilize transformation from serial to parallel converter 1652 to give parallelization (parallelized), and is sent to and reads first in first out memory bank 1651, Cyclical Redundancy Check detector 1654, command detector 1655, detector 1656 and package ending detector 1657 synchronously.Detector 1656 is distinguished the synchronization information group at input signal synchronously, when detecting the synchronization information group, can utilize provides start signal START to reading first in first out memory bank 1651, Cyclical Redundancy Check detector 1654, command detector 1655 and package ending detector 1657, the reception of beginning package.
Respond start signal START, read the content (from the signal of transformation from serial to parallel converter 1652) that first in first out memory bank 1651 begins to store input signal, Cyclical Redundancy Check detector 1654 can carry out the action of Cyclical Redundancy Check at input data (selectively based on the signal from command detector 1655) simultaneously.Note that if the testing result of Cyclical Redundancy Check for failure, can have various error handler to carry out, comprise terminator, require again transmission command/data etc.
At last, when package ending detector 1657 detects package ending message block, package ending detector 1657 can utilize issue termination signal STOP to reading first in first out memory bank 1651, Cyclical Redundancy Check detector 1654, command detector 1655 and package ending detector 1657, finish the reception of package, then, protocol controller 1360 reads packet data (can be status signal ST or data-signal DAT) by reading first in first out memory bank 1651, just begins the reception of next package then.Utilize this mode, that reads that first in first out memory bank 1651, Cyclical Redundancy Check detector 1654, command detector 1655 and package ending detector 1657 can be used as difference serial interface engine 1371 separates subpackage (de-packetizing) logical circuit.
The above description of this invention is illustrative, and nonrestrictive, and those skilled in the art is understood, and can carry out many modifications, variation or equivalence to it within spirit that claim limits and scope, but they will fall within the scope of protection of the present invention all.
Claims (3)
1. a flash memory cards is characterized in that, comprises:
One pin configuration is predetermined based on the pin count of this flash memory cards, and this pin configuration packet contains a group of pins, and in order to connect two pairs of differential serial data lines, each carries a positive signal and a negative signal to the differential serial data line;
One flash volume array;
One protocol controller is in order to this flash volume array of access; And
One differential data path, have an input differential signal is converted to the function that a status signal and an input data signal give this protocol controller, and the function that will be converted to an output differential signal from a control signal and an outputting data signals of this protocol controller, wherein this differential data path includes:
One difference transceiver is in order to change this input differential signal be an input multi-usage serial signal and an output multi-usage serial signal is converted to this output differential signal; And
One difference serial interface engine, be converted to this output multi-usage serial signal at least one status signal with this input data signal and with at least one control signal and this outputting data signals in order to change this input multi-usage serial signal, wherein this difference serial interface engine includes:
One demoder, it is according to a predetermined coding protocol this input multi-usage serial signal of decoding, and is converted to an input serial Bit String and flows;
One first converter was changed to one first sets of signals in order to should import the circulation of serial Bit String;
One synchronous detector is in order to carry out identification one synchronous message block and when detecting this synchronizing information group, to utilize generation one initial signal to begin the reception of package at this first sets of signals;
One writes the first in first out memory bank, responding this start signal, and exports this at least one status signal and this input data signal in order to the content that stores this first sets of signals;
One Cyclical Redundancy Check detector is in order to carry out a Cyclical Redundancy Check to respond this start signal at this first sets of signals;
One command detector, whether this first sets of signals is a command signal or a data-signal in order to decision, responding this start signal, and provides this decision to give this Cyclical Redundancy Check detector;
One start frame detector responding this start signal, and when detecting, triggers the generation of a local clock in order to a plurality of start frame message block of detecting this first sets of signals;
One package ending detector responding this start signal, and when detecting, is issued the reception that a termination signal finishes package in order to the package ending message block of detecting this first sets of signals;
One reads the first in first out memory bank, in order to the content that stores this at least one control signal and this outputting data signals by the output of this protocol controller and export a secondary signal group;
One synchronous generator is in order to produce a synchronous message block at this secondary signal group;
One Cyclical Redundancy Check generator is in order to produce a Cyclical Redundancy Check message block at this secondary signal group;
One command initialization circuit is a command signal or a data-signal in order to determine this secondary signal group, and provides this decision to give this Cyclical Redundancy Check generator;
One package ending generator is in order to produce package ending message block at this secondary signal group;
One second converter is converted to an output serial data crossfire in order to this secondary signal group, this Cyclical Redundancy Check message block, this synchronizing information group and this package ending message block with parallel receive; And
One scrambler applies this predetermined coding protocol to this output serial data crossfire, and is converted to this output multi-usage serial signal;
Wherein this flash memory cards includes one of them of a multimedia storage card, a secure digital storage card, a tight flash memory cards and a memory stick storage card.
2. an electronic installation is characterized in that, comprises:
One host stores card adapter, in order to connect a flash memory cards, this host stores card adapter includes:
One pin configuration, it is predetermined based on the pin count of this flash memory cards, and this pin configuration packet contains a group of pins, and in order to connect two pairs of differential serial data lines, each carries a positive signal and a negative signal to the differential serial data line;
One protocol controller is in order to provide the function of this flash memory cards communications protocol;
One uses breakout box, and in order to controlling this protocol controller, and this application breakout box provides the bridge between specific device communication and the particular memory card communication; And
One differential data path, have an input differential signal is converted to the function that a status signal and an input data signal give this protocol controller, and the function that will be converted to an output differential signal from a control signal and an outputting data signals of this protocol controller, wherein this differential data path includes:
One difference transceiver is in order to change this input differential signal be an input multi-usage serial signal and an output multi-usage serial signal is converted to this output differential signal; And
One difference serial interface engine, be converted to this output multi-usage serial signal at least one status signal with this input data signal and with at least one control signal and this outputting data signals in order to change this input multi-usage serial signal, wherein this difference serial interface engine includes:
One demoder, it is according to a predetermined coding protocol this input multi-usage serial signal of decoding, and is converted to an input serial Bit String and flows;
One first converter was changed to one first sets of signals in order to should import the circulation of serial Bit String;
One synchronous detector is in order to carry out identification one synchronous message block and when detecting this synchronizing information group, to utilize generation one initial signal to begin the reception of package at this first sets of signals;
One reads the first in first out memory bank, responding this start signal, and exports this at least one status signal and this input data signal in order to the content that stores this first sets of signals;
One Cyclical Redundancy Check detector is in order to carry out a Cyclical Redundancy Check to respond this start signal at this first sets of signals;
One command detector, whether this first sets of signals is a command signal or a data-signal in order to decision, responding this start signal, and provides this decision to give this Cyclical Redundancy Check detector;
One package ending detector responding this start signal, and when detecting, is issued the reception that a termination signal finishes package in order to the package ending message block of detecting this first sets of signals;
One writes the first in first out memory bank, in order to the content that stores this at least one control signal and this outputting data signals by the output of this protocol controller and export a secondary signal group;
One synchronous generator is in order to produce a synchronous message block at this secondary signal group;
One Cyclical Redundancy Check generator is in order to produce a Cyclical Redundancy Check message block at this secondary signal group;
One command initialization circuit, whether this secondary signal group is a command signal or a data-signal in order to decision, and provides this decision to give this Cyclical Redundancy Check generator;
One start frame and package ending generator are in order to produce an initial frame information group and package ending message block at this secondary signal group;
One second converter is converted to an output serial data crossfire in order to this secondary signal group, this Cyclical Redundancy Check message block, this synchronizing information group, this start frame message block and this package ending message block with parallel receive; And
One scrambler applies this predetermined coding protocol to this output serial data crossfire, and is converted to this output multi-usage serial signal;
Wherein this flash memory cards includes one of them of a multimedia storage card, a secure digital storage card, a tight flash memory cards and a memory stick storage card.
3. in a flash memory cards, carry out a method of operating for one kind, it is characterized in that this operate by the requirement of unique host institute, and this main frame disposes by the indivedual pins that match with this flash memory cards and interconnects,
Wherein this manipulates one group of pin that is used for connecting two pairs of differential serial data lines, and each carries a positive signal and a negative signal to the differential serial data line, and this method includes the following step:
To be sent to this flash memory cards from a plurality of orders of this main frame;
This flash memory cards of identification;
One agreement of this flash memory cards of initialization;
Control this initialization and the specific device communication is provided and the particular memory card communication between bridge;
Conversion is the multi-functional serial signal of an input from an input differential signal of this main frame, and changes this and import multi-functional serial signal and offer a flash body in this flash memory cards at least one status signal and an input data signal; And
Conversion is the multi-functional serial signal of an output from an at least one control signal of the flash body in this flash memory cards and an outputting data signals, and changing this, to export multi-functional serial signal be that an output differential signal offers this main frame.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101441662A CN102214315A (en) | 2010-04-12 | 2010-04-12 | Flash memory card used for differential data transmission |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101441662A CN102214315A (en) | 2010-04-12 | 2010-04-12 | Flash memory card used for differential data transmission |
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| CN102214315A true CN102214315A (en) | 2011-10-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010101441662A Pending CN102214315A (en) | 2010-04-12 | 2010-04-12 | Flash memory card used for differential data transmission |
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| CN103034603A (en) * | 2012-12-07 | 2013-04-10 | 天津瑞发科半导体技术有限公司 | Multi-channel flash memory card control device and control method thereof |
| CN104798010A (en) * | 2012-10-02 | 2015-07-22 | 英特尔公司 | Serial storage protocol compatible frame conversion, at least in part |
| CN106888027A (en) * | 2015-12-15 | 2017-06-23 | 台湾积体电路制造股份有限公司 | For the transmitter of radio frequency cross tie part RFI |
| CN107886149A (en) * | 2016-09-29 | 2018-04-06 | 三星电子株式会社 | Memory card and the storage system for including it |
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| CN104798010A (en) * | 2012-10-02 | 2015-07-22 | 英特尔公司 | Serial storage protocol compatible frame conversion, at least in part |
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| CN106888027A (en) * | 2015-12-15 | 2017-06-23 | 台湾积体电路制造股份有限公司 | For the transmitter of radio frequency cross tie part RFI |
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Application publication date: 20111012 |