CN102201429A - Resistive Random Access Memory (RRAM) unit - Google Patents
Resistive Random Access Memory (RRAM) unit Download PDFInfo
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- CN102201429A CN102201429A CN2010101317932A CN201010131793A CN102201429A CN 102201429 A CN102201429 A CN 102201429A CN 2010101317932 A CN2010101317932 A CN 2010101317932A CN 201010131793 A CN201010131793 A CN 201010131793A CN 102201429 A CN102201429 A CN 102201429A
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Abstract
The invention provides a Resistive Random Access Memory (RRAM) unit, comprising a substrate, a buried oxidization layer and an epitaxial layer sequentially formed on the substrate, a grid dielectric layer and a grid sequentially formed on the epitaxial layer, a source area and a drain area formed in the epitaxial layer on two sides of the grid, wherein the grid dielectric layer is made of hafnium oxide. According to the RRAM unit provided by the invention, a logic transistor with the high-k grid electric medium and the metal grid can be easily converted to the non-volatile RRAM, thus the logic of the system-level chip and the memory design can be easily produced together in a seamless connection manner to become the breakthrough. In the invention, how to convert the logic transistor to the RRAM is described, preferably, the hafnium oxide-based high K electric medium is used for opening and closing, and organizing operation of the array and the memory.
Description
Technical field
The present invention relates to semiconductor memory, specifically, relate to resistive random access memory (RRAM, Resistive Random Access memory) cellular construction and array and storage operation.
Background technology
21 century, the high speed development of computer technology, the Internet and novel popular electronic product presents the high speed ascendant trend to the demand of the stores processor product of electronic information, and presses at storage material and technical elements and make a breakthrough.The resistive random access memory (RRAM) that receives much concern as nonvolatile memory of future generation will become core memory of future generation.RRAM has such advantage: as working storage, its speed can be equal to SRAM; As access memory, can realize the cost that contends with NAND type flash memory.
2000, the scientist of houston, u.s.a university has reported and has found that in huge magnetic resistance sull device electric pulse triggers reversible resistance transition effect (EPIR effect), promptly add under the effect of nanosecond step voltage pulse outside, the resistance of device is reversible transition between low resistance state (" 0 ") and high-impedance state (" 1 "), rate of change can reach more than 1000 times, and resulting resistance is under can keeping after the external electric field removal.In the same year, IBM research and development department has also found similar effect in the perofskite type oxide thin-film device.Based on this effect, scientific circles have proposed a kind of novel nonvolatile memory notion, promptly above-mentioned resistive random access memory (RRAM).
The working mechanism of RRAM, promptly the phenomenon that RRAM utilized is that material resistance can reversible resistance great change take place because of the potential pulse that applies, and is also referred to as the CER phenomenon.The CER phenomenon is to be called common phenomena in " strong correlation (Strongly Correlated) " electrical type material.Strong correlation electrical type material is the general name of a class material, and this class material has the electronics characteristics of mutual strong effect on a large scale, and the electrical conductivity characteristic is different with common metal and semiconductor.Metal oxide such as NiO and PrCaMnO is an example wherein.By inference, resistance variations takes place and produces in the interface between CER phenomenon strong correlation electronic material and metal electrode, and the three stacked elements that press from both sides PrCaMnO on metal electrode are applied voltage, has detected resistance variations at this moment.The result shows, what resistance variations relied on is the voltage application direction, and by to the interfacial state iunjected charge, the height of the formed Schottky barrier in interface between strong correlation electronic material and metal electrode just can change.
RRAM is the generally good nonvolatile storage technologies of future generation of industry.The main advantage of RRAM shows: the one, and preparation is simple.Memory cell is the metal-oxide-metal sandwich structure, can be by conventional thin-film technique preparation such as sputter, vapour deposition; The 2nd, erasable speed is fast.Erasable speed was generally less than for 100 nanoseconds, far above the Flash memory by the pulse duration decision that triggers electric resistance changing; The 3rd, the storage density height.Studies show that the zone that resistance changes is very little, several approximately nanometers, therefore memory cell can be very little, in addition, in RRAM, also there is multilevel electric resistance changing phenomenon, utilize these resistance states can store different information, under the condition that does not change the memory cell volume, can realize the storage of more information; The 4th, the semiconductor technology compatibility is good, and RRAM can utilize the conventional semiconductor technology to produce, thereby reduces development cost greatly.
In the research of RRAM, the attentiveness research that has concentrates on that material component is simple, on manufacturing process and the cmos compatible binary metal oxide, studied the electric resistance changing characteristic of doping binary metal oxide innovatively.Experimental result is found to mix in binary metal oxide and can be improved the rate of finished products of device effectively, and this result makes the binary metal oxide material that mixes have the application potential of very big RRAM.Recent research is also based on the Cu/ZrO that has furtherd investigate
2: the Cu/Pt material structure.Up to the present, the bistable resistive switch is found and is present in perovskite oxide (as SrTiO
3,,SrZrO
3(SZO), PCMO, PZTO ... etc.), transition metal oxide (as Ni-O, Cu-O, W-O, TiON, Zr-O, Fe-O, Co-O ... etc.), copper doping SiO2 or W-O, solid electrolyte, even polymer.Although have multiple different material to show resistance switch and can be used for RRAM, have only with the standard CMOS backend process (as WO
x, Cu
xO etc.) those compatible fully materials are just by commercialization.
Fig. 1 shows the electrical characteristics figure of resistance switch material.The electrical characteristics of resistance switch material are normally based on the I-V scanning curve of MIM resistance.At first, the direct current or the pulse mode of "+set " action beginning I-V scanning from 0V to+voltage (measuring I), increase suddenly at a point up to electric current I from high impedance status (HRS), become low resistance state (LRS), shown in curve o-a-a or curve o-a-a ' (slow switch).+ V
SetWith+I
SetThe voltage and current of being ordered by a defines.The 1st group of operation is called as " formation ", have typical high amplitude+V
SetWith+I
SetSecondly, "+reset " startup+voltage scanning, descend suddenly (b point) up to electric current from LRS, shown in curve o-b-b or o-b-b ' (slow switch).+ V
ResetWith+I
ResetThe voltage and current definition of ordering then by b.Correspondingly, " set " and " resetting " operation can similarly define, and does not repeat them here.This resistor can have the favourable polarity that is used for switch, for example: "+set /+reset " or " set/-reset " (being called single-pole switch), perhaps "+set/-reset " or " set /+reset " (being called double-pole switch).In order to realize normal operation, each resistance should transistorized current range (for example～1 μ A to 1mA) and voltage (＜3.3v) carry out set/reset and read operation in the scope.Therefore, the target LRS of resistance and HRS should distinguish well-designed in a reasonable range, based on the circuit function and the memory density of sense amplifier.Too small or the HRS of LRS crosses senior general and causes carrying out reading with set/reset and operate, just simply owing to select transistor can't provide enough big power (electric current and voltage) to trigger set/reset to operate to resistor, to such an extent as to or the too little amplifier that can't be read out of electric current read.
When 90nm and 65nm nanometer nodes are utilized strain engineering to proceed the transistorized size of CMOS to dwindle, begun to utilize high-k gate dielectric and metal gates to arrive the technological level of 32 nanometer nodes.High-k gate dielectric can the suppressor grid leakage current and is kept the thickness of the gate oxide that approaches for transistor.
Therefore, need in the prior art a kind of can with RRAM device of existing C MOS process compatible and preparation method thereof.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The invention provides a kind of resistor random access memory cell, comprising: substrate; The buried oxide layer and the epitaxial loayer that on substrate, form successively; The gate dielectric and the grid that on described epitaxial loayer, form successively; The source region and the drain region that in the described epitaxial loayer of described grid both sides, form; The material of wherein said gate dielectric is a hafnium oxide.
According to an aspect of the present invention, resistor random access memory cell also comprises, respectively the lightly doped drain that forms near a side of grid in described source region and drain region.
According to another aspect of the present invention, described epitaxial loayer is p type or n type.
According to another aspect of the present invention, described source region or drain region are n+ type or p+ type.
According to another aspect of the present invention, the thickness of described gate dielectric is
According to another aspect of the present invention, the bias voltage that is applied on the described grid when forming described memory cell is an outer power voltage.
According to another aspect of the present invention, described resistor random access memory cell " 0 " and one state are represented by the low resistance state and the high resistance state of described gate dielectric respectively.
According to another aspect of the present invention, described memory cell is in write operation, and the bias voltage of described grid is+0.6V that source/drain voltage all is-0.6V.
According to another aspect of the present invention, described memory cell is in read operation, and the bias voltage of described grid is+0.5V that drain voltage is+1V that source voltage is 0V.
The present invention also provides a kind of resistive random access memory array, the unit of described array is formed by arbitrary resistor random access memory cell of the above-mentioned aspect according to the present invention, the drain electrode of described resistor random access memory cell and source electrode are connected respectively to the not corresponding lines of memory array, and grid is as word line.
According to process of the present invention, the logic transistor with high k and metal gates can be converted at an easy rate as non-volatile RRAM to be carried out.This makes and the logic and memory design of system level chip is manufactured in together with being easy to seamless link, becomes breakthrough.The invention describes how logic transistor is converted into the RRAM unit, preferably use hafnium oxide base high-k dielectrics to be beneficial to switch and to be organized as array and storage operation.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 represents the electrical characteristics figure of resistance switch material;
Fig. 2 a is the cutaway view according to the RRAM unit of the embodiment of the invention;
Fig. 2 b is the equivalent circuit diagram according to the RRAM unit of the embodiment of the invention;
Fig. 3 is the RRAM cellular construction figure with dual structure of nMOSFET and parasitic bipolar transistor;
Fig. 4 is the biasing figure that forms the hafnium oxide based dielectric in the nMOSFET device of making according to the present invention;
Fig. 5 represents to operate according to writing with set/reset of RRAM of the present invention unit;
Fig. 6 represents the read operation according to RRAM of the present invention unit.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that new RRAM cellular construction of the present invention is described and writes accordingly/the read operation method.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
According to the present invention, a kind of new RRAM cellular construction, array and method of operation are provided.Form thread resistance (resistive filament) by the high K medium between grid and the raceway groove, new RRAM unit can be simply changes from the logic transistor of (usually 32 nanometer nodes technologies) and obtains.Like this, the gate current that enters in the body layer can trigger and the conducting parasitic bipolar transistor.In the logic transistor of 32 nanometer nodes, the long only about 30nm of raceway groove, the parasitic bipolar transistor enlargement ratio is higher than about 50.The collector current of parasitic bipolar transistor is the base current that passes through resistance wire (or grid current) that amplifies, and can be reflected in the resistance amplitude of high value or low resistance state, forms the switching effect of memory thus.Can be set to array format according to this RRAM of the present invention unit, make bit line, make word line with grid with drain electrode and source electrode.The present invention can make RRAM integrated with the logic CMOS technology that is used for system level chip easily.
A. from new RRAM unit that the MOSFET of SOI and array structure forms:
Be manufactured on the MOSFET that has high-k dielectric and metal gates (HKMG) on the SOI and can change the resistive switch memory cell into, to be used for non-volatile memory function.In the present invention, adopt the material of hafnium (Hf) oxide-base as the gate dielectric in the HKMG transistor.The high k material of hafnium oxide base has trap and can carry out " resistance switch " by current stress after formation.As shown in Figure 7, adopted the transistorized form of nMOSFET, had the resistor path that forms in the medium between metal gates and epi channels (or base stage) zone according to RRAM of the present invention unit.Therefore, the grid current that flows in the epitaxial-base can trigger parasitic npn type bipolar transistor (mechanism that is used for read operation).The MOS operation still exists, because the resistor path from metal gate to the p epitaxial loayer is the very little local conductive resistance silk the gate dielectric.
Fig. 2 a and 2b have described by being manufactured on the MOSFET that has high-k dielectric and metal gates on the SOI and have changed basic unit of storage as the resistive switch storage array into.This RRAM unit can be organized into array format, and transistor drain and source electrode are connected to not corresponding lines (BL), and with grid as word line (WL), operate with execute store.Fig. 2 a is the cutaway view of RRAM of the present invention unit, and Fig. 2 b is the equivalent circuit diagram of this RRAM unit.
Shown in the cutaway view of Fig. 2 a, buried oxide layer (BOX) 202 and p type epitaxial loayer 203 that the MOSFET 200 of formation RRAM of the present invention unit comprises substrate 201, forms successively on substrate.Can form a plurality of shallow channel isolation areas (STI) 203 layers of p type epitaxial loayers, be used to isolate each MOSFET.Form gate dielectric 204 and grid 205 on p type epitaxial loayer 203 successively, this dielectric layer 204 is the material layers with high-k (high k), preferably uses hafnium oxide sill (HfO in the present invention
2).The technology of injecting by ion forms two n+ doped regions 206 as the MOSFET source-drain area respectively then, and the electrode wires (not shown) that will be connected with described metal gate, source, drain region respectively draws, respectively as the word line and the bit line of memory.
Preferably, can also form two n type lightly doped drains in the p type epitaxial loayer between source-drain area
(LDD) district 207 is adjacent with described source or drain region respectively.
Fig. 2 b illustrates the equivalent circuit diagram of this RRAM unit, and from Fig. 2 b as seen, gate dielectric 204 has formed the resistance unit with switching function.The grid of MOSFET is connected to the word line (WL) of memory cell array, and source and drain electrode are connected to the bit line (BL) of memory cell array.
Fig. 3 is the RRAM cellular construction figure with dual structure of nMOSFET and parasitic bipolar transistor.These RRAM unit as shown in Figure 3 also can be organized into an array, have to be connected to the not drain electrode and the source electrode of corresponding lines (BL1 and BL2), with grid as word line (WL), to carry out suitable storage operation.What one of ordinary skill in the art will appreciate that is, corresponding pMOSFET also can change into P raceway groove RRAM unit according to said method of the present invention, its array and class of operation are similar to N raceway groove RRAM unit, except the polarity of suitable counter-rotating biasing, in order to simplify, do not carry out repeat specification hereinafter.
MOSFET in the RRAM of the present invention unit has and the essentially identical structure of logic transistor, except having the resistor path that is formed by gate dielectric.RRAM of the present invention unit can be organized as array, makes bit line with drain electrode and source electrode, and makes word line with grid.This array can comprise n raceway groove and p trench cells or its combination.
B. at the technological process of RRAM optimizing application hafnium oxide base gate medium:
The hafnium oxide based dielectric that is used for logic transistor should make the body material of logic transistor minimized with trap (most possible relevant with the oxygen vacancy) at the interface, promptly realizes less V
tDrift, less g
mDeterioration and littler mismatch etc.But, to use for RRAM, the high density traps of the high k material of hafnium oxide base is relevant with the oxygen vacancy, to provide reliable resistance switch between resistance states (representing the storage of numerical data).Electric " formation " technology can activate the existing trap in these hafnium oxides, to carry out resistance switch, if but could produce more trap in the technology, then could cause lower operation (set/reset) voltage and stored digital is realized better maintenance and circulation.Therefore make in the technical process of RRAM in the present invention, for the consideration of compromising of the body material of logic transistor and trap at the interface.By after high k gate dielectric deposition, increase an extra mask step, so that in gate dielectric, inject the material of absorption impurity oxygen atom, as Si, Ti, Hf etc., in the hafnium oxide dielectric layer, produce more oxygen vacancy thus, in the hafnium oxide in RRAM zone, optionally to produce more trap.Therefore,, after the gate dielectric deposition, can adjust the trap density of hafnium oxide, realize better storage effect by technologic improvement.
The formation operation of c.RRAM:
Fig. 4 has illustrated the biasing of " formation " hafnium oxide based dielectric in the nMOSFET device of making according to the present invention.In " formation " process, raceway groove is inverted, and therefore has the surface field (perpendicular to interface) stronger than n+S/D LDD zone on the extension channel region, and this is because the work function of n type metal gate is about 4eV.Therefore, the conductive resistance silk is most likely in the high k dielectric layer on the epi channels zone and forms.The thickness that minimum formation voltage and formation time depend on hafnium oxide and the trap quantity of existence, for example, for forming technology, in typical 32nm node technology, common 40 dusts (
) thick hafnium oxide need about 2V formation voltage and the formation time of about 1 microsecond to 1 millisecond.For convenience's sake, in Fig. 4, the formation voltage that is used for the MOS transistor of 32nm is that Vcc (is an external voltage source, normally 1.2V, 1.8V or 2.5V etc.), these selected bit line and word lines all are ground connection, make to disturb to occur over just those and do not have selecteed unit (on the identical ranks of menu unit).After sending " formation " pulse, memory cell under reading mode whether to examine resistance at the state (being defined as " 0 ") of low resistance.If maximum formation voltage need then will add the electric charge booster circuit greater than Vcc.
In the forming process of Fig. 4, bias voltage is: grid voltage V
G≈+Vcc/2, source/drain voltage V
D=V
S≈-Vcc/2.Forming process is used a plurality of pulses.
D.RRAM write (set/reset) operates:
Among Fig. 5 for the nMOSFET device of making according to the present invention be provided with/biasing of reset operation is illustrated with the situation of individual unit and array.All are unchecked reads line and bit line is unsettled, the word line ground connection that all are selected.The poorest set/reset is disturbed on those not selected resistance that occur on the same selected BL, and those non-selected resistance only experience the very little shutoff leakage current by the n+/p+ tunnel junction.
After successfully forming, memory cell can set (for low resistance R) or reset (high value R), represents status data " 0 " or " 1 " respectively.As shown in Figure 5, except lower voltage bias, it is positive bias on grid that the operation of+set/reset is reduced to hypothesis, and similar with " formation " process.The multiple-pulse scheme is normally carried out by reading-write (checking) circulation, correctly is stored in the unit up to data.Also with " formation " process similarly be, in write operation, those unselected bit lines and word line all are grounded, and the unit experienced the poorest interference biasing also is when forming situation.
When using the MOSFET of this RRAM unit, not selected BL1, BL2 and WL line all can be grounded.Being in the size that the not selected unit on the identical ranks will be applied between grid and the channel region with the unit of choosing is the lowest interference voltage of Vcc/2, and therefore the interference voltage that is subjected to is very little, can not cause and crosstalk.
In write operation (+set or+reset operation), grid (word line) bias voltage is V
GThe 0.6v of=～+(＞threshold voltage V
Th), source/drain voltage V
D=V
S≈-0.6V.Can adopt a plurality of pulses.Be noted that in set or reset operation process, raceway groove is inverted, make that the surface field on the channel region top is stronger than S/D LDD district; Therefore, the resistor path on the top, type base region of epitaxial loayer is limited in the high-k dielectric zone on the channel region top.In this embodiment, the typical write time is less than 100 microseconds.
After each pulse that is used for write operation, the data that write need be read, to determine whether needing more pulse to proceed the write operation of these data.This is the process of checking.With form class of operation seemingly, unchecked BL1, BL2 and WL are grounded, and have strengthened the antijamming capability of MOSFET.
E. read operation:
Parasitic npn bipolar transistor is adopted in the read operation of RRAM, to amplify the gate current that flows into the p epitaxial-base by resistor.The grid voltage that applies is lower than the threshold voltage of MOS transistor, to suppress channel inversion.Therefore, (because low R state) bigger grid current has caused bigger amplification collector current I
CSimilarly, high R is by little collector current I
CDetect.Bit line that these are selected and word line be ground connection all, so that bipolar and MOS electric current all is suppressed in all selected unit.
Fig. 6 has represented the read operation process of RRAM.Collector current I
CAmplitude relevant with R, be used to determine " 1 " or " 0 ".These not selected bit lines and word line be ground connection all.
In read operation, bias voltage is V
GThe 0.5V (＜V of=～+
Th), VD=+1V; V
S=0V.If collector current I
CLittle, R=" 1 " or high value state, expression store status " 1 "; If collector current I
CBig, R=" 0 " or low resistance state, expression store status " 0 ".In this embodiment, typical time for reading is less than 100 microseconds.
It should be noted that at this moment MOSFET does not have conducting, have only parasitic npn bipolar transistor conducting, its collector current I
CBy the base current modulation, base current is determined by the resistance of the resistance R of gate bias voltage and hafnium oxide based dielectric.
Unchecked BL1, BL2 and WL are grounded.Unchecked unit had not both had the electric current of bipolar transistor, did not have the electric current of MOS transistor yet.Strengthened the antijamming capability of MOSFET like this.
F. beneficial effect of the present invention:
Under 32 nanometers even littler technology node, according to process of the present invention, the logic transistor with high k and metal gates can be converted at an easy rate as non-volatile RRAM to be carried out.This makes and the logic and memory design of system level chip is manufactured in together with being easy to seamless link, becomes breakthrough.The invention describes how logic transistor is converted into the RRAM unit, preferably use hafnium oxide base high-k dielectrics to be beneficial to switch and to be organized as array and storage operation.
Memory according to aforesaid embodiment manufacturing can be used for multiple consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (13)
1. resistor random access memory cell comprises:
Substrate;
The buried oxide layer and the epitaxial loayer that on substrate, form successively;
The gate dielectric and the grid that on described epitaxial loayer, form successively;
The source region and the drain region that in the described epitaxial loayer of described grid both sides, form;
The material of wherein said gate dielectric is a hafnium oxide.
2. resistor random access memory cell according to claim 1 also comprises, respectively the lightly doped drain that forms near a side of grid in described source region and drain region.
3. resistor random access memory cell according to claim 1, wherein said epitaxial loayer are p type or n type.
4. resistor random access memory cell according to claim 1, wherein said source region or drain region are n+ type or p+ type.
5. resistor random access memory cell according to claim 1, the thickness of wherein said gate dielectric is
6. resistor random access memory cell according to claim 1, wherein the bias voltage that is applied on the described grid when forming described memory cell is an outer power voltage.
7. resistor random access memory cell according to claim 1, wherein said resistor random access memory cell " 0 " and one state are represented by the low resistance state and the high resistance state of described gate dielectric respectively.
8. resistor random access memory cell according to claim 1, wherein said memory cell are in write operation, and the bias voltage of described grid is+0.6V that source/drain voltage all is-0.6V.
9. resistor random access memory cell according to claim 1, wherein said memory cell are in read operation, and the bias voltage of described grid is+0.5V that drain voltage is+1V that source voltage is 0V.
10. resistor random access memory cell according to claim 1 wherein after forming gate dielectric, injects the material that absorbs oxygen atom in gate dielectric.
11. resistor random access memory cell according to claim 10, the material of wherein said absorption oxygen atom is selected from one or more among Si, Ti and the Hf.
12. resistive random access memory array, the unit that it is characterized in that described array is formed by the arbitrary resistor random access memory cell according to claim 1-11, the drain electrode of described resistor random access memory cell and source electrode are connected respectively to the not corresponding lines of memory array, and grid is as word line.
13. an electronic equipment that comprises resistor random access memory cell as claimed in claim 1, wherein said electronic equipment personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| WO2022134870A1 (en) * | 2020-12-21 | 2022-06-30 | International Business Machines Corporation | Symmetric read operation resistive random-access memory cell with bipolar junction selector |
| US11411049B2 (en) | 2020-12-21 | 2022-08-09 | International Business Machines Corporation | Symmetric read operation resistive random-access memory cell with bipolar junction selector |
| GB2618233A (en) * | 2020-12-21 | 2023-11-01 | Ibm | Symmetric read operation resistive random-access memory cell with bipolar junction selector |
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