CN102201194A - Shift register circuit - Google Patents
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- CN102201194A CN102201194A CN2011101783062A CN201110178306A CN102201194A CN 102201194 A CN102201194 A CN 102201194A CN 2011101783062 A CN2011101783062 A CN 2011101783062A CN 201110178306 A CN201110178306 A CN 201110178306A CN 102201194 A CN102201194 A CN 102201194A
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Abstract
A shift register circuit includes a plurality of stages of shift registers, wherein each stage of the shift register has a first pull-down unit for pulling down a scan signal according to a driving control voltage and a first clock, an input unit for outputting the driving control voltage according to an input signal and a second clock opposite to the first clock, a first control unit for providing a first control signal according to the driving control voltage, a first pull-up unit for pulling up the driving control voltage and the scan signal according to the first control signal, a second pull-up unit for pulling up a light-emitting signal according to the scan signal, a second control unit for providing a second control signal according to the scan signal and the second clock, and a second pull-down unit for pulling down the light-emitting signal according to the second control signal.
Description
Technical field
The present invention relates to a kind of shift-register circuit, particularly relate to a kind of shift-register circuit that is used to provide a plurality of scanning signals and a plurality of luminous signals.
Background technology
Flat display apparatus (Flat Panel Display) has that external form is frivolous, power saving and advantage such as radiationless, so be widely used on the electronic products such as computer screen, mobile phone, PDA(Personal Digital Assistant), flat-surface television.In various flat display apparatus, active matrix organic light-emitting display device (Active Matrix Organic Light Emitting Display; AMOLED) but have also that autoluminescence, high brightness, high-luminous-efficiency, high contrast, reaction velocity are fast, a further advantage such as wide viewing angle and serviceability temperature scope are big, therefore highly competititve on the market of flat display apparatus.Generally speaking, the active matrix organic light-emitting display device includes a plurality of pixel cells, shift-register circuit and data driver.Data driver is used for producing a plurality of data signals to a plurality of pixel cells.Shift-register circuit is used for producing a plurality of pixel cells of a plurality of scanning signal feed-in to control the running that writes of a plurality of data signals.In addition, shift-register circuit is used for producing a plurality of luminous signals in addition, and the luminous activation control of a plurality of pixel cells is provided according to this, and the anti-phase transistor critical voltage compensation that operates to carry out circuit in correspondence scanning signal of each luminous signal.Prior art is with CMOS (Complementary Metal Oxide Semiconductor) (Complementary Metal Oxide Semiconductor; CMOS) the designed phase inverter of circuit provides anti-phase each other scanning signal and luminous signal, that is the existing shift-register circuit of this kind comprises P transistor npn npn and N transistor npn npn, so need complicated semiconductor fabrication process.
Summary of the invention
According to embodiments of the invention, it discloses a kind of shift-register circuit that is used to provide a plurality of scanning signals and a plurality of luminous signals.This kind shift-register circuit comprises multi-stage shift register, and each grade shift register comprises the first drop-down unit, input block, first control module, first pull-up unit, second pull-up unit, the second drop-down unit and second control module.The first drop-down unit is used for according to drive control voltage and first clock with drop-down corresponding scanning signal.The input block that is electrically connected on the first drop-down unit is used for according to input signal and anti-phase second clock in first clock with the output drive control voltage.First control module that is electrically connected on input block is used for according to drive control voltage so that first controlling signal to be provided.Be electrically connected on first control module, input block is used for according to drawing drive control voltage and corresponding scanning signal more than first controlling signal with first pull-up unit of the first drop-down unit.Second pull-up unit that is electrically connected on the first drop-down unit is used for according to drawing corresponding luminous signal more than the correspondence scanning signal.The second drop-down unit that is electrically connected on second pull-up unit is used for according to second controlling signal with the luminous signal of drop-down correspondence.Second control module that is electrically connected on the second drop-down unit is used for according to correspondence scanning signal and second clock so that second controlling signal to be provided.
Description of drawings
Fig. 1 is the synoptic diagram of the shift-register circuit of first embodiment of the invention.
Fig. 2 is the work related signal waveform synoptic diagram of shift-register circuit shown in Figure 1, and wherein transverse axis is a time shaft.
Fig. 3 is the synoptic diagram of the shift-register circuit of second embodiment of the invention.
Fig. 4 is the synoptic diagram of the shift-register circuit of third embodiment of the invention.
The reference numeral explanation
Embodiment
Hereinafter be described with reference to the accompanying drawings especially exemplified by embodiment, but the embodiment that is provided not is the scope that contains in order to restriction the present invention according to shift-register circuit of the present invention.
Fig. 1 is the synoptic diagram of the shift-register circuit of first embodiment of the invention.As shown in Figure 1, shift-register circuit 100 comprises multi-stage shift register, for convenience of description, 100 of shift-register circuits show (N-1) level shift register 111, N level shift register 112 and (N+1) level shift register 113, wherein have only N level shift register 112 to show the built-in function unit structure, all the other grades shift register is similar to N level shift register 112, does not give unnecessary details in addition.In the running of shift-register circuit 100, the scanning signal SSn-1 that N level shift register 112 is used for producing according to (N-1) level shift register 111, scanning signal SSn+1, the first clock CK1 that (N+1) level shift register 113 produces, and anti-phase second clock CK2 in the first clock CK1 to produce scanning signal SSn and luminous signal EMn, all the other grades shift register can in like manner be analogized.
N level shift register 112 comprises the first drop-down unit 120, input block 125, first pull-up unit 130, first control module 135, second pull-up unit, 140, the second drop-down unit 145, second control module 150, voltage regulation unit 155 and the 3rd pull-up unit 160.The input block 125 that is electrically connected on (N-1) level shift register 111 is used for according to scanning signal SSn-1 and second clock CK2 with output drive control voltage VQn.The first drop-down unit 120 that is electrically connected on input block 125 and sweep trace LSn is used for according to drive control voltage VQn and the first clock CK1 with drop-down scanning signal SSn, and wherein sweep trace LSn scans signal SSn in order to transmission.First control module 135 that is electrically connected on input block 125 is used for according to drive control voltage VQn so that the first controlling signal SC1 to be provided.First pull-up unit 130 that is electrically connected on first control module 135, input block 125 and the first drop-down unit 120 is used for according to drawing drive control voltage VQn and scanning signal SSn more than the first controlling signal SC1.
Second pull-up unit 140 that is electrically connected on the first drop-down unit 120 and transmission line LEn is used for according to drawing luminous signal EMn more than the scanning signal SSn, and wherein transmission line LEn is in order to transmit luminous signal EMn.Second control module 150 that is electrically connected on the first drop-down unit 120 is used for according to scanning signal SSn and second clock CK2 so that the second controlling signal SC2 to be provided.The second drop-down unit 145 that is electrically connected on the transmission line LEn and second control module 150 is used for according to the second controlling signal SC2 with drop-down luminous signal EMn.The 3rd pull-up unit 160 that is electrically connected on sweep trace LSn and (N+1) level shift register 113 is used for according to drawing scanning signal SSn more than the scanning signal SSn+1.The voltage regulation unit 155 that is electrically connected on the input block 125 and the first drop-down unit 120 is used for according to scanning signal SSn with voltage stabilizing drive control voltage VQn.
In the embodiment in figure 1, the first drop-down unit 120 comprises the first transistor 121, first pull-up unit 130 comprises transistor seconds 131 and the 3rd transistor 132, first control module 135 comprises the 4th transistor 136 and the 5th transistor 137, second pull-up unit 140 comprises the 6th transistor 141, the second drop-down unit 145 comprises the 7th transistor 146, second control module 150 comprises the 8th transistor 151 and the 9th transistor 152, the 3rd pull-up unit 160 comprises the tenth transistor 161, input block 125 comprises the 11 transistor 126 and the tenth two-transistor 127, and voltage regulation unit 155 comprises the 13 transistor 156.Each transistor that note that above-mentioned or the following stated can be thin film transistor (TFT) (Thin Film Transistor; TFT) or field effect transistor (Field Effect Transistor; FET).
The first transistor 121 has gate terminal that first end, that is used for receiving the first clock CK1 is used for receiving drive control voltage VQn, and second end that is used for output scanning signal SSn.The 11 transistor 126 has gate terminal that first end, that is used for receiving scanning signal SSn-1 is used for receiving second clock CK2, and second end that is electrically connected on the tenth two-transistor 127.The tenth two-transistor 127 has gate terminal that first end, that is electrically connected on second end of the 11 transistor 126 is used for receiving second clock CK2, and second end that is electrically connected on the gate terminal of the first transistor 121.The tenth transistor 161 has gate terminal that first end, that is electrically connected on second end of the first transistor 121 is used for receiving scanning signal SSn+1, and second end that is used for receiving high reference voltage VGH.Transistor seconds 131 has gate terminal that first end, that is electrically connected on second end of the first transistor 121 is used for receiving the first controlling signal SC1, and second end that is used for receiving high reference voltage VGH.The 3rd transistor 132 has gate terminal that first end, that is electrically connected on second end of the tenth two-transistor 127 is used for receiving the first controlling signal SC1, and second end that is used for receiving high reference voltage VGH.
The 4th transistor 136 comprises first end, second end and gate terminal, and wherein first end and gate terminal are used for receiving low reference voltage VGL, and second end is used for exporting the first controlling signal SC1.The 5th transistor 137 has gate terminal that first end, that is electrically connected on second end of the 4th transistor 136 is used for receiving drive control voltage VQn, and second end that is used for receiving high reference voltage VGH.The 6th transistor 141 has gate terminal that first end, that is used for receiving high reference voltage VGH is used for receiving scanning signal SSn, and second end that is used for exporting luminous signal EMn.The 7th transistor 146 has gate terminal that first end, that is electrically connected on second end of the 6th transistor 141 is used for receiving the second controlling signal SC2, and second end that is used for receiving low reference voltage VGL.The 8th transistor 151 has gate terminal that first end, that is used for exporting the second controlling signal SC2 is used for receiving second clock CK2, and second end that is used for receiving low reference voltage VGL.The 9th transistor 152 has gate terminal that first end, that is electrically connected on first end of the 8th transistor 151 is used for receiving scanning signal SSn, and second end that is used for receiving high reference voltage VGH.
The 13 transistor 156 comprises first end, second end and gate terminal, and wherein first end and gate terminal are used for receiving scanning signal SSn, and second end is electrically connected on first end of the tenth two-transistor 127.The 13 transistor 156 can transfer to the scanning signal SSn of tool low voltage level first end of the tenth two-transistor 127, and the drain-source extreme pressure difference that is used for reducing the tenth two-transistor 127 to be suppressing leakage current, and then reaches the voltage regulation result of drive control voltage VQn.In another embodiment, the 13 transistor 156 and the tenth two-transistor 127 can omit, second end of the 11 transistor 126 then directly is coupled to the gate terminal of the first transistor 121, the gate terminal of the 5th transistor 137 and first end of the 3rd transistor 132, and the 11 transistor 126 that makes the apparatus low leakage characteristic is to reach the voltage regulation result of drive control voltage VQn.
Fig. 2 is the work related signal waveform synoptic diagram of shift-register circuit shown in Figure 1, and wherein transverse axis is a time shaft.In Fig. 2, basipetal signal is respectively the first clock CK1, second clock CK2, scanning signal SSn-1, drive control voltage VQn, scanning signal SSn, luminous signal EMn and scanning signal SSn+1.Consult Fig. 2 and Fig. 1, in period T1, scanning signal SSn-1 and second clock CK2 switch to low level by high level, so but conducting the 11 transistor 126 and the tenth two-transistor 127 with drop-down drive control voltage VQn to the first low voltage level VL1.At this moment, but drive control voltage VQn conducting the 5th transistor of the tool first low voltage level VL1 draws the paramount reference voltage VGH of the first controlling signal SC1 more than 137, and then by transistor seconds 131 and the 3rd transistor 132.
In period T2, second clock CK2 switches to high level by low level, according to this by the 11 transistor 126 and the tenth two-transistor 127, thereby make drive control voltage VQn become suspension joint voltage, switch to low level because of the first clock CK1 by high level again, so can be by the element capacitive coupling effect of the first transistor 121, drive control voltage VQn is pulled down to the second low voltage level VL2 from the first low voltage level VL1, and conducting the first transistor 121 according to this, will scan signal SSn and be pulled down to low level from high level.At this moment, but have low level scanning signal SSn conducting the 6th transistor 141, and then luminous signal EMn is pulled to high level from low level.Draw the paramount reference voltage VGH of the second controlling signal SC2 more than 152 but have other conducting the 9th transistor of low level scanning signal SSn, thereby by the 7th transistor 146.In addition, but low voltage level conducting ten three transistor 156 of scanning signal SSn in period T2, and then the voltage of first end of the tenth two-transistor 127 is pulled down to low voltage level, the drain-source extreme pressure difference that is used for reducing the tenth two-transistor 127 so can reach the voltage regulation result of drive control voltage VQn to reduce leakage current.
In period T3, but have low level scanning signal SSn+1 conducting the tenth transistor 161, will scan signal SSn according to this and be pulled to high reference voltage VGH, and then by the 6th transistor 141 and the 9th transistor 152.At this moment, CK2 switches to low level by high level because of second clock, but, conducting the 8th transistor 151 promptly is used for conducting the 7th transistor 146 with the extremely low reference voltage VGL of drop-down luminous signal EMn so, having the second controlling signal SC2 of low reference voltage VGL with the extremely low reference voltage VGL of the drop-down second controlling signal SC2.
Please note, as shown in Figure 1, the all crystals pipe of N level shift register 112 is the P transistor npn npn, that is N level shift register 112 based on the circuit that only comprises the P transistor npn npn so that anti-phase each other scanning signal SSn and luminous signal EMn to be provided, in like manner, therefore all the other grades shift register also can significantly simplify semiconductor fabrication process to reduce production costs based on the circuit that only comprises the P transistor npn npn so that anti-phase each other scanning signal and luminous signal to be provided.In addition, the framework that those skilled in the art can be disclosed according to N level shift register 112 and finish the reciprocity shift-register circuit that only comprises the N transistor npn npn easily is not so also break away from the spirit and scope of the present invention based on the reciprocity shift-register circuit that only comprises the N transistor npn npn.
Fig. 3 is the synoptic diagram of the shift-register circuit of second embodiment of the invention.As shown in Figure 3, shift-register circuit 200 comprises multi-stage shift register, for convenience of description, 200 of shift-register circuits show (N-1) level shift register 211, N level shift register 212 and (N+1) level shift register 213, wherein have only N level shift register 212 to show the built-in function unit structure, all the other grades shift register is similar to N level shift register 212, does not give unnecessary details in addition.In the running of shift-register circuit 200, the start pulse signal STn-1 that N level shift register 212 is used for producing according to (N-1) level shift register 211, scanning signal SSn+1, the first clock CK1 that (N+1) level shift register 213 produces, and anti-phase second clock CK2 in the first clock CK1 to produce scanning signal SSn, luminous signal EMn and start pulse signal STn, all the other grades shift register can in like manner be analogized.
N level shift register 212 is similar to N level shift register 112 shown in Figure 1, and main difference is input block 125 is replaced into input block 225, the 3rd pull-up unit 160 is replaced into the 3rd pull-up unit 260, and also comprises carry unit 270.The input block 225 that is electrically connected on (N-1) level shift register 211 is used for according to start pulse signal STn-1 and second clock CK2 to export drive control voltage VQn.The carry unit 270 that is electrically connected on input block 225 is used for according to drive control voltage VQn and the first clock CK1 with output start pulse signal STn.The 3rd pull-up unit 260 that is electrically connected on the first drop-down unit 120, carry unit 270 and (N+1) level shift register 213 is used for according to drawing scanning signal SSn and start pulse signal STn more than the scanning signal SSn+1.
In the embodiments of figure 3, input block 225 comprises the 11 transistor 226 and the tenth two-transistor 227, and carry unit comprises the 14 transistor 271, the three pull-up units 260 and comprises the tenth transistor 261 and the 15 transistor 262.The 11 transistor 226 has gate terminal that first end, that is used for receiving start pulse signal STn-1 is used for receiving second clock CK2, and second end that is electrically connected on the tenth two-transistor 227.The tenth two-transistor 227 has gate terminal that first end, that is electrically connected on second end of the 11 transistor 226 is used for receiving second clock CK2, and second end that is electrically connected on the gate terminal of the first transistor 121.The 14 transistor 271 has gate terminal that first end, that is used for receiving the first clock CK1 is used for receiving drive control voltage VQn, and second end that is used for exporting start pulse signal STn.The tenth transistor 261 has gate terminal that first end, that is electrically connected on second end of the first transistor 121 is used for receiving scanning signal SSn+1, and second end that is used for receiving high reference voltage VGH.The 15 transistor 262 has gate terminal that first end, that is electrically connected on second end of the 14 transistor 271 is electrically connected on the gate terminal of the tenth transistor 261, and second end that is used for receiving high reference voltage VGH.In another embodiment, the gate terminal of the tenth transistor 261 is electrically connected on (N+1) level shift register 213 to receive start pulse signal STn+1.
Because the waveform of start pulse signal STn-1, start pulse signal STn and start pulse signal STn+1 is same as the waveform of scanning signal SSn-1, scanning signal SSn and scanning signal SSn+1 in fact respectively, so the circuit working principle of N level shift register 212 can in like manner be analogized according to the circuit working principle of above-mentioned N level shift register 112.In addition, as shown in Figure 3, the all crystals pipe of N level shift register 212 is the P transistor npn npn, that is to say, N level shift register 212 also based on the circuit that only comprises the P transistor npn npn so that anti-phase each other scanning signal SSn and luminous signal EMn to be provided, and the start pulse signal STn that is used for driving (N+1) level shift register 213 also is provided, so still can significantly simplify semiconductor fabrication process to reduce production costs.
Fig. 4 is the synoptic diagram of the shift-register circuit of third embodiment of the invention.As shown in Figure 4, shift-register circuit 300 comprises multi-stage shift register, for convenience of description, 300 of shift-register circuits show (N-1) level shift register 311, N level shift register 312 and (N+1) level shift register 313, wherein have only N level shift register 312 to show the built-in function unit structure, all the other grades shift register is similar to N level shift register 312, does not give unnecessary details in addition.In the running of shift-register circuit 300, the start pulse signal STn-1 that N level shift register 312 is used for producing according to (N-1) level shift register 311, scanning signal SSn+1, the first clock CK1 that (N+1) level shift register 313 produces, and anti-phase second clock CK2 in the first clock CK1 to produce scanning signal SSn, luminous signal EMn and start pulse signal STn, all the other grades shift register can in like manner be analogized.
N level shift register 312 is similar to N level shift register 212 shown in Figure 3, and main difference is first pull-up unit 130 is replaced into first pull-up unit 330, and the 3rd pull-up unit 260 is replaced into the 3rd pull-up unit 360.First pull-up unit 330 that is electrically connected on first control module 135, input block 225, the first drop-down unit 120 and carry unit 270 is used for according to drawing drive control voltage VQn, scanning signal SSn and start pulse signal STn more than the first controlling signal SC1.The 3rd pull-up unit 360 that is electrically connected on input block 225, the first drop-down unit 120, carry unit 270 and (N+1) level shift register 313 is used for according to drawing drive control voltage VQn, scanning signal SSn and start pulse signal STn more than the scanning signal SSn+ 1.
In the embodiment of Fig. 4, first pull-up unit 330 comprises transistor seconds 331, the 3rd transistor 332 and the 16 transistor 333, the three pull-up units 360 and comprises the tenth transistor the 361, the 15 transistor 362 and the 17 transistor 363.Transistor seconds 331 has gate terminal that first end, that is electrically connected on second end of the first transistor 121 is used for receiving the first controlling signal SC1, and second end that is used for receiving high reference voltage VGH.The 3rd transistor 332 has gate terminal that first end, that is electrically connected on second end of the tenth two-transistor 227 is used for receiving the first controlling signal SC1, and second end that is used for receiving high reference voltage VGH.The 16 transistor 333 has gate terminal that first end, that is electrically connected on second end of the 14 transistor 271 is used for receiving the first controlling signal SC1, and second end that is used for receiving high reference voltage VGH.
The tenth transistor 361 has gate terminal that first end, that is electrically connected on second end of the first transistor 121 is used for receiving scanning signal SSn+1, and second end that is used for receiving high reference voltage VGH.The 15 transistor 362 has gate terminal that first end, that is electrically connected on second end of the 14 transistor 271 is electrically connected on the gate terminal of the tenth transistor 361, and second end that is used for receiving high reference voltage VGH.The 17 transistor 363 has gate terminal that first end, that is electrically connected on second end of the tenth two-transistor 227 is electrically connected on the gate terminal of the tenth transistor 361, and second end that is used for receiving high reference voltage VGH.In another embodiment, the gate terminal of the tenth transistor 361 is electrically connected on (N+1) level shift register 313 to receive start pulse signal STn+ 1.
Basically, the circuit working principle of N level shift register 312 is similar to the circuit working principle of above-mentioned N level shift register 212.In addition, as shown in Figure 4, the all crystals pipe of N level shift register 312 is the P transistor npn npn, so N level shift register 312 also based on the circuit that only comprises the P transistor npn npn so that anti-phase each other scanning signal SSn and luminous signal EMn to be provided, and the start pulse signal STn that is used for driving (N+1) level shift register 313 is provided in addition, so still can significantly simplify semiconductor fabrication process to reduce production costs.
To sum up, shift register of the present invention can be based on the circuit that only comprises P transistor npn npn or N transistor npn npn to provide anti-phase each other scanning signal and luminous signal to pixel cell, make pixel cell can carry out light emitting control running and transistor critical voltage compensation running according to this, so can significantly simplify semiconductor fabrication process to reduce production costs.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention is to be as the criterion with claim of the present invention.
Claims (20)
1. a shift-register circuit is used to provide a plurality of scanning signals and a plurality of luminous signal, and this shift-register circuit comprises multi-stage shift register, and a N level shift register of these grades shift register comprises:
One first drop-down unit is used for scanning the N scanning signal of signals according to a drive control voltage and one first clock with drop-down these;
One input block is electrically connected on this first drop-down unit, and this input block is used for according to one first input signal and an anti-phase second clock in this first clock to export this drive control voltage;
One first control module is electrically connected on this input block, and this first control module is used for according to this drive control voltage so that one first controlling signal to be provided;
One first pull-up unit is electrically connected on this first control module, this input block and this first drop-down unit, and this first pull-up unit is used for drawing this drive control voltage and this N scanning signal more than first controlling signal according to this;
One second pull-up unit is electrically connected on this first drop-down unit, and this second pull-up unit is used for scanning the luminous signal of a N that draws these luminous signals more than the signal according to this N;
One second drop-down unit is electrically connected on this second pull-up unit, and this second drop-down unit is used for according to one second controlling signal with the luminous signal of drop-down this N; And
One second control module is electrically connected on this second drop-down unit, and this second control module is used for according to this N scanning signal and this second clock so that this second controlling signal to be provided.
2. shift-register circuit as claimed in claim 1, wherein this first drop-down unit comprises:
One the first transistor has gate terminal that first end, that is used for receiving this first clock is used for receiving this drive control voltage, and second end that is used for exporting this N scanning signal.
3. shift-register circuit as claimed in claim 1, wherein this first pull-up unit comprises:
One transistor seconds has gate terminal that first end, that is electrically connected on this first drop-down unit is used for receiving this first controlling signal, and second end that is used for receiving a high reference voltage; And
One the 3rd transistor has gate terminal that first end, that is electrically connected on this input block is used for receiving this first controlling signal, and second end that is used for receiving this high reference voltage.
4. shift-register circuit as claimed in claim 1, wherein this first control module comprises:
One the 4th transistor has gate terminal that first end, that is used for receiving a low reference voltage is electrically connected on this first end, and second end that is used for exporting this first controlling signal; And
One the 5th transistor has gate terminal that first end, that is electrically connected on the 4th transistorized second end is used for receiving this drive control voltage, and second end that is used for receiving a high reference voltage.
5. shift-register circuit as claimed in claim 1, wherein this second pull-up unit comprises:
One the 6th transistor has gate terminal that first end, that is used for receiving a high reference voltage is used for receiving this N scanning signal, and second end that is used for exporting the luminous signal of this N.
6. shift-register circuit as claimed in claim 1, wherein this second drop-down unit comprises:
One the 7th transistor has gate terminal that first end, that is electrically connected on this second pull-up unit is used for receiving this second controlling signal, and second end that is used for receiving a low reference voltage.
7. shift-register circuit as claimed in claim 1, wherein this second control module comprises:
One the 8th transistor has gate terminal that first end, that is used for exporting this second controlling signal is used for receiving this second clock, and second end that is used for receiving a low reference voltage; And
One the 9th transistor has gate terminal that first end, that is electrically connected on the 8th transistorized first end is used for receiving this N scanning signal, and second end that is used for receiving a high reference voltage.
8. shift-register circuit as claimed in claim 1, wherein this N level shift register also comprises:
One the 3rd pull-up unit is electrically connected on this first drop-down unit, and the 3rd pull-up unit is used for according to drawing this N scanning signal more than one second input signal.
9. shift-register circuit as claimed in claim 8, wherein the 3rd pull-up unit comprises:
The tenth transistor has gate terminal that first end, that is electrically connected on this first drop-down unit is used for receiving this second input signal, and second end that is used for receiving a high reference voltage.
10. shift-register circuit as claimed in claim 8, wherein this first input signal is one (N-1) scanning signal of these scanning signals, this second input signal is one (N+1) scanning signal of these scanning signals.
11. shift-register circuit as claimed in claim 1, wherein this input block comprises:
The 11 transistor has gate terminal that first end, that is used for receiving this first input signal is used for receiving this second clock, and second end that is electrically connected on this first drop-down unit.
12. shift-register circuit as claimed in claim 1, wherein this N level shift register also comprises:
One voltage regulation unit is electrically connected on this input block and this first drop-down unit, and this voltage regulation unit is used for according to this N scanning signal with this drive control voltage of voltage stabilizing.
13. shift-register circuit as claimed in claim 12, wherein:
This input block comprises:
The 11 transistor has gate terminal that first end, that is used for receiving this first input signal is used for receiving this second clock, and one second end; And
The tenth two-transistor has gate terminal that first end, that is electrically connected on the 11 transistorized second end is used for receiving this second clock, and second end that is electrically connected on this first drop-down unit; And
This voltage regulation unit comprises:
The 13 transistor has gate terminal that first end, that is used for receiving this N scanning signal is used for receiving this N scanning signal, and second end that is electrically connected on first end of the tenth two-transistor.
14. shift-register circuit as claimed in claim 1, wherein this N level shift register also comprises:
One carry unit is electrically connected on this input block, and this carry unit is used for according to this drive control voltage and this first clock to export a N start pulse signal; And
One the 3rd pull-up unit is electrically connected on this input block, this first drop-down unit and this carry unit, and the 3rd pull-up unit is used for according to drawing this drive control voltage, this N scanning signal and this N start pulse signal more than one second input signal.
15. shift-register circuit as claimed in claim 14, wherein this first input signal is one (N-1) start pulse signal, and this second input signal is one (N+1) scanning signal of one (N+1) start pulse signal or these scanning signals.
16. shift-register circuit as claimed in claim 14, wherein this carry unit comprises:
The 14 transistor has gate terminal that first end, that is used for receiving this first clock is used for receiving this drive control voltage, and second end that is used for exporting this N start pulse signal.
17. shift-register circuit as claimed in claim 14, wherein the 3rd pull-up unit comprises:
The tenth transistor has gate terminal that first end, that is electrically connected on this first drop-down unit is used for receiving this second input signal, and second end that is used for receiving a high reference voltage; And
The 15 transistor has gate terminal that first end, that is electrically connected on this carry unit is used for receiving this second input signal, and second end that is used for receiving this high reference voltage.
18. shift-register circuit as claimed in claim 17, wherein the 3rd pull-up unit also comprises:
The 17 transistor has gate terminal that first end, that is electrically connected on this input block is used for receiving this second input signal, and second end that is used for receiving this high reference voltage.
19. shift-register circuit as claimed in claim 14, wherein this first pull-up unit also is used for drawing this N start pulse signal more than first controlling signal according to this.
20. shift-register circuit as claimed in claim 19, wherein this first pull-up unit comprises:
One transistor seconds has gate terminal that first end, that is electrically connected on this first drop-down unit is used for receiving this first controlling signal, and second end that is used for receiving a high reference voltage;
One the 3rd transistor has gate terminal that first end, that is electrically connected on this input block is used for receiving this first controlling signal, and second end that is used for receiving this high reference voltage; And
The 16 transistor has gate terminal that first end, that is electrically connected on this carry unit is used for receiving this first controlling signal, and second end that is used for receiving this high reference voltage.
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| TW100114848A TWI493557B (en) | 2011-04-28 | 2011-04-28 | Shift register circuit |
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| TWI493557B (en) | 2015-07-21 |
| CN102201194B (en) | 2014-01-01 |
| TW201243853A (en) | 2012-11-01 |
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