CN102194203B - A kind of method and apparatus reducing Face datection memory space - Google Patents
A kind of method and apparatus reducing Face datection memory space Download PDFInfo
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Abstract
The present invention relates to a kind of method and apparatus reducing Face datection memory space, wherein, the method comprises: the pixel bit wide reducing image to be detected; The error diffusion that the gray-scale value of each pixel produces by employing error-diffusion method in reduction pixel bit is wider than journey is on neighbor pixel; To reducing pixel bit wide and having carried out the image of error diffusion, ask for its integral image and square integral image; Wherein, integral image required storage is (pixel bit wide+log
2(W
*h))
*w
*h bit, integrated square image required storage is (pixel bit wide
*2+log
2(W
*h))
*w
*h bit, W is the pixel quantity of picture traverse, and H is the pixel quantity of picture altitude.The present invention, by reducing the pixel bit wide of image and carrying out error diffusion, under the prerequisite not affecting Face datection algorithm, saves integral image and the storage space needed for square integral image in hardware chip, reduces chip cost.
Description
Technical field
The present invention relates to a kind of method and apparatus reducing Face datection memory space.
Background technology
Along with the popularization of video monitoring, human face detection tech and become more and more important.In various human face detection tech, adopt the human face detection tech accuracy rate of AdaBoost self-adaptive enhancement algorithm higher, and realized by hardware chip.The gray level image of the 8 bit bit wides that this technology generally adopts CCD or cmos camera to export is as input.
Fig. 1 is the exemplary plot of the micro-feature adopted in the human face detection tech based on AdaBoost self-adaptive enhancement algorithm.
As shown in Figure 1, in the Face datection processing procedure of this technology, this technology have employed a lot of typical micro-feature.
Such as, a kind of template of leftmost micro-character representation.In processes, need first to obtain pixel in white piece of corresponding region and, then the pixel obtained in black patch corresponding region and, then both are subtracted each other.In the same position of face and non-face picture, the size of the value calculated is different, therefore this slightly feature can be used for distinguishing face and non-face.As can be seen here, in Face datection, a large amount of computing relate to ask pixel in certain region and.In order to accelerate this computation process, need a link being specifically designed to calculated product partial image and square integral image, and the memory space that this link takies is many.
Fig. 2 is the schematic diagram of calculated product partial image and square integral image.
As shown in Figure 2, image is divided into A, B, C, D tetra-regions, and the point in the lower right corner, each region is 1,2,3,4 points respectively, and the coordinate in the image lower right corner is (x, y).
At coordinate points (x, y), the value of integral image be by the rectangular area formed between the shown image upper left corner and the lower right corner the summation of gray-scale value a little.Such as, the gray-scale value summation of each point in the A of region is represented the value of 1, referred to as I1; Represent the gray-scale value summation of each point in the A+B of region the values of 2, be designated as I2; Similar, be designated as I3 the value of 3; I4 is designated as the value of 4.So the gray-scale value summation of rectangular area D can be expressed as I1+I4-I2-I3.
Similar, integrated square image represents the summation of each point gray-scale value square of region A the value of 1, referred to as A, being A+B the values of 2, is A+C the values of 3, is A+B+C+D the values of 4.So, the summation of the gray-scale value of rectangular area D square also can by the 1st, 2,3, the integrated square image value of 4 simply draws.
Should be appreciated that an effable different colours number of pixel depends on bit per pixel (bpp, bitper pixel), such as 8bpp represents each pixel 8 bits and represents, namely pixel bit wide is 8 bits.In general, pixel bit wide can be referred to as image bit wide.
If piece image is wide is W pixel, height is H pixel, and pixel bit wide is 8 bits; Then in integral image, the maximum bit wide that certain pixel may need is 8+log
2(W
*h), the memory space that therefore whole integral image needs is about (8+log
2(W
*h))
*w
*h bit; In like manner, in integrated square image, the maximum bit wide that certain pixel may need is 16+log
2(W
*h), the memory space that therefore whole integrated square image needs is about (16+log
2(W
*h))
*w
*h bit.
As can be seen from above-mentioned formula, integral image and the memory space needed for square integral image and pixel bit wide have very direct relation, pixel bit can cause the memory space required for integral image and square integral image very large wider than height, thus increases the cost of hardware chip.
Summary of the invention
The invention provides a kind of method and apparatus of the reduction Face datection memory space that can overcome the above problems.
In first aspect, provide a kind of method reducing Face datection memory space, comprising: the pixel bit wide reducing image to be detected; The error diffusion that the gray-scale value of each pixel produces by employing error-diffusion method in reduction pixel bit is wider than journey is on neighbor pixel; To reducing pixel bit wide and having carried out the image of error diffusion, ask for its integral image and square integral image; Wherein, integral image required storage is (pixel bit wide+log
2(W
*h))
*w
*h bit, integrated square image required storage is (pixel bit wide
*2+log
2(W
*h))
*w
*h bit, W is the pixel quantity of picture traverse, and H is the pixel quantity of picture altitude.
Preferably, error-diffusion method is being reduced on the error diffusion that produces in the pixel bit wide right to described pixel, lower left, below and bottom-right four neighbor pixels by the gray-scale value of pixel.
Preferably, the error distribution ratio adopted in error diffusion is 3: 3: 5: 5, distinguishes the right of corresponding described pixel, lower left, below and bottom-right neighbor pixel.
Preferably, pixel bit wide reduces is that pixel bit wide is reduced to 6 bits from 8 bits.
In second aspect, provide a kind of equipment reducing Face datection memory space, comprising: the module reducing the pixel bit wide of image to be detected; The error diffusion that the gray-scale value of each pixel produces by employing error-diffusion method in reduction pixel bit is wider than journey is to the module on neighbor pixel; To reducing pixel bit wide and having carried out the image of error diffusion, ask for the module of its integral image and square integral image; Wherein, integral image required storage is (pixel bit wide+log
2(W
*h))
*w
*h bit, integrated square image required storage is (pixel bit wide
*2+log
2(W
*h))
*w
*h bit, W is the pixel quantity of picture traverse, and H is the pixel quantity of picture altitude.
The present invention, by reducing the pixel bit wide of image to be checked in Face datection process, saves in hardware chip storage space required when calculating integral image and square integral image, reduces chip cost; And the error produced in pixel bit wide reduction process is spread, reduce the impact of the result of calculation on integral image and square integral image, thus the energy maintaining image is substantially constant.
Accompanying drawing explanation
Below with reference to accompanying drawings specific embodiment of the invention scheme is described in detail, in the accompanying drawings:
Fig. 3 is the method schematic diagram reducing Face datection hardware store amount according to an embodiment of the invention; And
Fig. 4 is the schematic diagram of error-diffusion method according to an embodiment of the invention.
Embodiment
In the present invention, in order to reduce the memory space required for calculated product partial image and square integral image in Face datection process, adopt when carrying out described calculating the image that precision is lower.Such as, every in image pixel 6 bits or 5 bits are represented, reduces the precision of images.
Fig. 3 is the method schematic diagram reducing Face datection hardware store amount according to an embodiment of the invention.
As shown in Figure 3, the pixel bit wide of image to be detected is first reduced; Then, the error diffusion adopting error-diffusion method just to produce in pixel bit wide is opened; Finally, to reducing pixel bit wide and having carried out the image of error diffusion, its integral image and square integral image is asked for.
It should be pointed out that and various method can be adopted to reduce the pixel bit wide of image.Such as, the grayvalue transition of pixel can be become expect the gray-scale value corresponding to pixel bit wide, thus reduce pixel bit wide.
Fig. 4 is the schematic diagram of error-diffusion method according to an embodiment of the invention.
Such as, the image of 8 bit bit wides, namely 256 grades of gray level images has a pixel, and its gray-scale value is 110 (0 ~ 255).If this pixel will be converted to the pixel value of 6 bits, i.e. 64 grades of gray scales, a kind of method is divided by 4 by this pixel value.So, the gray-scale value after changing is 110/4=27.5, is exactly 27 after retaining integer-bit, there is the error of 0.5 as seen after conversion.
In order to make the image after conversion close to original image, need with error-diffusion method, the error diffusion introduced in transfer process to be opened.So-called error diffusion, is exactly when pixel depth reduces, the variation error of pixel color is spread apart.By error diffusion, make naked eyes when observation picture, the error of the Set Global of neighbor pixel diminishes, and more presses close to original image.
As shown in Figure 4, when the gray-scale value of previous 8 bit pixel points is P, after becoming 6 bits, its gray-scale value is P ', then the error d (relative to 8 bit grayscale value) introduced in this process is:
D=P-4
*p ' (being multiplied by 4 is because P ' is 6 bit values)
After this error is multiplied by corresponding weight, on 4 pixels being added to adjacent: right, lower left, below, lower right, its corresponding weight is 3/16,3/16,5/16,5/16.Weight illustrates adopted error diffusion scheme, and the error distribution ratio namely for the neighbor pixel of correspondence is 3: 3: 5: 5.
Should be appreciated that and by error diffusion on adjacent less and/or more pixel, can also adopt other error distribution ratio in error diffusion, the error distribution ratio of such as 7: 3: 5: 1 and so on.
Such as, originally the gray-scale value of 8 bit pixel points of below is Q, and after overlay error, its gray-scale value Q ' becomes:
Q’＝Q+d
＊5/16
The rest may be inferred, can draw the gray-scale value of other neighbor pixels.Such as, after overlay error, the gray-scale value of this pixel right, lower left and bottom-right neighbor pixel is respectively: Q+d
*3/16, Q+d
*3/16, Q+d
*5/16.By such error diffusion, and then can obtain a fabric width, high identical with original image, pixel bit wide is the image of 6 bits.Then, the image being 6 bits to pixel bit wide calculates its integral image and square integral image.From on calculating to integral image and square integral image, before reduction pixel bit wide, the memory space of integral image is (8+log
2(W
*h))
*w
*h bit, the memory space of integrated square image is (16+log
2(W
*h))
*w
*h, after the pixel bit wide reducing image, the memory space of integral image is reduced to (6+log
2(W
*h))
*w
*h bit, the memory space of integrated square image is reduced to (12+log
2(W
*h))
*w
*h bit.As can be seen here, integral image and square integral image required storage have had obvious reduction after pixel bit wide reduces.
By adopting error-diffusion method, the pixel bit wide of image is reduced integral image impact less.Because in certain region, the error that each pixel brings because reducing bit wide is generally all diffused on pixel adjacent in the same area.In addition, relative to the impact concerning integral image, adopt error-diffusion method slightly large on the impact of integrated square image, but general also negligible.Adopt error-diffusion method to lower the pixel bit wide of image, the energy of image can be kept substantially constant.
Like this, under the prerequisite substantially not affecting Face datection algorithm, save hardware chip and preserve integral image and the storage space required for square integral image, reduce the cost of chip.
In addition, after the pixel bit wide reduction of image, simplification can also be made to corresponding arithmetic element (as multiplier, divider etc.).
In other examples, also the image of 8 bit bit wides can be reduced to the image of 5 bits, 4 bits or other bit wides.Should be appreciated that according to embody rule occasion, suitable bit wide can be chosen.
Obviously, under the prerequisite not departing from true spirit of the present invention and scope, the present invention described here can have many changes.Therefore, all changes that it will be apparent to those skilled in the art that, all should be included within scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (5)
1. reduce a method for Face datection memory space, comprising:
Reduce the pixel bit wide of image to be detected;
The error diffusion that the gray-scale value of each pixel produces by employing error-diffusion method in reduction pixel bit is wider than journey is on neighbor pixel;
To reducing pixel bit wide and having carried out the image of error diffusion, ask for its integral image and square integral image;
Wherein, integral image required storage is (pixel bit wide+log
2(W*H)) * W*H bit, integrated square image required storage is (pixel bit wide * 2+log
2(W*H)) * W*H bit, W is the pixel quantity of picture traverse, and H is the pixel quantity of picture altitude.
2. method according to claim 1, wherein, error-diffusion method is being reduced on the error diffusion that produces in the pixel bit wide right to described pixel, lower left, below and bottom-right four neighbor pixels by the gray-scale value of pixel.
3. method according to claim 2, wherein, the error distribution ratio adopted in error diffusion is 3: 3: 5: 5, distinguishes the right of corresponding described pixel, lower left, below and bottom-right neighbor pixel.
4. method according to claim 1, wherein, it is that pixel bit wide is reduced to 6 bits from 8 bits that pixel bit wide reduces.
5. reduce an equipment for Face datection memory space, comprising:
Reduce the module of the pixel bit wide of image to be detected;
The error diffusion that the gray-scale value of each pixel produces by employing error-diffusion method in reduction pixel bit is wider than journey is to the module on neighbor pixel;
To reducing pixel bit wide and having carried out the image of error diffusion, ask for the module of its integral image and square integral image;
Wherein, integral image required storage is (pixel bit wide+log
2(W*H)) * W*H bit, integrated square image required storage is (pixel bit wide * 2+log
2(W*H)) * W*H bit, W is the pixel quantity of picture traverse, and H is the pixel quantity of picture altitude.
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| 场致发射显示器新型图像驱动技术的研究;林志贤等;《液晶与显示》;20091031;第24卷(第5期);685-691 * |
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Address after: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Patentee after: Mid Star Technology Limited by Share Ltd Address before: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Patentee before: Zhongxing Technology Co., Ltd. Address after: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Patentee after: Mid Star Technology Limited by Share Ltd Address before: 100083 Haidian District, Xueyuan Road, No. 35, the world building, the second floor of the building on the ground floor, No. 16 Patentee before: Zhongxing Technology Co., Ltd. |
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