CN102184859A - Manufacturing method of cold metal oxide semiconductor (MOS) super-junction structure and cold MOS super-junction structure - Google Patents
Manufacturing method of cold metal oxide semiconductor (MOS) super-junction structure and cold MOS super-junction structure Download PDFInfo
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Abstract
The invention provides a manufacturing method of a cold metal oxide semiconductor (MOS) super-junction structure. The method comprises the following steps of: providing an N type semiconductor substrate; forming an N type epitaxial layer on the N type semiconductor substrate; etching a deep groove on the N type epitaxial layer; depositing heavily doped polysilicon in the deep groove, and fully filling the deep groove; and diffusing impurities in the heavily doped polysilicon into the N type epitaxial layer to form an impurity diffusing area. Correspondingly, the invention also provides the cold MOS super-junction structure. The cold MOS super-junction structure is manufactured through a deep groove etching technology, so complex processes, such as photoetching for multiple times, ion implantation, propelling, epitaxial growth and the like, required in the preparation of the traditional super-junction structure are avoided, the manufacturing cost is effectively reduced, and the defect that electricity leakage is easy to cause when an MOS device works because the joint face of the traditional super-junction structure which is in a shape like sugarcoated haws on a stick is not uniform. By the method, the breakdown voltage of the MOS device can be effectively increased, the on resistance of the MOS device can be greatly reduced, the process is simple, and the controllability is high.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, the present invention relates to a kind of manufacture method and a kind of cold MOS super-junction structure of cold MOS super-junction structure.
Background technology
Power MOSFET with its input impedance height, loss is low, switching speed is fast, no second breakdown, the safety operation area is wide, dynamic property good, easily generally be used for low-power conversion and control field with characteristics such as the big electric currentization of preceding utmost point coupling realization, conversion efficiency height.Though power MOS (Metal Oxide Semiconductor) device has obtained surprising raising on power handling capability, in the high pressure field,, make the conduction loss of power MOS (Metal Oxide Semiconductor) device rise rapidly along with withstand voltage raising owing to conducting resistance Ron., reduction conduction loss withstand voltage in order to improve, a series of new construction, new technology are arisen at the historic moment.And the effect of super knot (Super Junction) technology in the high pressure field that wherein is used for improving the power MOS (Metal Oxide Semiconductor) device performance showing very much, attracted large quantities of device suppliers research and development of injecting capital into, successfully developed the cold MOS in plane at present and dropped into commercial the application.
Cold MOS (Cool MOS) has another name called Super Junction MOSFET (super node MOSFET), invented by the Chen Xing of the Chengdu University of Electronic Science and Technology academician that assists at first, after transfer company of German Infineon.As the new device of power MOSFET field milestone, Cool MOS has broken the theoretical limit of conventional power MOSFET, comes out in 1998 and also moves towards market very soon.
Compare with common high-voltage MOSFET, Cool MOS is owing to adopt new structure of voltage-sustaining layer, utilized the notion of super knot, when almost keeping all advantages of power MOSFET, extremely low conduction loss is arranged again, caloric value is very low, can also show in addition to reduce chip area, so just be called Cool MOS.At this power transistor with 600 volts is example, uses the conducting resistance of the Cool MOS with super-junction structure to have only 20% of conventional power transistors of the same area.And its output capacitance, input capacitance also reduce synchronously, and the operating frequency characteristic of device is improved.
In the prior art, the preparation of super-junction structure mainly is to use a kind of repeatedly injection, multilayer epitaxial to form the method for super knot.Fig. 1 is use in the prior art is repeatedly injected, multilayer epitaxial forms super-junction structure cross-sectional view.As shown in the figure, this method is by extension successively on N type silicon substrate 100, and the mode of using ion to inject p type impurity on each layer N type epitaxial loayer 101～103 respectively correspondingly successively forms the P trap 104～106 of same horizontal level.Advance with boiler tube technology then, the expanded range of the P trap 104～106 in the N type epitaxial loayer 101～103 is come, the P trap 104～106 of same horizontal level is together in series up and down and forms a kind of " sugarcoated haws " shape, obtains super-junction structure.
As seen, need in the preparation of traditional super-junction structure through repeatedly photoetching, ion injection, propelling and epitaxial growth, complex process and cost are very high.In addition, the super-junction structure with " sugarcoated haws " shape that Using such method forms has the uneven shortcoming in composition surface, and leaky takes place when causing cold MOS device to work easily for this, thereby reduces the electric property of device.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method and a kind of cold MOS super-junction structure of cold MOS super-junction structure, can avoid needing complicated technologies such as repeatedly photoetching, ion injection, propelling and epitaxial growth in the preparation of traditional super-junction structure, effectively reduce manufacturing cost, and overcome the uneven shortcoming in super-junction structure composition surface of traditional " sugarcoated haws " shape.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of cold MOS super-junction structure, comprise step:
The N type semiconductor substrate is provided;
On described N type semiconductor substrate, form N type epitaxial loayer;
On described N type epitaxial loayer, etch deep trench;
The heavily doped polysilicon of deposit fills up described deep trench in described deep trench;
Diffusion of impurities in the described heavily doped polysilicon in described N type epitaxial loayer, is formed impurity diffusion zone.
Alternatively, described N type semiconductor substrate is a N type heavily-doped semiconductor substrate.
Alternatively, the width of described deep trench is 0.4～3 μ m, and the degree of depth is 10～80 μ m, and the angle between the described N type epitaxial loayer is 80～90 degree.
Alternatively, described heavily doped polysilicon is the P type.
Alternatively, described diffusion of impurities is done down to advance to finish at 1000～2000 ℃.
Alternatively, the degree of depth of described impurity diffusion zone is 0.5～5 μ m.
Correspondingly, the present invention also provides a kind of cold MOS super-junction structure, comprise the N type epitaxial loayer that is positioned on the N type semiconductor substrate, be etched with deep trench on the described N type epitaxial loayer, be deposited with heavily doped polysilicon in the described deep trench and fill up described deep trench, the described deep trench outside is surrounded by the impurity diffusion zone that is penetrated in the described N type epitaxial loayer.
Alternatively, described N type semiconductor substrate is a N type heavily-doped semiconductor substrate.
Alternatively, the width of described deep trench is 0.4～3 μ m, and the degree of depth is 10～80 μ m, and the angle between the described N type epitaxial loayer is 80～90 degree.
Alternatively, described heavily doped polysilicon is the P type.
Alternatively, the degree of depth of described impurity diffusion zone is 0.5～5 μ m.
Compared with prior art, the present invention has the following advantages:
The present invention adopts deep plough groove etched technology to make the super-junction structure of cold MOS, avoided needing complicated technologies such as repeatedly photoetching, ion injection, propelling and epitaxial growth in the preparation of traditional super-junction structure, effectively reduce manufacturing cost, and the super-junction structure composition surface that has overcome traditional " sugarcoated haws " shape is inhomogeneous, and the shortcoming of electric leakage takes place when easily causing cold MOS device to work.The charge balance concept of the present invention by super knot both sides not only can improve the puncture voltage of power MOS (Metal Oxide Semiconductor) device effectively, significantly reduce conducting resistance, and technology is simple, controllability is good.
Description of drawings
Above-mentioned and other feature, character and advantage of the present invention will become more obvious by the description below in conjunction with drawings and Examples, wherein:
Fig. 1 is use in the prior art is repeatedly injected, multilayer epitaxial forms super-junction structure generalized section;
Fig. 2 is the flow chart of manufacture method of the cold MOS super-junction structure of one embodiment of the invention;
Fig. 3 to Fig. 5 is the cross-sectional view of manufacture process of the cold MOS super-junction structure of one embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Fig. 2 is the flow chart of manufacture method of the cold MOS super-junction structure of one embodiment of the invention.As shown in the figure, this manufacture method originates in step S201.This method can comprise: execution in step S201 provides the N type semiconductor substrate; Execution in step S202 forms N type epitaxial loayer on the N type semiconductor substrate; Execution in step S203 etches deep trench on N type epitaxial loayer; Execution in step S204, the heavily doped polysilicon of deposit fills up deep trench in deep trench; Execution in step S204 in N type epitaxial loayer, forms impurity diffusion zone with the diffusion of impurities in the heavily doped polysilicon.
Fig. 3 to Fig. 5 is the cross-sectional view of manufacture process of the cold MOS super-junction structure of one embodiment of the invention.
As shown in Figure 3, provide N type semiconductor substrate 300, this N type semiconductor substrate 300 is specifically as follows N type heavily-doped semiconductor substrate.More specifically, this N type semiconductor substrate 300 can be N type heavily doped silicon (Si) substrate.
Then, form N type epitaxial loayer 302 on this N type semiconductor substrate 300, the method that forms this N type epitaxial loayer 302 can adopt the technology of well known to a person skilled in the art.
Afterwards, etch deep trench 304 on this N type epitaxial loayer 302, the method for this deep trench 304 of etching can adopt the dry etching method, and the width of this deep trench 304 can be 0.4～3 μ m, the degree of depth can be 10～80 μ m, and the angle between the N type epitaxial loayer 302 can be 80～90 degree.The concrete numerical value of shape that it will be understood by those skilled in the art that above-mentioned deep trench 304 can be according to the performance of power MOS (Metal Oxide Semiconductor) device and concrete the setting.
As shown in Figure 4, the heavily doped polysilicon of deposit (Poly Silicon) 306 fills up deep trench 304 in deep trench 304.This heavily doped polysilicon 306 can be the P type.
As shown in Figure 5, the diffusion of impurities in the heavily doped polysilicon 306 in N type epitaxial loayer, is formed impurity diffusion zone 308, finish the manufacture process of the cold MOS super-junction structure of present embodiment thus, can obtain cold MOS super-junction structure provided by the present invention.This diffusion of impurities process is done down to advance to finish at 1000～2000 ℃ in boiler tube, and the degree of depth 310 of this impurity diffusion zone 308 can be 0.5～5 μ m.
After forming above-mentioned cold MOS super-junction structure, can also proceed traditional MOS technology, finally finish the manufacturing process of power MOS (Metal Oxide Semiconductor) device.
Wherein, Fig. 5 also shows a kind of cold MOS super-junction structure that obtains according to said method, comprise the N type epitaxial loayer 302 that is positioned on the N type semiconductor substrate 300, be etched with deep trench 304 on this N type epitaxial loayer 302, be deposited with heavily doped polysilicon 306 in the deep trench 304 and fill up this deep trench 304, deep trench 304 outsides are surrounded by the impurity diffusion zone 308 that is penetrated in the N type epitaxial loayer 302.
In the present embodiment, this N type semiconductor substrate 300 can be N type heavily-doped semiconductor substrate, more specifically can be N type heavily doped silicon substrate.And the width of deep trench 304 can be 0.4～3 μ m, and the degree of depth can be 10～80 μ m, and the angle between the N type epitaxial loayer 302 can be 80～90 degree.The heavily doped polysilicon 306 that is deposited in the deep trench 304 can be P type polysilicon, and the degree of depth 310 of impurity diffusion zone 308 then can be 0.5～5 μ m.
The present invention adopts deep plough groove etched technology to make the super-junction structure of cold MOS, avoided needing complicated technologies such as repeatedly photoetching, ion injection, propelling and epitaxial growth in the preparation of traditional super-junction structure, effectively reduce manufacturing cost, and the super-junction structure composition surface that has overcome traditional " sugarcoated haws " shape is inhomogeneous, and the shortcoming of electric leakage takes place when easily causing cold MOS device to work.The charge balance concept of the present invention by super knot both sides not only can improve the puncture voltage of power MOS (Metal Oxide Semiconductor) device effectively, significantly reduce conducting resistance, and technology is simple, controllability is good.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1. the manufacture method of a cold MOS super-junction structure comprises step:
The N type semiconductor substrate is provided;
On described N type semiconductor substrate, form N type epitaxial loayer;
On described N type epitaxial loayer, etch deep trench;
The heavily doped polysilicon of deposit fills up described deep trench in described deep trench;
Diffusion of impurities in the described heavily doped polysilicon in described N type epitaxial loayer, is formed impurity diffusion zone.
2. the manufacture method of super-junction structure according to claim 1 is characterized in that, described N type semiconductor substrate is a N type heavily-doped semiconductor substrate.
3. the manufacture method of super-junction structure according to claim 1 is characterized in that, the width of described deep trench is 0.4～3 μ m, and the degree of depth is 10～80 μ m, and the angle between the described N type epitaxial loayer is 80～90 degree.
4. the manufacture method of super-junction structure according to claim 1 is characterized in that, described heavily doped polysilicon is the P type.
5. the manufacture method of super-junction structure according to claim 1 is characterized in that, described diffusion of impurities is done down to advance to finish at 1000～2000 ℃.
6. the manufacture method of super-junction structure according to claim 1 is characterized in that, the degree of depth of described impurity diffusion zone is 0.5～5 μ m.
7. cold MOS super-junction structure, comprise the N type epitaxial loayer that is positioned on the N type semiconductor substrate, be etched with deep trench on the described N type epitaxial loayer, be deposited with heavily doped polysilicon in the described deep trench and fill up described deep trench, the described deep trench outside is surrounded by the impurity diffusion zone that is penetrated in the described N type epitaxial loayer.
8. super-junction structure according to claim 7 is characterized in that, described N type semiconductor substrate is a N type heavily-doped semiconductor substrate.
9. super-junction structure according to claim 7 is characterized in that, the width of described deep trench is 0.4～3 μ m, and the degree of depth is 10～80 μ m, and the angle between the described N type epitaxial loayer is 80～90 degree.
10. super-junction structure according to claim 7 is characterized in that, described heavily doped polysilicon is the P type.
11. super-junction structure according to claim 7 is characterized in that, the degree of depth of described impurity diffusion zone is 0.5～5 μ m.
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| CN104900697A (en) * | 2014-03-04 | 2015-09-09 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN104979382A (en) * | 2014-04-02 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN110416285A (en) * | 2019-07-31 | 2019-11-05 | 电子科技大学 | A kind of superjunction power DMOS device |
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Application publication date: 20110914 |