CN102171810A - 用于互连集成的非连续/非均匀金属帽盖结构及方法 - Google Patents
用于互连集成的非连续/非均匀金属帽盖结构及方法 Download PDFInfo
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Abstract
提供了一种互连结构,其包括含有贵金属的帽盖,所述帽盖至少存在于嵌入互连介电材料中的至少一个导电材料的上表面的某部分上。在一个实施例中,含有贵金属的帽盖是非连续的,例如,作为至少一个导电材料的上表面上的核或岛而存在。在另一实施例中,含有贵金属的帽盖具有跨至少一个导电材料的表面的非均匀厚度。
Description
技术领域
本发明涉及半导体互连结构及其制造方法。更具体地,本发明涉及具有改善的抗电迁徙(EM)能力且不会降低时间依赖介电击穿可靠性的半导体互连结构。
背景技术
一般而言,半导体器件包括多个电路,其形成在制造于半导体衬底上的集成电路(IC)上。复杂的信号路径网络一般经过路径规划以连接分布在衬底表面上的电路元件。在器件上对这些信号进行有效的路径规划需要形成多层级或多层方案,诸如,单镶嵌或双镶嵌布线结构。布线结构典型地包括铜(Cu),因为在复杂半导体芯片上大量的晶体管之间,基于Cu的互连传送信号的速度比基于铝(Al)的互连高。
在典型的互连结构内,金属过孔垂直于半导体衬底延伸且金属线平行于半导体衬底延伸。在现今的IC产品芯片中,将金属线及金属过孔(如,导电特征)嵌入介电常数小于4.0的介电材料中,可进一步提高信号速度并抑制邻进金属线的信号(称为“串扰”)。
在半导体互连结构中,将电迁徙(EM)视为一种金属故障机制。电迁徙是导体中因传导电子及扩散金属原子间的动量转移致使离子慢慢移动所造成的材料输送。此效应在诸如微电子器件及相关结构中使用高直流密度的应用中很重要。随着结构尺寸缩小,EM实际意义增加。
自19世纪60年代以来,对于超大规模集成(VLSI)电路及制造而言,EM是影响可靠性的最严重问题之一。该问题不仅在制程开发周期中要加以克服以确保制程合乎要求,更要在芯片寿命期间持续应对该问题。在互连结构的金属导体内部由于高密度电流流动所造成的金属离子移动会导致产生空隙。
虽然金属互连中的快速扩散路径因依赖于芯片制造所使用的整体集成方案和材料而有所不同,但已观察到沿着金属/后平坦化电介质帽盖界面输送的金属原子(诸如Cu原子)在EM寿命估计中扮演着重要的角色。EM初始空隙首先在金属/电介质帽盖界面处形成,然后向互连底部的方向扩展,最后导致电路失效断路。
图1A-1D为现有技术互连结构在EM故障不同阶段时的图式。在这些图式中,参考数字12代表电介质帽盖,及参考数字10代表金属互连特征;未对现有技术互连结构中所有其它元件标示参考数字,以免模糊EM问题的焦点。图1A属于初始应力阶段。图1B属于空隙14在金属互连特征10/电介质帽盖12之界面处开始形成时的阶段。图1C属于空隙14朝导电特征10的底部扩展时的阶段,及图1D属于空隙14扩展穿过金属互连特征10造成电路失效断路时的阶段。
已证实,以Cu/金属界面取代Cu/电介质界面可提高抗电迁徙能力超过100倍。现有技术金属帽盖通常由含有Co的合金(例如CoWP)组成,该合金被选择性沉积在互连结构的Cu导体区域的顶上。利用此类选择性沉积的金属帽盖的一个问题是,部分金属帽盖延伸至互连介电材料的邻接表面上,因而可能引起相邻互连间的电气短路。例如参见图2,其中参考数字20代表介电材料,参考数字22代表嵌入介电材料20的导电材料,参考数字24代表含有Co的合金金属帽盖,及参考数字25代表来自含有Co的合金帽盖制程的金属残余物。
除了上文以外,已知可使互连导电材料凹陷低于互连介电材料的表面,直接在互连导电材料(例如,Cu)的表面上提供金属帽盖。此种结构如图3所示。在该图中,参考数字20代表互连介电材料,参考数字22代表嵌入介电材料20的互连导电材料,参考数字23代表电介质帽盖,及参考数字24代表金属帽盖。虽然该现有技术凹陷制程提供了仅仅位于凹陷导电材料表面上的金属帽盖,但此种制程因相关的制程成本很高而具有问题。
另外值得一提的是,在稀氢氟酸(一般用来清洗互连介电材料的表面)中清洗期间,可能会腐蚀金属帽盖。在使用CoWP作为金属帽盖材料时,尤其可以观察到此现象。
有鉴于上文,因此持续需要提供一种改善抗EM能力且不会降低互连结构的时间依赖介电击穿可靠性的互连结构。
发明内容
本发明提供具有改善的EM可靠性的半导体互连结构。可在不降低互连结构的时间依赖介电击穿可靠性的情况下改善EM可靠性。本发明还提供了对于半导体产业具有较佳可靠性和技术可扩充性的互连结构。
在一个实施例中,本发明提供一种互连结构,其中非连续的含有贵金属的帽盖存在于非凹陷导电材料的暴露的上表面的部分上,该导电材料嵌入低k介电材料中。提及含有贵金属的帽盖时,术语“非连续”代表帽盖作为在非凹陷导电材料的暴露的上表面的某些部分的顶上的核(nuclei)或岛而存在。
在本发明的另一实施例中,提供一种互连结构,其包括存在于非凹陷导电材料的暴露上表面上的非均匀的含有贵金属的帽盖,所述导电材料嵌入低k介电材料中。提及含有贵金属的帽盖时,术语语“非均匀”代表帽盖具有由跨嵌入的导电材料的暴露上表面的变化的厚度所界定的粗糙源。
在上述两个实施例中,本发明的含有贵金属的帽盖不会延伸到低k介电材料的暴露的上表面上。优选地,本发明的含有贵金属的帽盖不会延伸到用于分隔导电材料与低k介电材料的扩散阻挡层的上表面上。其中本发明的含有贵金属的帽盖不会延伸到扩散阻挡层的上表面上的第二个实施例提供了一种相比于现有技术互连结构改善了泄漏控制的结构。
一般而言,本发明提供一种互连结构,包括:
介电材料,其具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料,所述至少一个导电材料具有与所述介电材料的上表面共面的上表面;以及
含有贵金属的帽盖,其至少存在于所述至少一个导电材料的所述上表面的某部分上,其中所述含有贵金属的帽盖是非连续的并具有非均匀的厚度。
在本发明的结构中,沉积到该电介质表面上的含有贵金属的帽盖没有任何“残余物”。“残余物”的意思是没有任何贵金属材料的碎片形成在介电材料的表面上。在一些实施例中,该含有贵金属的帽盖未出现在分隔该至少一个导电材料与该介电材料的扩散阻挡层的上表面上。
存在于本发明的互连结构中的介电材料可以是任何具有约3.0或更小的介电常数的互连介电材料。举例而言,本发明所用的介电材料包含倍半硅氧烷、包括至少Si、C、O及H的C掺杂的氧化物(即,有机硅酸盐)、热固化聚芳撑醚、或其多层。介电材料可为多孔、无孔或含有多孔的区域和/或表面以及无孔的其它区域和/或表面。
在互连结构内的形成嵌入的导电区域的导电材料包括任何能够转移电力的材料。可存在于导电区域中的导电材料实例包括例如:多晶Si、导电金属、导电金属合金、导电金属硅化物或其组合及其多层。在本发明的一个实施例中,导电材料包括导电金属,例如Cu、W、和/或Al。在本发明的一个高度优选的实施例中,导电材料包括含有Cu的导电材料,例如,Cu或Cu合金(诸如AlCu)。
如上所述,导电材料与介电材料被扩散阻挡层所分隔。扩散阻挡层防止导电材料扩散至介电材料中。可存在于导电区域内的扩散阻挡层的实例包括例如:Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、IrTa、IrTaN、W、WN或其组合及其多层。
导电材料可存在于过孔开口、线路开口、组合式过孔和线路开口或其任何组合内。
提及直接位于至少一个导电材料的顶上的帽盖时,术语“含有贵金属”包括任何抗腐蚀或抗氧化的金属。可在本发明中使用的优选的贵金属可选自由以下组成的群组:Ru、Ir、Rh、Pt、Co、W及其合金。更优选地,用作含有贵金属的帽盖的贵金属包括Ru或Ru合金。
除了上述互连结构之外,本发明还提供了其制造方法。一般而言,本发明的方法包括:
提供介电材料,所述介电材料具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料,所述至少一个导电材料具有与所述介电材料的上表面共面的上表面;以及
直接在所述至少一个导电材料的所述上表面上形成含有贵金属的帽盖,其中所述贵金属帽盖是非连续或非均匀的。
附图说明
图1A-1D为示例了现有技术互连结构中因EM故障而形成电路失效断路的图式(横截面图);
图2为现有技术互连结构(横截面图),其包括位于导电材料的顶上的含有Co的合金金属帽盖,导电材料被嵌入介电材料中,以及来自含有Co的合金帽盖制程的金属残余物出现在电介质表面上;
图3为现有技术互连结构(横截面图),其包括嵌入介电材料中的凹陷导电材料,该凹陷导电材料具有位在其上的金属帽盖层;
图4A-4E为图式(横截面图),其示例了可在本发明中形成的互连结构,该结构含有在嵌入介电材料中的导电材料的顶上的非连续的含有贵金属的帽盖。注意,图4B-4E为平行于在介电材料中形成的开口的横截面;以及
图5为图式(平行于在介电材料中形成的开口的横截面图),其示例了可在本发明中形成的备选互连结构,该结构含有在嵌入介电材料中的导电材料的顶上的非均匀的含有贵金属的帽盖。
具体实施方式
本发明提供具有改善的抗电迁徙(EM)能力且不降低时间依赖介电击穿可靠性的互连结构及其形成方法,现将通过参考以下论述及本申请的附图来详细说明。注意,本申请附图仅用于示例,因此,这些图式并未按比例绘制。
在以下说明中,提出许多具体细节,如特定结构、成分、材料、尺寸、处理步骤以及技术,以便全面了解本发明。然而,一般技术者应明白,在没有以上特定细节的情况下,也可实施本发明。在其它例子中,为了避免模糊本发明的焦点,并未说明所熟知的结构或处理步骤。
应明了,当表示一个元件(如层、区域或衬底)位于另一元件之“上”时,为表示直接位于其它元件的上面或可存有中间元件。反之,当表示一个元件“直接”位于另一元件上,便表示其间没有中间元件。另外应明白,当表示某元件为“连接”或“耦合”至另一元件时,该元件为直接连接或耦合至另一元件或可存有中间元件。反之,当表示一个元件“直接连接”或“直接耦合”至另一元件,便表示其间没有中间元件。
如上述,本发明提供一种互连结构(例如,见图4E及图5),其包括具有约3.0或更小的介电常数且具有嵌入其中的至少一个导电材料的介电材料。至少一个导电材料具有与介电材料的上表面共面的上表面。本发明的互连结构还包括含有贵金属的帽盖,其至少位于至少一个导电材料的上表面的某个部分上。在一个实施例中,含有贵金属的帽盖是非连续的,如,作为至少一个导电材料的上表面上的核或岛而存在。在另一具体实施例中,含有贵金属的帽盖具有跨至少一个导电材料的表面的非均匀厚度。
在本发明结构中,沉积在该电介质表面上的含有贵金属的帽盖没有任何“残余物”。“残余物”的意思是没有任何贵金属材料的碎片形成在介电材料的表面上。在一些实施例中,该含有贵金属的帽盖未出现在分隔该至少一个导电材料与该介电材料的扩散阻挡层的上表面上。
本发明还提供了一种制造互连结构的方法,该结构包括非连续/非均匀的含有贵金属的帽盖。一般而言,本发明的方法,例如在图4A-4E中所示,包括提供具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料的介电材料。该至少一个导电材料具有与介电材料的上表面共面的上表面。接下来,直接在至少一个导电材料的上表面上,形成含有贵金属的帽盖。含有贵金属的帽盖可以是具有粗糙表面的非连续帽盖或非均匀帽盖。
具体而言,图4A示例了本发明在制造本发明互连结构时所采用的初始结构50。初始结构50包括介电材料52,其具有位在其上表面上的衬垫叠层54。
注意,初始结构50通常位于衬底(未在本申请的图式中显示)上。衬底可包含半导体材料、绝缘材料、导电材料或包括其多层的任何组合。在衬底由半导体材料构成时,可使用任何半导体,诸如Si、SiGe、SiGeC、SiC、Ge合金、GaAs、InAs、InP以及其它III/V或II/VI化合物半导体。除了所列出的这些半导体材料类型,本发明还构思半导体衬底为分层半导体的情况,分层半导体诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗(SGOI)。
当衬底为绝缘材料时,该绝缘材料可以是有机绝缘体、无机绝缘体或其包括多层的组合。当衬底为导电材料时,此衬底可包括例如:多晶Si、元素金属、元素金属的合金、金属硅化物、金属氮化物或其包括多层的组合。当衬底包含半导体材料时,可在其上制造一个或多个半导体器件,诸如互补金属氧化物半导体(CMOS)器件。
当衬底包含绝缘材料和导电材料的组合时,衬底可代表多层互连结构的第一互连层级。
初始结构50的介电材料52包含任何层间或层内电介质,其包括无机电介质或有机电介质。介电材料52可为多孔、无孔或含有多孔的区域和/或表面以及无孔的其它区域和/或表面。可用作介电材料52的合适电介质的一些实例包括但不限于:倍半硅氧烷、包括Si、C、O以及H的原子的C掺杂的氧化物(即,有机硅酸盐)、热固化聚芳撑醚、或其多层。在本申请中使用的术语“聚芳撑(polyarylene)”代表通过化学键、稠环、或例如氧、硫、砜、亚砜、羰基等的惰性链接基团链接在一起的芳基部分或惰性替代的芳基部分。
介电材料52典型地具有约3.0或更小的介电常数,其中介电常数约2.8或更小较为典型。除非另外指明,本文所提到的所有介电常数为相对于真空。与具有介电常数高于4.0的介电材料相比,这些电介质一般具有较低的寄生串扰。介电材料52的厚度可根据使用的介电材料以及在介电材料52内的电介质层的确切数目而有所变化。典型地,并对于一般互连结构而言,介电材料52具有在50nm至1000nm之间的厚度。
介电材料52可利用任何常规沉积方法形成,包括但不限于:气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、蒸镀、化学溶液沉积以及旋涂。
在形成介电材料52后,在介电材料52的暴露上表面上形成衬垫叠层54。衬垫叠层54包括氧化物、氮化物、氮氧化物或其多层(如,包括衬垫氧化物和衬垫氮化物的衬垫叠层)。衬垫叠层54典型地包括半导体氧化物、半导体氮化物及和/或半导体氮氧化物。优选地,衬垫叠层54包含硅的氧化物和/或硅的氮化物。
在一些实施例中,衬垫叠层54可利用任何常规沉积方法形成,包括例如:CVD、PECVD、蒸镀、化学溶液沉积、物理气相沉积(PVD)以及原子层沉积(ALD)。在其它实施例中,衬垫叠层54通过热制程形成,例如,热氧化、热氮化和/或热氮氧化制程。在另外的其它具体实施例中,利用沉积和热制程的组合形成衬垫叠层54。
衬垫叠层54的厚度可根据衬垫叠层内的材料数目以及形成衬垫叠层时使用的技术而有所变化。典型地,衬垫叠层54具有在10nm至80nm的厚度。
在形成图4A所示的初始结构50后,利用衬垫叠层54作为图形掩模,在介电材料52中形成至少一个开口56。例如,在图4B中示出了包括至少一个开口56的所形成结构。至少一个开口56可包括过孔开口、线路开口、组合的过孔和线路开口、或其任何组合。在附图中,以非限制性实例的方式示出了线路开口。
利用常规光刻和蚀刻形成至少一个开口56。光刻步骤包括利用常规沉积制程,例如,CVD、PECVD及旋涂,在衬垫叠层54的顶上形成光致抗蚀剂(有机、无机或混合)。在形成光致抗蚀剂后,使光致抗蚀剂曝光于所要的辐射图形。接着,利用常规抗蚀剂显影制程,显影经曝光的光致抗蚀剂。
在显影步骤后,执行蚀刻步骤,将构图的光致抗蚀剂的图形首先转印至衬垫叠层54,然后再转印至介电材料52。在将图形转印至衬垫叠层54后,典型地利用常规光致抗蚀剂剥离制程,例如,灰化,自结构表面去除构图的光致抗蚀剂。形成至少一个开口56时使用的蚀刻步骤包括干法蚀刻制程(包括反应性离子蚀刻、离子束蚀刻、等离子体蚀刻或激光烧蚀)、湿法化学蚀刻制程或其任何组合。典型地,使用反应性离子蚀刻形成至少一个开口56。
接下来,并如图4C所示,在至少一个开口56中的每一个中形成扩散阻挡层58和导电材料60。扩散阻挡层58包括Ta、TaN、Ti、TiN、Ru、RuN、RuTa、RuTaN、IrTa、IrTaN、W、WN或任何其它可用作阻挡层以防止导电材料从中扩散的材料。扩散阻挡层58的厚度可根据使用的沉积制程以及采用的材料而有所变化。通常,扩散阻挡层58具有的厚度为4nm至40nm,更典型地,厚度为7nm至20nm。
扩散阻挡层58位于在导电材料60与介电材料52之间,可利用任何常规沉积制程形成,包括例如:CVD、PECVD、PVD、溅镀以及镀敷。
形成互连结构的导电区域所使用的导电材料60包括例如:多晶Si、导电金属、包含至少一个导电金属的合金、导电金属硅化物或其组合。优选地,形成导电区域时所使用的导电材料60为导电金属,诸如Cu、W或Al,其中Cu或Cu合金(诸如AlCu)在本发明中是高度优选的。
利用任何常规的沉积制程,包括例如CVD、PECVD、PVD、溅镀、镀敷、化学溶液沉积及无电镀敷,在每一个衬有扩散阻挡层58的开口56中形成导电材料60。在沉积导电材料60后,对结构进行平坦化制程,例如,化学机械抛光(CMP)和/或研磨。平坦化制程提供诸如图4C中显示的平面结构,其中介电材料52、扩散阻挡层58(现为U形)以及导电材料60的上表面大体上彼此共面。注意,在平坦化制程期间,自结构中去除剩余的衬垫叠层54。
接着,并如图4D所示,基本上在导电材料60的顶上选择性地形成非连续的含有贵金属的帽盖62。在提及实质上位于至少一个导电区域(即,导电材料60)的顶上的非连续的贵金属帽盖62时,术语“含有贵金属”包括任何抗腐蚀或抗氧化的金属。在提及非连续的含有贵金属的帽盖62时,本文使用的术语“实质上”表示没有任何帽盖部分延伸至介电材料的表面上。优选地,帽盖62没有任何部分延伸至扩散阻挡层上。
在本发明中可用作非连续的含有贵金属的帽盖62的优选贵金属可选自由以下组成的群组:Ru、Ir、Rh、Pt、Co、W及其合金。使用术语“合金”代表贵金属以及诸如W、B及P等元素的混合物。更优选地,用作非连续的含有贵金属的帽盖62的贵金属包括Ru或Ru合金。在一些实施例中,非连续的含有贵金属的帽盖62包括多层贵金属或贵金属合金叠层。
在本发明的一些实施例中,非连续的含有金属的帽盖62利用化学沉积制程形成,包括例如CVD、PECVD及ALD。在形成非连续的含有贵金属的帽盖62时使用化学沉积制程时,通过控制沉积时间、沉积压力以及沉积温度中的至少一个,达成帽盖的非连续性。
具体而言,申请人确定为获得如上述的非连续的含有贵金属的帽盖,可使用以下沉积参数中的至少一个来进行化学沉积:沉积时间小于3分钟,优选0.1分钟至2分钟,以及更优选0.5分钟至1分钟。沉积压力50mTorr或更小,优选20mTorr或更小,以及更优选5mTorr至20mTorr。沉积温度300℃或更小,优选200℃或更小,以及更优选150℃至200℃。在本发明的高度优选实施例中,可利用150℃至200℃的温度和5Torr至20Torr的压力以及小于1分钟的持续时间的化学沉积,获得非连续的含有贵金属的帽盖62。
除了化学沉积之外,还可以利用无电镀敷或电镀敷,形成非连续的含有贵金属的帽盖62。镀敷制程使用电流从溶液中还原希望的材料(例如,贵金属)的阳离子,然后以材料(如,贵金属)的薄层涂布导电物体(例如,至少一个导电材料)。在无电镀敷中,氧化还原反应发生在衬底表面(例如,至少一个导电材料)上,其涉及氧化一种或多种可溶解还原剂(例如,次磷酸盐),以及还原一种或多种金属离子(如,贵金属离子)。
在形成非连续帽盖中使用镀敷技术时,要达成帽盖中的非连续性,可执行镀敷制程持续时间小于3分钟,优选0.1分钟至2分钟,以及更优选0.5分钟至1分钟。在此实施例中,镀敷温度及压力与控制帽盖62的非连续性无关。
除了上述技术,非连续的含有贵金属的帽盖62可利用以下方式形成:首先跨至少一个导电材料的整个表面形成连续的含有贵金属的帽盖;部分贵金属帽盖可延伸至扩散阻挡层的上表面上,但没有延伸至介电材料上。此沉积通过利用低温化学沉积制程达成,包括例如:CVD、PECVD、低压CVD及ALD。“低温”的意思是沉积温度约200℃或更小,且沉积温度小于约150℃是优选的。选择沉积条件以提供在导电材料60上沉积连续的含有贵金属的帽盖的0.2至/sec的沉积速率。
在形成连续的含有贵金属的帽盖后,选择性地去除连续的含有贵金属的帽盖的若干部分,以形成非连续的含有贵金属的帽盖,如上所述。通过首先在结构的若干部分(包括连续的含有贵金属的帽盖的若干部分)上形成构图的掩模或阻挡掩模,进行选择性去除。接着,可以使用选择性蚀刻制程,其包括例如干法蚀刻或湿法化学蚀刻。使用干法蚀刻时,可以使用反应性离子蚀刻、离子束蚀刻、等离子体蚀刻以及激光烧蚀中的一种。使用湿法化学蚀刻时,可以使用HCl、H2SO4、HF以及HNO3的混合物作为化学蚀刻剂。在又一实施例中,可使用修饰化学机械抛光(touch-up CMP)制程,达成选择性去除。“修饰CMP”的意思是简短的、小于1分钟、以及非均匀的CMP制程。
主要在导电材料60上选择性性地形成非连续的含有贵金属的帽盖62后,在图4D示出的整个结构上形成介电帽盖层64。所形成的包括介电帽盖层64的结构如图4E所示的。介电帽盖层64包括任何适宜的介电帽盖材料,诸如,SiC、Si4NH3、SiO2、碳掺杂的氧化物、氮以及氢掺杂的碳化硅SiC(N,H)或其多层。
介电帽盖层64的厚度可根据形成帽盖层所使用的技术以及组成该层的材料而有所变化。通常,介电帽盖层64具有的厚度为15nm至100nm,以且优选地厚度为25nm至45nm。
利用任何常规的沉积制程,包括例如:CVD、PECVD、蒸镀、旋涂以及化学溶液沉积,形成介电帽盖层64。
图4E示例了根据本发明的实施例的互连结构。具体而言,本发明的互连结构包括具有约3.0或更小的介电常数的介电材料52。介电材料52具有嵌入介电材料52中的至少一个导电区域(以导电材料60代表),该至少一个导电区域具有上表面。非连续的贵金属帽盖62直接位于至少一个导电区域(即,导电材料60)的上表面上。
图5示例了可在本发明中采用的备选互连结构。图5的备选互连结构与图4E示出的互连结构实质上相同,只是以具有粗糙表面的贵金属帽盖(其特征为跨至少一个导电材料的整个表面具有变化的厚度)取代非连续的含有贵金属的帽盖62。在备选互连结构中,使用参考数字62′代表“非均匀的”含有贵金属的帽盖。非均匀的含有贵金属的帽盖62′基本上利用与上述相同的化学沉积技术以及材料形成。上述确保非均匀的含有贵金属的帽盖62′的化学沉积技术间的一个差异是使用较长的制程时间。例如,非均匀的含有贵金属的帽盖62′可使用以下沉积时间形成:小于5分钟,优选0.5至3分钟,以及更优选1分钟至2分钟。
无论是否形成非连续或非均匀的含有贵金属的帽盖,申请人确定的是在嵌入互连电介质中的导电材料的顶上出现非连续的含有贵金属的帽盖或非均匀的含有贵金属的帽盖均可改善互连结构的抗EM能力。在现有技术的互连结构中,使用连续的含有贵金属的帽盖,且其被视为是改善EM的理想帽盖设计。除了改善EM之外,申请人确定的是在嵌入互连电介质中的导电材料的顶上出现非连续的含有贵金属的帽盖或非均匀的含有贵金属的帽盖,还可以改善互连结构的时间依赖介电击穿(TDDB)可靠性。在采用连续的含有贵金属的帽盖时,无法观察到这样的TDDB可靠性的改善。
虽然已经参考优选实施例详细说明了本发明,但本领域的技术人员应明白,可在不脱离本发明的精神和范围的情况下,进行上述以及其它形式和细节的改变。因此,本发明的目的并不限于所描述和示例的确切形式及细节,而应以随附权利要求的范围为主。
Claims (25)
1.一种互连结构,其包括:
介电材料,其具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料,所述至少一个导电材料具有与所述介电材料的上表面共面的上表面;以及
非连续的含有贵金属的帽盖,其至少存在于所述至少一个导电材料的所述上表面的某部分上。
2.根据权利要求1所述的互连结构,其中所述非连续的含有贵金属的帽盖选自:Ru、Ir、Rh、Pt、Co、W及其合金。
3.根据权利要求2所述的互连结构,其中所述非连续的含有贵金属的帽盖包括Ru或Ru合金。
4.根据权利要求1所述的互连结构,还包括位于所述介电材料和所述非连续的含有贵金属的帽盖的顶上的介电帽盖层。
5.根据权利要求4所述的互连结构,其中所述介电帽盖层包括:SiC、Si4NH3、SiO2、碳掺杂的氧化物、氮和氢掺杂的碳化硅SiC(N,H)或其多层。
6.根据权利要求1所述的互连结构,其中所述至少一个导电材料包括多晶Si、导电金属、导电金属合金、导电金属硅化物或其组合及其多层。
7.根据权利要求6所述的互连结构,其中所述至少一个导电材料为选自Cu、W以及Al中的一种的导电金属。
8.根据权利要求1所述的互连结构,其中所述介电材料包括倍半硅氧烷、包括至少Si、C、O以及H的原子的C掺杂的氧化物、热固化聚芳撑醚或其多层。
9.一种互连结构,其包括:
介电材料,其具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料,所述至少一个导电材料具有与所述介电材料的上表面共面的上表面;以及
含有贵金属的帽盖,其存在于所述至少一个导电材料的所述上表面上,所述含有贵金属的帽盖具有非均匀的厚度。
10.根据权利要求9所述的互连结构,其中所述含有贵金属的帽盖选自:Ru、Ir、Rh、Pt、Co、W及其合金。
11.根据权利要求10所述的互连结构,其中所述含有贵金属的帽盖包括Ru或Ru合金。
12.根据权利要求9所述的互连结构,还包括位于所述介电材料和所述含有贵金属的帽盖的顶上的介电帽盖层。
13.根据权利要求12所述的互连结构,其中所述介电帽盖层包括:SiC、Si4NH3、SiO2、碳掺杂的氧化物、氮和氢掺杂的碳化硅SiC(N,H)或其多层。
14.根据权利要求9所述的互连结构,其中所述至少一个导电材料包括多晶Si、导电金属、导电金属合金、导电金属硅化物或其组合及其多层。
15.根据权利要求14所述的互连结构,其中所述至少一个导电材料为选自Cu、W以及Al中的一种的导电金属。
16.根据权利要求9所述的互连结构,其中所述介电材料包括倍半硅氧烷、包括至少Si、C、O以及H的原子的C掺杂的氧化物、热固化聚芳撑醚或其多层。
17.一种制造互连结构的方法,其包括:
提供介电材料,所述介电材料具有约3.0或更小的介电常数和嵌入其中的至少一个导电材料,所述至少一个导电材料具有与所述介电材料的上表面共面的上表面;以及
直接在所述至少一个导电材料的所述上表面上形成含有贵金属的帽盖,其中所述贵金属帽盖是非连续或非均匀的。
18.根据权利要求17所述的方法,其中形成所述含有贵金属的帽盖可选自由以下组成的群组:化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD)、无电镀敷以及电镀敷。
19.根据权利要求18所述的方法,其中形成所述含有贵金属的帽盖包括CVD、PECVD、ALD中的一种,以及使用以下沉积参数中的至少一个进行所述沉积:沉积时间小于3分钟、沉积压力50mTorr或更小以及沉积温度300℃或更小。
20.根据权利要求19所述的方法,其中以150℃至200℃的温度和5mTorr至20mTorr的压力以及小于1分钟的持续时间进行所述沉积。
21.根据权利要求17所述的方法,其中形成所述含有贵金属的帽盖包括首先利用约200℃或更小的化学沉积温度,跨所述至少一个导电材料的整个上表面形成连续的含有贵金属的帽盖;以及选择性地去除所述连续的含有贵金属的帽盖的部分,以形成所述非连续的含有贵金属的帽盖。
22.根据权利要求21所述的方法,其中选择性地去除包括提供构图的掩模或阻挡掩模以及进行蚀刻。
23.根据权利要求21所述的方法,其中选择性去除包括修饰化学机械抛光制程。
24.根据权利要求17所述的方法,还包括在所述介电材料和所述含有贵金属的帽盖的顶上形成介电帽盖层。
25.根据权利要求17所述的方法,其中所述含有贵金属的帽盖是非连续的。
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US8211776B2 (en) | 2010-01-05 | 2012-07-03 | International Business Machines Corporation | Integrated circuit line with electromigration barriers |
US8796853B2 (en) | 2012-02-24 | 2014-08-05 | International Business Machines Corporation | Metallic capped interconnect structure with high electromigration resistance and low resistivity |
US9076847B2 (en) | 2013-01-18 | 2015-07-07 | International Business Machines Corporation | Selective local metal cap layer formation for improved electromigration behavior |
US9123726B2 (en) | 2013-01-18 | 2015-09-01 | International Business Machines Corporation | Selective local metal cap layer formation for improved electromigration behavior |
US8962479B2 (en) * | 2013-05-10 | 2015-02-24 | International Business Machines Corporation | Interconnect structures containing nitrided metallic residues |
US8906799B1 (en) | 2013-07-29 | 2014-12-09 | International Business Machines Corporation | Random local metal cap layer formation for improved integrated circuit reliability |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
US20040224500A1 (en) * | 2003-05-09 | 2004-11-11 | Ihl Hyun Cho | Method of forming metal line of semiconductor device |
US6821909B2 (en) * | 2002-10-30 | 2004-11-23 | Applied Materials, Inc. | Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application |
US20060131751A1 (en) * | 2004-12-21 | 2006-06-22 | Gaku Minamihaba | Semiconductor device and method for manufacturing the same |
US20080197499A1 (en) * | 2007-02-15 | 2008-08-21 | International Business Machines Corporation | Structure for metal cap applications |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5300813A (en) | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
US5695810A (en) | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
CN1329972C (zh) * | 2001-08-13 | 2007-08-01 | 株式会社荏原制作所 | 半导体器件及其制造方法 |
US7404985B2 (en) | 2002-06-04 | 2008-07-29 | Applied Materials, Inc. | Noble metal layer formation for copper film deposition |
US7279423B2 (en) * | 2002-10-31 | 2007-10-09 | Intel Corporation | Forming a copper diffusion barrier |
US6706625B1 (en) | 2002-12-06 | 2004-03-16 | Chartered Semiconductor Manufacturing Ltd. | Copper recess formation using chemical process for fabricating barrier cap for lines and vias |
US6975032B2 (en) | 2002-12-16 | 2005-12-13 | International Business Machines Corporation | Copper recess process with application to selective capping and electroless plating |
US6955984B2 (en) * | 2003-05-16 | 2005-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface treatment of metal interconnect lines |
US20040262772A1 (en) * | 2003-06-30 | 2004-12-30 | Shriram Ramanathan | Methods for bonding wafers using a metal interlayer |
US7008871B2 (en) | 2003-07-03 | 2006-03-07 | International Business Machines Corporation | Selective capping of copper wiring |
US7074719B2 (en) | 2003-11-28 | 2006-07-11 | International Business Machines Corporation | ALD deposition of ruthenium |
US7170050B2 (en) | 2004-09-17 | 2007-01-30 | Pacific Biosciences Of California, Inc. | Apparatus and methods for optical analysis of molecules |
US20060068588A1 (en) | 2004-09-30 | 2006-03-30 | Tokyo Electron Limited | Low-pressure deposition of ruthenium and rhenium metal layers from metal carbonyl precursors |
US7476618B2 (en) | 2004-10-26 | 2009-01-13 | Asm Japan K.K. | Selective formation of metal layers in an integrated circuit |
US20060205204A1 (en) | 2005-03-14 | 2006-09-14 | Michael Beck | Method of making a semiconductor interconnect with a metal cap |
US7935631B2 (en) | 2005-07-04 | 2011-05-03 | Freescale Semiconductor, Inc. | Method of forming a continuous layer of a first metal selectively on a second metal and an integrated circuit formed from the method |
JP2007035734A (ja) | 2005-07-25 | 2007-02-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7446034B2 (en) | 2005-10-06 | 2008-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for making a metal seed layer |
US7435674B2 (en) | 2006-03-27 | 2008-10-14 | International Business Machines Corporation | Dielectric interconnect structures and methods for forming the same |
US20080054466A1 (en) * | 2006-08-31 | 2008-03-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
JP2008172051A (ja) * | 2007-01-12 | 2008-07-24 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7776740B2 (en) * | 2008-01-22 | 2010-08-17 | Tokyo Electron Limited | Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device |
US7737528B2 (en) * | 2008-06-03 | 2010-06-15 | International Business Machines Corporation | Structure and method of forming electrically blown metal fuses for integrated circuits |
-
2008
- 2008-10-08 US US12/247,632 patent/US8823176B2/en active Active
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- 2009-07-21 CN CN2009801388986A patent/CN102171810A/zh active Pending
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
US6821909B2 (en) * | 2002-10-30 | 2004-11-23 | Applied Materials, Inc. | Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application |
US20040224500A1 (en) * | 2003-05-09 | 2004-11-11 | Ihl Hyun Cho | Method of forming metal line of semiconductor device |
US20060131751A1 (en) * | 2004-12-21 | 2006-06-22 | Gaku Minamihaba | Semiconductor device and method for manufacturing the same |
US20080197499A1 (en) * | 2007-02-15 | 2008-08-21 | International Business Machines Corporation | Structure for metal cap applications |
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KR20110083636A (ko) | 2011-07-20 |
US8823176B2 (en) | 2014-09-02 |
US20100084767A1 (en) | 2010-04-08 |
US8889546B2 (en) | 2014-11-18 |
EP2342743A1 (en) | 2011-07-13 |
TW201027684A (en) | 2010-07-16 |
SG188903A1 (en) | 2013-04-30 |
US20120329271A1 (en) | 2012-12-27 |
WO2010042265A1 (en) | 2010-04-15 |
BRPI0914051A2 (pt) | 2015-11-03 |
EP2342743A4 (en) | 2012-05-16 |
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