CN102169888B - Strain geoi structure and forming method thereof - Google Patents
Strain geoi structure and forming method thereof Download PDFInfo
- Publication number
- CN102169888B CN102169888B CN2011100583707A CN201110058370A CN102169888B CN 102169888 B CN102169888 B CN 102169888B CN 2011100583707 A CN2011100583707 A CN 2011100583707A CN 201110058370 A CN201110058370 A CN 201110058370A CN 102169888 B CN102169888 B CN 102169888B
- Authority
- CN
- China
- Prior art keywords
- layer
- thin layer
- strain
- passivation
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention provides a strain GeOI structure which comprises a silicon substrate with an oxide insulating layer on a surface; a Ge layer formed on the oxide insulating layer, wherein a first passivation thin layer is formed between the Ge layer and the oxide insulating layer; a gate stack is formed on the Ge layer, and a channel region formed below the gate stack, and drain region and a source region formed at both sides of the channel region; and a SiN strain cap layer for covering the gate stack to enable the channel region to produce strain. The passivation thin layer formed by strontium germanide or barium germanide in the invention embodiment belongs to the semiconductor; an interface state problem between the Ge material and the insulating oxide can be improved through a first passivation layer so as to reduce the electric leakage and scattering at the interface. Furthermore, the SiN strain cap layer enables the channel region to produce strain so as to improve the performance of the appliance.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of strain GeOI (ge-on-insulator) structure and forming method thereof.
Background technology
For a long time; It is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' s law) always; Its operating rate is more and more faster; But,, approached the physics and the technological dual limit for for Si material itself.Thereby people have proposed various methods for the performance that constantly promotes the MOSFET device, thereby the development of MOSFET device has got into so-called back mole (More-Than-Moore) epoch.High mobility raceway groove engineering based on high carrier mobility material systems such as dissimilar materials structure especially Si base Ge materials is an a kind of fruitful technology wherein.For example, it is exactly a kind of Si base Ge material with high hole mobility that Ge is formed the GeOI structure with the Si sheet Direct Bonding with SiO2 insulating barrier, has good application prospects.
Existing GeOI structure is with Ge and SiO
2Deng the insulation oxide Direct Bonding, perhaps be formed with GeO on the Ge
2Again with wafer bonding.The shortcoming that prior art exists is; If in the GeOI technology, directly on the insulation oxide substrate, form the Ge material; Because the contact interface between Ge material and the insulation oxide is poor; Especially interface state density is very high, thereby causes more serious scattering and electric leakage, has finally influenced device performance.In addition, because the Ge layer is extremely thin, so the Ge layer is difficult to form strain.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, particularly solve in the present GeOI structure the very poor defective of interfacial state between the Ge and oxide-insulator, and the Ge layer is difficult to form the defective of strain.
For achieving the above object, one aspect of the present invention proposes a kind of strain GeOI structure, and comprising: the surface has the silicon substrate of oxide insulating layer; Be formed on the Ge layer on the said oxide insulating layer, wherein, be formed with the first passivation thin layer between said Ge layer and the said oxide insulating layer; The grid that are formed on the said Ge layer pile up, and are formed on channel region and drain region and the source region of channel region both sides of said grid under piling up; With cover SiN stress cap layer that said grid pile up so that said channel region produces strain.
In one embodiment of the invention, said grid pile up and comprise: be positioned at the gate dielectric layer on the said Ge layer; Be positioned at the gate electrode on the said gate dielectric layer; With the side wall that is positioned at said gate dielectric layer and said gate electrode both sides, wherein, the height of said side wall be said gate electrode height 0.5-0.8 doubly.
In one embodiment of the invention, the said first passivation thin layer is strontium germanide thin layer, barium germanide thin layer, GeSi passivation thin layer or Si thin layer.
In one embodiment of the invention, also comprise: be formed on the second passivation thin layer on the said Ge layer, the said second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
In one embodiment of the invention, link to each other through the bonding mode between said oxide insulating layer and the said Ge layer.
The present invention has also proposed a kind of formation method of strain GeOI structure on the other hand, may further comprise the steps: on first substrate, form the Ge layer; The first surface of said Ge layer is handled to form the first passivation thin layer; With said first substrate, said Ge layer and the upset of the said first passivation thin layer and be transferred to the silicon substrate that there is oxide insulating layer on the surface; Remove said first substrate; The grid that formation is positioned on the said Ge layer pile up, and form and to be positioned at said grid and to form channel region under piling up, and the drain region and the source region that are positioned at said channel region both sides; With pile up at said grid on form to cover SiN stress cap layer that said grid pile up so that said channel region produces strain.
In one embodiment of the invention, said piling up further at formation grid on the Ge layer comprises: on said Ge layer, form gate dielectric layer; On said gate dielectric layer, form gate electrode; Form side wall at said gate dielectric layer and said gate electrode both sides; The said side wall of etching so that the height of said side wall be said gate electrode height 0.5-0.8 doubly.
In one embodiment of the invention, the said first passivation thin layer is strontium germanide thin layer, barium germanide thin layer, GeSi passivation thin layer or Si thin layer.
In one embodiment of the invention; After said removal first substrate; Also comprise: the second surface of said Ge layer is handled to form the second passivation thin layer, and the said second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
In one embodiment of the invention, after said removal first substrate, also comprise: the second surface to said Ge layer carries out silicidation to form GeSi passivation thin layer.
In one embodiment of the invention, through the bonding mode the said first passivation thin layer is linked to each other with said oxide insulating layer.
Can improve the interfacial state problem between Ge material and the insulation oxide through first passivation layer in embodiments of the present invention, thereby reduce this electric leakage and scattering at the interface.In the preferred embodiment of the present invention; The passivation thin layer that strontium germanide or barium germanide or GeSi form belongs to semiconductor; Therefore not only can improve the interfacial state problem between Ge material and the insulation oxide; Reduce this electric leakage and scattering at the interface, also can excessively not reduce the mobility performance of Ge material in addition.In addition, the SiN stress cap layer through the embodiment of the invention can make channel region produce strain, thereby improves device performance.In effective embodiment of the present invention, when the height of side wall was 0.5-0.8 times of height of gate electrode, the stress of SiN stress cap layer can more effectively be delivered to channel region, thereby more effectively improves device performance.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the sketch map of the strain GeOI structure of the embodiment of the invention;
Fig. 2-6 is the intermediate steps sketch map of formation method of the strain GeOI structure of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
As shown in Figure 1, be the sketch map of the strain GeOI structure of the embodiment of the invention.This GeOI structure comprises that there is the silicon substrate 1100 of oxide insulating layer 1200 on the surface and is formed on the Ge layer 1300 on the oxide insulating layer 1200, wherein, is formed with the first passivation thin layer 1400 between Ge layer 1300 and the oxide insulating layer 1200.In embodiments of the present invention, the first passivation thin layer 1300 is strontium germanide GeSr for adopting strontium Sr or barium Ba to what the first surface of Ge layer 1200 was handled formation
xOr barium germanide GeBa
xCertainly in other embodiments of the invention, the first passivation thin layer 1400 also can be GeSi passivation thin layer or Si thin layer.In one embodiment of the invention, the surface has the silicon substrate 1100 of oxide insulating layer to comprise the Si substrate, and is formed on the SiO on the Si substrate
2Insulating barrier.Because the passivation thin layer that strontium germanide or barium germanide form belongs to semiconductor; Therefore not only can improve the interfacial state problem between Ge material and the insulation oxide; Reduce this electric leakage and scattering at the interface, also can excessively not reduce the mobility performance of Ge material in addition.In embodiments of the present invention, in order to generate the Ge channel device with strain, this strain GeOI structure also is included in grid and forms covering gate on piling up and pile up the SiN stress cap layer 1900 of (gate dielectric layer 1600 and gate electrode 1700) so that channel region produces strain.In embodiments of the present invention, can make channel region produce compressive strain or tensile strain through the component of regulating N in the SiN stress cap layer 1900, thereby improve device performance.
In one embodiment of the invention, this strain GeOI structure also comprises the second passivation thin layer 1500 that is formed on the said Ge layer.Wherein, likewise, the second passivation thin layer 1500 adopts strontium Sr or barium Ba to be strontium germanide or barium germanide to what the second surface of Ge layer 1400 was handled formation.Certainly in other embodiments of the invention, also can form the second passivation thin layer 1500 through other modes, promptly this second passivation thin layer 1500 is GeSi.
In one embodiment of the invention, this GeOI structure also comprises the gate dielectric layer 1600 that is formed on the second passivation thin layer 1500 and is formed on the gate electrode 1700 on the gate dielectric layer 1600, and is formed on the source electrode and drain electrode 1800 among the Ge layer 1400.
Shown in Fig. 2-6, be the intermediate steps sketch map of the formation method of the strain GeOI structure of the embodiment of the invention.This method may further comprise the steps:
Step S101 provides first substrate 2000, and wherein, first substrate 2000 is Si substrate or Ge substrate.Certainly in other embodiments of the invention, also can adopt other substrates.First substrate 2000 is reusable in embodiments of the present invention, thereby reduces manufacturing cost.
Step S102 forms Ge layer 1300 on first substrate 2000, as shown in Figure 2.
Step S103 adopts strontium Sr or barium Ba that the first surface of Ge layer 1300 is handled to form the first passivation thin layer 1400, and this first passivation thin layer 1400 is strontium germanide or barium germanide, and is as shown in Figure 3.Certainly in other embodiments of the invention, the first passivation thin layer 1400 also can be GeSi passivation thin layer or Si thin layer, for example Ge layer 1300 is carried out the Siization processing, perhaps deposit Si thin layer on Ge layer 1300.
Step S104, with first substrate 2000, Ge layer 1300 and 1400 upsets of the first passivation thin layer and be transferred to the silicon substrate 1100 that there is oxide insulating layer 1200 on the surface, as shown in Figure 4.In one embodiment of the invention, through the bonding mode the first passivation thin layer 1300 is linked to each other with oxide insulating layer 1200.
Step S105 removes first substrate 2000, and is as shown in Figure 5.
Step S106 selectively, adopts strontium or barium that the second surface of Ge layer 1400 is handled to form the second passivation thin layer 1500, and this second passivation thin layer 1500 is strontium germanide or barium germanide, and is as shown in Figure 6.Likewise, in other embodiments of the invention, also can form the second passivation thin layer 1500 through other modes, promptly this second passivation thin layer 1500 is GeSi.
Step S107 forms that the grid be positioned on the second passivation thin layer 1500 pile up (being gate dielectric layer 1600 and gate electrode 1700) and grid pile up the side wall of both sides, and forms and be positioned at grid and form channel region under piling up, and the drain region and the source region 1800 that are positioned at the channel region both sides.。In an embodiment of the present invention, grid pile up and the formation in source region and drain region both can have been adopted preceding grid (gate-first) technology, also can adopt back grid (gate-last) technology.
In a preferred embodiment of the invention, also can carry out etching, make its 0.5-0.8 that highly is about gate height doubly side wall.
Step S108, deposit SiN layer, and carry out etching to form SiN stress cap layer 1900, as shown in Figure 1.
Can improve the interfacial state problem between Ge material and the insulation oxide through first passivation layer in embodiments of the present invention, thereby reduce this electric leakage and scattering at the interface.In the preferred embodiment of the present invention; The passivation thin layer that strontium germanide or barium germanide form belongs to semiconductor; Therefore not only can improve the interfacial state problem between Ge material and the insulation oxide, reduce this electric leakage and scattering at the interface, also can excessively not reduce the mobility performance of Ge material in addition.In addition, the SiN stress cap layer through the embodiment of the invention can make channel region produce strain, thereby improves device performance.In effective embodiment of the present invention, when the height of side wall was 0.5-0.8 times of height of gate electrode, the stress of SiN stress cap layer can more effectively be delivered to channel region, thereby more effectively improves device performance.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (8)
1. a strain GeOI structure is characterized in that, comprising:
The surface has the silicon substrate of oxide insulating layer;
Be formed on the Ge layer on the said oxide insulating layer, wherein, be formed with the first passivation thin layer between said Ge layer and the said oxide insulating layer;
The grid that are formed on the said Ge layer pile up, and are formed on channel region and drain region and the source region of channel region both sides of said grid under piling up; With
Cover the SiN stress cap layer that said grid pile up so that said channel region produces strain,
Wherein, the said first passivation thin layer is strontium germanide thin layer or barium germanide thin layer.
2. strain GeOI structure as claimed in claim 1 is characterized in that said grid pile up and comprise:
Be positioned at the gate dielectric layer on the said Ge layer;
Be positioned at the gate electrode on the said gate dielectric layer; With
Be positioned at the side wall of said gate dielectric layer and said gate electrode both sides, wherein, the height of said side wall be said gate electrode height 0.5-0.8 doubly.
3. strain GeOI structure as claimed in claim 1 is characterized in that, also comprises:
Be formed on the second passivation thin layer on the said Ge layer, the said second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
4. strain GeOI structure as claimed in claim 1 is characterized in that, links to each other through the bonding mode between said oxide insulating layer and the said Ge layer.
5. the formation method of a strain GeOI structure is characterized in that, may further comprise the steps:
On first substrate, form the Ge layer;
The first surface of said Ge layer is handled to form the first passivation thin layer;
With said first substrate, said Ge layer and the upset of the said first passivation thin layer and be transferred to the silicon substrate that the surface has oxide insulating layer;
Remove said first substrate;
The grid that formation is positioned on the said Ge layer pile up, and form and to be positioned at said grid and to form channel region under piling up, and the drain region and the source region that are positioned at said channel region both sides; With
, said grid form to cover SiN stress cap layer that said grid pile up on piling up so that said channel region produces strain,
Wherein, the said first passivation thin layer is strontium germanide thin layer or barium germanide thin layer.
6. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, the said grid that on the Ge layer, form pile up further and comprise:
On said Ge layer, form gate dielectric layer;
On said gate dielectric layer, form gate electrode;
Form side wall at said gate dielectric layer and said gate electrode both sides;
The said side wall of etching so that the height of said side wall be said gate electrode height 0.5-0.8 doubly.
7. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, after said removal first substrate, also comprises:
The second surface of said Ge layer is handled to form the second passivation thin layer, and the said second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
8. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, through the bonding mode the said first passivation thin layer is linked to each other with said oxide insulating layer.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100583707A CN102169888B (en) | 2011-03-10 | 2011-03-10 | Strain geoi structure and forming method thereof |
| PCT/CN2011/078946 WO2012119418A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
| US13/263,236 US8704306B2 (en) | 2011-03-10 | 2011-08-25 | Strained Ge-on-insulator structure and method for forming the same |
| PCT/CN2011/078948 WO2012119419A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
| US13/263,222 US8786017B2 (en) | 2011-03-10 | 2011-08-25 | Strained Ge-on-insulator structure and method for forming the same |
| US13/263,227 US8890209B2 (en) | 2011-03-10 | 2011-08-25 | Strained GE-ON-insulator structure and method for forming the same |
| PCT/CN2011/078944 WO2012119417A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100583707A CN102169888B (en) | 2011-03-10 | 2011-03-10 | Strain geoi structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102169888A CN102169888A (en) | 2011-08-31 |
| CN102169888B true CN102169888B (en) | 2012-11-14 |
Family
ID=44490972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100583707A Active CN102169888B (en) | 2011-03-10 | 2011-03-10 | Strain geoi structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102169888B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489777A (en) * | 2012-06-11 | 2014-01-01 | 中芯国际集成电路制造(上海)有限公司 | Stress memory technology method |
| CN107275416A (en) * | 2017-05-09 | 2017-10-20 | 浙江大学 | A kind of photo-detector and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1973155B1 (en) * | 2004-11-19 | 2011-07-06 | S.O.I. TEC Silicon | Method for fabricating a germanium on insulator (GeOI) type wafer |
| FR2892230B1 (en) * | 2005-10-19 | 2008-07-04 | Soitec Silicon On Insulator | TREATMENT OF A GERMAMIUM LAYER |
| CN101295647A (en) * | 2008-01-16 | 2008-10-29 | 清华大学 | Method for reinforcing MOS device channel region strain |
| CN101882624B (en) * | 2010-06-29 | 2011-09-14 | 清华大学 | Structure with high-Ge strained layer formed on insulating substrate and forming method |
-
2011
- 2011-03-10 CN CN2011100583707A patent/CN102169888B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102169888A (en) | 2011-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102184954B (en) | Ge channel device and forming method thereof | |
| CN102437088B (en) | Semiconductor structure and manufacture method thereof | |
| CN102117808B (en) | Field effect transistor device with improved carrier mobility and manufacturing method thereof | |
| CN103337516B (en) | Enhancement mode switching device and manufacture method thereof | |
| CN100583451C (en) | Semiconductor device and method for fabricating the same | |
| Mertens et al. | Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal | |
| CN102117750A (en) | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof | |
| CN202487541U (en) | Semiconductor structure | |
| CN102237401A (en) | High electron mobility transistors including lightly doped drain regions and methods of manufacturing the same | |
| CN101320711B (en) | Metal-oxide-semiconductor transistor and preparation thereof | |
| KR20140038826A (en) | Semiconductor devices and methods of manufacturing the same | |
| CN102769033A (en) | HEMT (high electron mobility transistor) with high breakdown voltage and manufacturing method of HEMT | |
| CN106257620B (en) | A kind of semiconductor devices and its manufacturing method, electronic device | |
| CN102237294B (en) | Source and drain region, contact hole and methods for forming source and drain region and contact hole | |
| CN102157379B (en) | High-performance semiconductor device and manufacturing method thereof | |
| CN102169888B (en) | Strain geoi structure and forming method thereof | |
| CN102651397B (en) | Semiconductor device and manufacturing method thereof | |
| CN102800699A (en) | Semiconductor structure and forming method thereof | |
| US8729639B2 (en) | Semiconductor device and method for producing the same | |
| CN102194692A (en) | Production method for semiconductor device | |
| CN102157432A (en) | GeOI structure and formation method thereof | |
| CN102184953B (en) | Stress GeOI structure and forming method thereof | |
| CN202003995U (en) | Field effect transistor device with stress structures | |
| CN102446700A (en) | Method for improving silicon substrate and obtained silicon substrate | |
| CN102184940A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |