CN102158227B - Non-integer N type phase-locked loop - Google Patents
Non-integer N type phase-locked loop Download PDFInfo
- Publication number
- CN102158227B CN102158227B CN 201010121443 CN201010121443A CN102158227B CN 102158227 B CN102158227 B CN 102158227B CN 201010121443 CN201010121443 CN 201010121443 CN 201010121443 A CN201010121443 A CN 201010121443A CN 102158227 B CN102158227 B CN 102158227B
- Authority
- CN
- China
- Prior art keywords
- frequency
- phase
- locked loop
- signal
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001914 filtration Methods 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims description 5
- 238000013139 quantization Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000001427 coherent effect Effects 0.000 description 2
- 230000004069 differentiation Effects 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Images
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention relates to a non-integer N type phase-locked loop, which comprises a phase detector (PD), a voltage control oscillator (VOO), a frequency divider (FD) and a frequency multiplier, wherein the frequency multiplier has a frequency multiplication coefficient of a fraction form; the phase detector is used for comparing a reference voltage and phase difference between frequency division signals output by the frequency divider, the voltage control oscillator is used for generating output frequency according to the phase difference, and the frequency multiplier is used for further performing frequency multiplication on the output frequency for generating a frequency multiplication signal; the frequency multiplier comprises a second phase-locked loop and can further generate a second loop; the frequency divider is used for performing frequency division on the frequency multiplication signal for generating a frequency division signal; and the phase detector is used for comparing the frequency division signal with reference frequency for judging the phase difference.
Description
Technical field
The present invention relates to a kind of phase-locked loop, particularly about a kind of phase-locked loop of nido non-integer N type.
Background technology
Phase-locked loop (phase-locked loop, PLL) is a kind of control circuit, and it uses negative feedback (negative feedback) so that the phase place of output frequency is locked in a reference frequency.The phase-locked loop is used in the various application widely, for example is used for synthesizing a stable frequency or replys the acquisition signal from communication channel.The output frequency of phase-locked loop and the ratio of reference frequency can be integers, or integer adds the mixed fraction of a mark, the former is commonly referred to Integer N type phase-locked loop/synthesizer (integer-N PLL/synthesizer), and the latter is commonly referred to non-integer N type phase-locked loop/synthesizer (fractional-N PLL/synthesizer).And in various types of non-integer N type synthesizers, the trigonometric integral synthesizer (delta-sigma synthesizer) with trigonometric integral (delta sigma) modulator (delta sigma modulator, SDM) often is used.Yet the quantization error that triangular integration modulator produces (quantization noise) can cause the phenomenon of output clock shake (clock jitter).In order to slow down clock jitter, will use and have a large amount of electric capacity the capacitor of (if for example surpassing thousand pico farads (picofarad, pF)) to filter quantization error, thereby cause the increase of circuit area and energy resource consumption.
Because existing phase-locked loop can't be reduced the clock jitter phenomenon of trigonometric integral synthesizer efficiently, therefore need badly and propose a kind of new framework, before needn't increasing circuit area, put, can filter efficiently quantization error.
Summary of the invention
In view of the foregoing invention background, the purpose of the embodiment of the invention is to propose a kind of non-integer N type phase-locked loop, and it need not use too large electric capacity and can filter efficiently quantization error.
According to the embodiment of the invention, non-integer N type phase-locked loop (fractional-N PLL) comprises the first phase-locked loop and the second phase-locked loop.In the first phase-locked loop, first-phase bit detector (phasedetector) has compared first-phase potential difference (phase difference) and has produced one first error signal and represented this first-phase potential difference.The first voltage controlled oscillator (voltage-controlled oscillator, VCO) produces an output frequency according to the first error signal.Frequency multiplier (frequency multiplier) this output frequency that doubles produces a frequency-doubled signal, and this frequency multiplier comprises the second phase-locked loop, and it has formed second servo loop.The first frequency divider (frequency divider) carries out frequency division to produce the first fractional frequency signal to frequency-doubled signal.By the first-phase bit detector the first fractional frequency signal and a reference frequency are compared, to determine this first-phase potential difference.In one embodiment, the frequency range of the second phase-locked loop of described frequency multiplier is greater than the frequency range of the first phase-locked loop.
Description of drawings
Fig. 1 is the function block schematic diagram of a specific embodiment of disclosed non-integral N-type phase-locked loop.
Fig. 2 is the system architecture schematic diagram of a specific embodiment of disclosed nido phase-locked loop.
Fig. 3 is a specific embodiment of the disclosed example implementation circuit with design parameter.
[main element symbol description]
1 phase-locked loop
10,150 phase detectors
11,151 electric charge pumps
12,152 loop filters
13,153 voltage controlled oscillators
14,154 frequency dividers
15 frequency multipliers
155 triangular integration modulators
f
rReference frequency
f
OutOutput frequency
Embodiment
At first, see also Fig. 1, be the function block schematic diagram of a specific embodiment of disclosed non-integral N-type phase-locked loop 1.
In the present embodiment, phase-locked loop 1 comprises phase detectors (phase detector, PD) 10, electric charge pump (Charge Pump, CP) 11, loop filter (Loop Filter, LF) 12, voltage controlled oscillator (Voltage-Controlled Oscillator, VCO) 13, frequency divider (Frequency Divider, FD) 14 and frequency multiplier (frequency multiplier) 15.Specifically, phase detectors 10 are preferably phase/frequency detector (phase frequency detector, PFD), are used for comparison reference frequency f
rAnd the phase difference between the fractional frequency signal of frequency divider 14 output represents the phase difference of two frequencies to produce an error signal.Electric charge pump 11 is controlled an electric charge pump electric current according to the error signal of phase detectors 10 outputs.Loop filter 12 can be a low pass filter (low-pass filter), be used for the output of level and smooth electric charge pump 11, be sent to voltage controlled oscillator 13 to produce a filtering signal, and this loop filter 12 can comprise a resistor capacitor circuit (RC circuit).Voltage controlled oscillator 13 is used for producing output frequency f
Out, this output frequency f
OutError signal proportional or that indirectly export according to phase detectors 10 produces with filtering signal.15 couples of output frequency f of frequency multiplier
OutCarry out frequency multiplication to produce a frequency-doubled signal.In the present embodiment, the Clock Multiplier Factor of frequency multiplier 15 is mixed fractions, that is an integer M adds a mark F.Frequency divider 14 is used for to the frequency-doubled signal frequency division to produce fractional frequency signal.In the present embodiment, the divide ratio of frequency divider 14 is Integer N.It should be noted that in the phase-locked loop 1, except all blocks of frequency multiplier 15 all can be implemented with general phase-locked loop technology.
Then, see also Fig. 2, be the system architecture schematic diagram of a specific embodiment of disclosed nido phase-locked loop.Please consult simultaneously Fig. 3, for having the example implementation circuit of design parameter.As shown in Figure 2, frequency multiplier 15 can come implementation by the phase-locked loop framework.Frequency multiplier 15 comprises phase detectors (PD) 150, an electric charge pump (CP) 151, a loop filter (LF) 152, a voltage controlled oscillator (VCO) 153 and a frequency divider 154, and wherein this frequency divider 154 has the divide ratio that a value is (M+F); 153 filtering signals of exporting according to loop filter (LF) 152 of voltage controlled oscillator (VCO) are to produce frequency-doubled signal.The function of above-mentioned block 151～154 and framework are similar to block 11～14, thus its details it will not go into details.In particular, phase detectors 150 are used for comparison output frequency f
OutAnd the phase difference between the fractional frequency signal of frequency divider 154 outputs.In addition, triangular integration modulator (delta sigma modulator, SDM) 155 can be according to the fractional frequency signal of frequency divider 154 to provide mark F to frequency divider 154.In this manual, can add " first " before the element such as phase detectors 10, electric charge pump 11, loop filter 12, voltage controlled oscillator 13, frequency divider 14 and the coherent signal thereof; And can add " second " before the element such as phase detectors 150, electric charge pump 151, loop filter 152, voltage controlled oscillator 153, frequency divider 154 and the coherent signal thereof, in order to differentiation.
According to framework shown in Figure 2, thereby form a kind of multilayer loop (multi-loop) or nido phase-locked loop.Although present embodiment only comes for example with the phase-locked loop in two-layer loop, however surpass the phase-locked loop (multi-loop PLL) in two-layer multilayer loop can certainly the same concept implementation out, so be not limited with disclosed person.In the present embodiment, voltage controlled oscillator gain (VCO gain) (for example 360MHz/v) of the voltage controlled oscillator 13 in the first loop of phase-locked loop (or main loop) is less than the voltage controlled oscillator gain (for example 1640MHz/v) of the voltage controlled oscillator 153 of the second servo loop of frequency multiplier 15.The frequency range in the first loop is less than second servo loop, so the running speed of second servo loop can be faster than the first loop.So second servo loop can filter first the quantization error that triangular integration modulator (SDM) 155 produces, next filter further quantization error by the first loop of narrower frequency range again.
According to above-described embodiment, the nido non-integer N type phase-locked loop more can filter quantization error efficiently compared to traditional phase-locked loop, and then reduces the phenomenon of output clock shake.The more traditional phase-locked loop of capacitance that it should be noted that nido capacitor that non-integer N type phase-locked loop is used is come littlely with capacitance.For instance, as shown in Figure 3, use the capacitor of capacitance 273pF namely enough to be used for filtering quantization error, therefore, can reduce practically circuit area and the energy loss of nido non-integer N type phase-locked loop.
The above is the preferred embodiments of the present invention only, is not to limit claim of the present invention; All other do not break away from the equivalence of finishing under the spirit that invention discloses and changes or modify, and all should be included in the following claim.
Claims (8)
1. non-integer N type phase-locked loop comprises:
One first-phase bit detector in order to compare a first-phase potential difference, represents this first-phase potential difference to produce one first error signal;
One first voltage controlled oscillator, its according to this first error signal to produce an output frequency;
One frequency multiplier, it carries out frequency multiplication to this output frequency, and to produce a frequency-doubled signal, this frequency multiplier comprises one second phase-locked loop, thereby forms a second servo loop; And
One first frequency divider, it carries out frequency division to this frequency-doubled signal, to produce one first fractional frequency signal, wherein, by this first-phase bit detector this first fractional frequency signal and a reference frequency is compared, to determine this first-phase potential difference;
Wherein, this first-phase bit detector, this first voltage controlled oscillator, this frequency multiplier and this first frequency divider form one first loop;
Wherein this second phase-locked loop comprises:
One second-phase bit detector in order to compare a second-phase potential difference, represents this second-phase potential difference to produce one second error signal;
One second electric charge pump, its according to this second error signal of this second-phase bit detector output to control one second electric charge pump electric current;
One second servo loop filter is in order to the output of level and smooth this second electric charge pump, to produce one second filtering signal;
One second voltage controlled oscillator, its according to this second filtering signal to produce this frequency-doubled signal; And
One second frequency divider in order to this frequency-doubled signal is carried out frequency division, to produce one second fractional frequency signal, wherein, compares this second fractional frequency signal and this output frequency by this second-phase bit detector, to determine this second-phase potential difference; And
Wherein said non-integer N type phase-locked loop also comprises a triangular integration modulator, and it is according to this second fractional frequency signal, so that the fractional value of Clock Multiplier Factor to be provided.
2. non-integer N type phase-locked loop as claimed in claim 1, wherein the frequency range of this second servo loop is greater than the frequency range in this first loop.
3. non-integer N type phase-locked loop as claimed in claim 1, wherein this first loop is fast for the running speed of this second servo loop.
4. non-integer N type phase-locked loop as claimed in claim 1, wherein this first-phase bit detector is a phase/frequency detector.
5. non-integer N type phase-locked loop as claimed in claim 1 also comprises one first electric charge pump, its according to this first error signal of this first-phase bit detector output to control one first electric charge pump electric current.
6. non-integer N type phase-locked loop as claimed in claim 5 also comprises one first loop filter, and in order to the output of level and smooth this first electric charge pump, to produce one first filtering signal, wherein this first filtering signal more reaches this first voltage controlled oscillator.
7. non-integer N type phase-locked loop as claimed in claim 6, wherein this first loop filter is a low pass filter (low-pass filter).
8. non-integer N type phase-locked loop as claimed in claim 7, wherein this first loop filter comprises resistor capacitor circuit (RC circuit).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010121443 CN102158227B (en) | 2010-02-11 | 2010-02-11 | Non-integer N type phase-locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010121443 CN102158227B (en) | 2010-02-11 | 2010-02-11 | Non-integer N type phase-locked loop |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102158227A CN102158227A (en) | 2011-08-17 |
| CN102158227B true CN102158227B (en) | 2013-04-17 |
Family
ID=44439449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010121443 Expired - Fee Related CN102158227B (en) | 2010-02-11 | 2010-02-11 | Non-integer N type phase-locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102158227B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102882518A (en) * | 2012-10-24 | 2013-01-16 | 四川和芯微电子股份有限公司 | Phase-locked loop system and implementation method for same |
| TWI552531B (en) * | 2015-12-24 | 2016-10-01 | 財團法人工業技術研究院 | Frequency synthesizer and frequency synthesis method |
| CN116667846B (en) * | 2023-08-01 | 2024-02-23 | 牛芯半导体(深圳)有限公司 | Frequency synthesis circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| CN1241325A (en) * | 1997-08-12 | 2000-01-12 | 皇家菲利浦电子有限公司 | Multichannel radio device, radio communication system, and fractional division frequency synthesizer |
| CN1815892A (en) * | 2005-01-31 | 2006-08-09 | 瑞昱半导体股份有限公司 | Circuit for detecting phase-error and generating control signal |
-
2010
- 2010-02-11 CN CN 201010121443 patent/CN102158227B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4789996A (en) * | 1988-01-28 | 1988-12-06 | Siemens Transmission Systems, Inc. | Center frequency high resolution digital phase-lock loop circuit |
| CN1241325A (en) * | 1997-08-12 | 2000-01-12 | 皇家菲利浦电子有限公司 | Multichannel radio device, radio communication system, and fractional division frequency synthesizer |
| CN1815892A (en) * | 2005-01-31 | 2006-08-09 | 瑞昱半导体股份有限公司 | Circuit for detecting phase-error and generating control signal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102158227A (en) | 2011-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8054114B2 (en) | Fractional-N phase-locked loop | |
| US10298244B2 (en) | Wide range frequency synthesizer with quadrature generation and spur cancellation | |
| AU637237B2 (en) | Frequency synthesizer | |
| US8587352B2 (en) | Fractional-N phase locked loop | |
| US8373469B2 (en) | Phase-locked loop based frequency synthesizer and method of operating the same | |
| CN103155415A (en) | Cancellation system for phase jumps at loop gain changes in fractional-n frequency synthesizers | |
| CN102158227B (en) | Non-integer N type phase-locked loop | |
| US8664989B1 (en) | Method to increase frequency resolution of a fractional phase-locked loop | |
| KR101002244B1 (en) | HERSHEY-KISS MODULATION PROFILE SPREAD SPECTRUM CLOCK GENERATOR USING DUAL δ-σ MODULATOR | |
| CN111294043B (en) | System for automatically recovering external clock based on PLL | |
| EP4175180A1 (en) | Circuitry and methods for fractional division of high-frequency clock signals | |
| US9191128B2 (en) | Spread spectrum clock generator and method for generating spread spectrum clock signal | |
| GB2504509A (en) | Phase locked loop with reduced susceptibility to VCO frequency pulling | |
| CN104320133A (en) | Electric circuit and method for restraining fractional stray of fractional phase locking loops | |
| CN110429935B (en) | Frequency-cutting phase-locked loop and algorithm applied by same | |
| Ghasemzadeh et al. | A new adaptive PLL to reduce the lock time in 0.18 µm technology | |
| CN207782771U (en) | A kind of phaselocked loop | |
| TWI412233B (en) | Fractional-n phase-locked loop | |
| CN116667846B (en) | Frequency synthesis circuit | |
| CN116707524B (en) | Phase-locked loop circuit applied to 16Gbps and above interface technology | |
| KR102392109B1 (en) | Fractional-N Phase Locked Loop Using Phase Rotator | |
| CN104702277A (en) | Phase-locked loop circuit | |
| US20140184274A1 (en) | Fractional-n frequency synthesizer with low quantization noise | |
| KR20110130294A (en) | Design of an integer-n phase delay locked loop | |
| Bagherzadeh et al. | Δ∑ Fractional-N Synthesizer for GSM-E-900 Frequency Standard |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 |