CN102158219B - Signal processing system - Google Patents
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- CN102158219B CN102158219B CN 201110020655 CN201110020655A CN102158219B CN 102158219 B CN102158219 B CN 102158219B CN 201110020655 CN201110020655 CN 201110020655 CN 201110020655 A CN201110020655 A CN 201110020655A CN 102158219 B CN102158219 B CN 102158219B
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Abstract
The embodiment of the invention discloses a signal processing system, which comprises a parameter regulation circuit, a capacitance isolation circuit, a rectifier circuit and a frequency halving circuit, wherein the parameter regulation circuit is used for regulating a parameter of a voltage signal to obtain a regulated signal; the capacitance isolation circuit is used for isolating the regulatedsignal to obtain a sharp pulse signal; the rectifier circuit is used for rectifying the sharp pulse signal to obtain a forward signal, wherein a difference between the amplitude of the forward signaland the amplitude of the voltage signal is less than a preset threshold value, and the cycle of the forward signal is a half of the cycle of the voltage signal; and the frequency halving circuit is used for outputting a frequency division signal by taking the forward signal as the clock pulse of a frequency division circuit, wherein the amplitude and cycle of the frequency division signal are thesame as those of the forward signal. By the technical scheme, the normal use of the signal is ensured. Simultaneously, in system designing, the capacitance of a capacitor in the capacitance isolationcircuit is set according to the amplitude and frequency of the voltage signal to ensure the capacitance isolation circuit to have relatively higher capacitive reactance, and when the signal passes through the capacitance isolation circuit, output current is low so as to avoid damages to a user and realize isolative protection.
Description
Technical field
The present invention relates to the signal processing technology field, more particularly, relate to a kind of signal processing system.
Background technology
End product go out family line TNV (telecommunication network voltage, communication network voltage)-2 circuit or the output voltage signal that do not go out family line TNV-3 circuit are transferred to client after through the modulators modulate in the signal processing system, demodulator demodulation in the client recycling system, the difference of the signal amplitude after the demodulation and voltage signal amplitude is in predetermined threshold value, cycle is identical with the voltage signal cycle, guarantees the normal use of signal.
Yet, go out family line TNV-2 circuit in normal working conditions, its output voltage signal is the high voltage low-frequency square-wave signal, magnitude of voltage surpasses SELV (Safety Extra Low Voltage, safety extra low voltage) limit value, do not go out family line TNV-3 circuit in normal working conditions, its output voltage signal also surpasses the limit value of SELV.And SELV refer to can adventurous ceiling voltage to the user under worst situation.Therefore, since the output voltage signal that goes out family line TNV-2 circuit or do not go out family line TNV-3 circuit of end product all surpasses the limit value of SELV, then for client, going out family line TNV-2 circuit or not going out family line TNV-3 circuit all is dangerous circuit, the user is when using out family line TNV-2 circuit or do not go out the output voltage signal of family line TNV-3 circuit, need careful operation, have an accident avoiding.Therefore, when guaranteeing normally to use signal, need carry out isolating and protecting to going out family line TNV-2 circuit or not going out family line TNV-3 circuit, guarantee the security of products energy, and then guarantee user's safety.
Summary of the invention
For solving the problems of the technologies described above, the embodiment of the invention provides a kind of signal processing system, when using to guarantee that signal is normal, and to the isolating and protecting of dangerous circuit, and then assurance user's safety.Its technical scheme is as follows:
The embodiment of the invention provides a kind of signal processing system, comprising:
The parameter regulating circuit for the parameter of regulation voltage signal, obtains conditioning signal, and described parameter comprises amplitude at least, and the cycle of described conditioning signal is identical with the cycle of described voltage signal;
The electric capacity buffer circuit that links to each other with described parameter regulating circuit is used for isolating described conditioning signal, obtains the spike signal, and the amplitude of described spike signal is identical with amplitude and the cycle of described conditioning signal respectively with the cycle;
The rectification circuit that links to each other with described electric capacity buffer circuit is used for described spike signal rectification, obtains forward signal, and the difference of the amplitude of described forward signal and described voltage signal amplitude is in predetermined threshold value, and the cycle is 1/2 of the described voltage signal cycle;
The frequency-halving circuit that links to each other with described rectification circuit is used for the clock pulse of described forward signal as frequency dividing circuit, the output frequency division signal, and the amplitude of described fractional frequency signal is identical with described forward signal amplitude, and the cycle is identical with the cycle of described voltage signal.
Use technique scheme, after voltage signal passes through parameter regulating circuit, electric capacity buffer circuit, rectification circuit and frequency-halving circuit successively, the amplitude of the signal of system's output and voltage signal amplitude are in predetermined threshold value, and the cycle is identical with the voltage signal cycle, has guaranteed the normal use of signal.Simultaneously, when the capacity of electric capacity designs in system in the electric capacity buffer circuit, according to amplitude and the frequency setting of voltage signal, the capacitive reactance that guarantees the electric capacity buffer circuit is bigger, and during this electric capacity buffer circuit of signal process, its output current is very little, can not work the mischief to the user, and then realize isolating and protecting.Therefore, the signal processing system that the embodiment of the invention provides realizes the isolating and protecting to dangerous circuit when guaranteeing the normal use of signal, and then guarantees user's safety.
Description of drawings
The structural representation of the signal processing system that Fig. 1 provides for the embodiment of the invention;
Fig. 2 is a kind of circuit diagram of signal processing system shown in Figure 1;
Fig. 3 is the oscillogram of signal among Fig. 2;
Fig. 4 is the another kind of circuit diagram of signal processing system shown in Figure 1;
Fig. 5 is the oscillogram of signal among Fig. 4;
Fig. 6 is another circuit diagram of signal processing system shown in Figure 1;
Fig. 7 is the oscillogram of signal among Fig. 6;
Fig. 8 is another circuit diagram of signal processing system shown in Figure 1;
Fig. 9 is the oscillogram of signal among Fig. 8.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Going out family line TNV-2 circuit or not going out family line TNV-3 circuit of end product is dangerous circuit, and the output voltage signal of circuit is the high voltage low-frequency square-wave signal, and electric current is bigger in signals transmission, is enough to endanger user's safety.In view of this, the embodiment of the invention provides a kind of signal processing system, when guaranteeing the normal use of signal, realizes the isolating and protecting to dangerous circuit, and then guarantees user's safety.
Fig. 1 is the structural representation of the signal processing system that provides of the embodiment of the invention, comprising: parameter regulating circuit 10, electric capacity buffer circuit 11, rectification circuit 12 and frequency-halving circuit 13, wherein:
Certainly, parameter also comprises rising edge time and/or the trailing edge time of signal.For example: it is 5ns that host-host protocol requires rising edge and trailing edge with voltage signal, and duty ratio is 50% etc.; At this moment, if primary signal does not satisfy the requirement of host-host protocol, then need corresponding parameter is adjusted, to satisfy the requirement of host-host protocol.The adjustment of these parameters can realize by type of device, repeat no more here.
Electric capacity buffer circuit 11 is used for isolating conditioning signal, obtains the spike signal.The amplitude of spike signal is identical with amplitude and the cycle of conditioning signal respectively with the cycle.When the appearance value of electric capacity designs in system in the electric capacity buffer circuit 11, frequency setting according to voltage signal, the capacitive reactance that guarantees electric capacity buffer circuit 11 is bigger, during this electric capacity buffer circuit 11 of signal process, its output current is very little, can not work the mischief to the user, and then realize isolating and protecting to voltage signal.For example: when the amplitude of voltage signal is 90V, when frequency was 25Hz, those skilled in the art as can be known, the human body safe current is 10ma, therefore, be lower than the human body safe current in order to guarantee electric capacity buffer circuit 11 output currents, then the appearance value of electric capacity minimum is 0.07PF in the electric capacity buffer circuit 11.
Fig. 2 is a kind of physical circuit figure of signal processing system shown in Figure 1.Fig. 3 is the signal waveforms after voltage signal is handled through circuit diagram shown in Figure 2.In the signal processing system shown in Figure 2, parameter regulating circuit 10 is the total radio amplifier that directly is coupled, and comprising: NPN triode 101, base resistance 102,103, collector resistance 104, negative feedback resistor 105 and power supply 106.Wherein: collector resistance 104 1 ends connect the collector electrode of NPN triode 101, the other end connects power supply 106, negative feedback resistor 105 is connected between the emitter and ground end of NPN triode 101, base resistance 103 is connected between the base stage and power supply 106 of NPN triode 101, one end of base resistance 102 is connected the tie point of the base stage of base resistance 103 and NPN triode 101, and the other end connects voltage signal.
Because the rising edge of the voltage signal of different clocks is different with trailing edge, voltage signal is through behind the rectification circuit 12 simultaneously, signal amplitude descends, therefore at first need the amplitude of voltage signal is increased oppositely, comprise the full-bridge rectification bridge circuit as rectification circuit among Fig. 2 12, signal pressure drop after oversampling circuit has reduced by two diode forward conduction voltage drops, when voltage signal is that high level is 3.3V, low level is 0V, and the cycle is the square-wave signal of 250ns, through behind the rectification circuit 12, voltage falls 1.5V, becomes 1.8V, so be lower than the voltage signal amplitude for fear of signal through rectification circuit 12 back amplitudes, therefore, the amplitude of voltage signal need be increased.Behind the voltage signal process parameter regulating circuit 10, its amplitude rises to 5V in the embodiment of the invention.
In addition, except needing the amplitude of regulation voltage signal, also need rising edge and trailing edge are adjusted to preset value, for example: use the high frequency low-power transistor, make that the rising edge of voltage signal is 5ns, trailing edge is 10ns.In order to realize the function of parameter regulating circuit 10, selecting by the requirement decision of host-host protocol to characteristics of signals of triode, such as: the voltage signal of transmission 1MHz, duty ratio is 50%, delay requirement is less than 20ns, and the ON time minimum value of so selected triode is 20ns.
The embodiment of the invention why total radio amplifier that directly is coupled of the employing among Fig. 2 is because the quiescent point Q of triode has determined not only whether circuit can produce distortion, but also affects dynamic parameters such as voltage amplification factor, input resistance.In fact, the fluctuation of voltage signal, element aging and because of the variation of transistor parameter that variations in temperature causes all can be caused the instability of quiescent point Q, thereby be made the dynamic parameter instability, even causes the circuit can't operate as normal.Cause quiescent point Q unsettled all multifactor in, temperature is main to the influence of transistor parameter.And the direct coupling total radio amplifier among employing Fig. 2 is when temperature raises, collector current I
cIncrease emitter current I
eWill inevitably increase, thus the voltage on the emitter resistance 105 to increase (be emitter voltage to earth U thereupon
EIncrease); Because base stage quiescent voltage U
BQSubstantially constant, and the voltage U between base stage and the emitter
BE=U
B-U
ESo, U
BECertainly will reduce, cause base current I
bReduce collector current I
cCorresponding I thereupon
cReduce.As a result, collector current I
cRaise the part increases by owing to base current I with temperature
bThe part that reduces and reduce offsets, collector current I
cTo be constant substantially, U
CETo be constant substantially also, thereby make quiescent point Q keep stable.Equally, when temperature reduces, can guarantee that also quiescent point Q keeps stable.Basic total radio amplifier can't guarantee that quiescent point Q is stable under the situation of variations in temperature.
Those skilled in the art as can be known, adopt metal-oxide-semiconductor field effect t (Metal-Oxide Field Effect Transistor, MOSFET), or the field effect transistor of other types, cooperate corresponding resistor also can form similar amplifying circuit, realize the function that parameter is regulated, do not repeat them here.
The voltage signal that circuit diagram shown in Figure 2 applies in gauge point 1 place is to be time of delay 2ns, and fall time and rise time are 5ns, and high level is 3.3V, and low level is 0V, and the cycle is the square-wave signal of 250ns, as the A waveform among Fig. 3.This square-wave signal is through behind the direct coupling total radio amplifier 10, and its amplitude rises to 5V, and its amplification oppositely back voltage is exported the waveform of its output such as the B waveform among Fig. 3 at gauge point 2.Contrast A waveform and B waveform, the relative amplitude of B waveform is greater than the relative amplitude of A waveform.
Electric capacity buffer circuit 11 comprise that first electric capacity 111 and second electric capacity, 112, the first electric capacity 111 are connected the signal output positive terminal of parameter regulating circuit, and second electric capacity 112 is connected the signal output negative phase end of direct coupling total radio amplifier 10.When the capacity system of first electric capacity and second electric capacity designs, according to amplitude and the frequency setting of voltage signal.For example, when the amplitude of voltage signal is 90V, when frequency was 25Hz, then appearance value minimum was 0.07PF, can be 1pF～2200pF.Become waveform of sharp pulses behind the B waveform process electric capacity buffer circuit 11 among Fig. 3, the waveform shape at gauge point 3 places is shown in the C waveform among Fig. 3.The amplitude of signal shown in the C waveform is identical with amplitude and the signal period of the described signal of B waveform respectively with the signal period.
Frequency-halving circuit 13 is specially rising edge and triggers d type flip flop, and the clock end of described rising edge triggering d type flip flop connects the output of described load resistance 122, and input connects negative output, output output frequency division signal.The clock pulse that is to say rising edge triggering d type flip flop is the signal shown in the D waveform, saltus step takes place at the rising edge of clock pulse in the output of d type flip flop constantly, therefore, d type flip flop has been realized two divided-frequency to signal, and its output signal at gauge point 5 is shown in the E waveform among Fig. 3.Contrast E waveform and D waveform as can be seen, both amplitudes are identical, and the cycle of E waveform is the twice of D wave period, and namely the amplitude of E waveform and A waveform differs 0.2, and the cycle is identical, guarantee the normal use of signal.
Certainly, frequency-halving circuit 13 can adopt other triggers, for example: the T trigger.Can also adopt the combination of trailing edge d type flip flop and inverter.
In one embodiment of the invention, first electric capacity 111 in the signal processing system, second electric capacity 112 and load resistance 122 can satisfy following relation: the time of the series capacitance of first electric capacity 111 and second electric capacity 112 and the product gained of load resistance 122, and less than the shared time of low level in the one-period in the spike signal.The relation that first electric capacity 111 in the embodiment of the invention, second electric capacity 112 and load resistance 122 satisfy can for: the series capacitance of first electric capacity 111 and second electric capacity 112 and the product gained time of load resistance 122 are less than the half period time of the C waveform among Fig. 3.When first electric capacity 111, second electric capacity 112 and load resistance 122 satisfied above-mentioned relation, the signal that the frequency-halving circuit of signal processing system is exported and original voltage signal same degree were higher.
Use technique scheme, after voltage signal passes through parameter regulating circuit 10, electric capacity buffer circuit 11, rectification circuit 12 and frequency-halving circuit 13 successively, the amplitude of the signal of system's output and voltage signal amplitude are in predetermined threshold value, cycle is identical with the voltage signal cycle, has guaranteed the normal use of signal.Simultaneously, when the capacity of electric capacity designs in system in the electric capacity buffer circuit, according to amplitude and the frequency setting of voltage signal, the capacitive reactance that guarantees electric capacity buffer circuit 11 is bigger, and during signal process electric capacity buffer circuit 11, its output current is very little, can not work the mischief to the user, and then realize isolating and protecting.Therefore, the signal processing system that the embodiment of the invention provides realizes the isolating and protecting to dangerous circuit when guaranteeing the normal use of signal, and then guarantees user's safety.In addition, be the basic components and parts of using always because the circuit of the signal processing system that provides of the embodiment of the invention constitutes what choose, and do not use the special chip of optical coupler and other logic loads such as SI88XX series etc., therefore, reduced the cost of system.
See also Fig. 4 and Fig. 5, Fig. 4 is the another kind of circuit diagram of signal processing system shown in Figure 1, and Fig. 5 is the oscillogram of signal among Fig. 4.
The circuit of electric capacity buffer circuit 11, rectification circuit 12 and frequency-halving circuit 13 constitutes identically in circuit diagram shown in Figure 4 and the circuit diagram shown in Figure 2, and this embodiment of the invention is no longer set forth.Both differences are that the parameter regulating circuit 10 in the circuit diagram shown in Figure 4 is first inverter, the input termination voltage signal of first inverter, output output regulation signal.First inverter can be TTL (Transistor-Transistor Logic, logic gates) inverter or CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) inverter, voltage signal through first inverter after, when the amplitude of voltage signal surpasses the threshold value of first inverter, output low level signal, otherwise output high level signal.
After voltage signal was handled through circuit diagram shown in Figure 4, the oscillogram of the signal of institute's gauge point as shown in Figure 5 in the circuit diagram.Wherein: the signal of gauge point 1 is voltage signal, and its waveform is shown in the A waveform among Fig. 5.Voltage signal through first inverter after at the reverse conditioning signal of gauge point 2 output amplification, the B waveform among conditioning signal waveform such as Fig. 5.Conditioning signal is input to the electric capacity buffer circuit 11 that comprises first electric capacity 111 and second electric capacity 112, conditioning signal is exported the spike signal through the charging and discharging of first electric capacity 111 and second electric capacity 112 at gauge point 3 places, the waveform of spike signal is referring to the C waveform among Fig. 5.The spike signal is input to the rectification circuit 12 that comprises full-bridge rectification bridge circuit 121 and load resistance 122 again, and 4 places are rectified the output forward signal at gauge point, and the oscillogram of this signal is the D waveform among Fig. 5.Forward signal is by frequency-halving circuit 13 two divided-frequencies, at gauge point 5 output square-wave signal, the waveform of square-wave signal such as the E waveforms among Fig. 5.The amplitude of contrast E waveform and A waveform differs 0.2, and the cycle is identical, guarantees the normal use of signal.
Use technique scheme, when guaranteeing the normal use of signal, realize the isolating and protecting to dangerous circuit, and then guarantee user's safety.In addition, be the basic components and parts of using always because the circuit of the signal processing system that provides of the embodiment of the invention constitutes what choose, and do not use the special chip of optical coupler and other logic loads, therefore, reduced the cost of system.
The circuit diagram of signal processing system can also use other circuit diagram except adopting Fig. 2 and circuit diagram shown in Figure 4.Fig. 6 is another circuit diagram of the signal processing system that provides of the embodiment of the invention, and Fig. 7 is the oscillogram of signal among Fig. 6.
The components and parts of circuit map parameter regulating circuit 10 shown in Figure 6 constitute identical with the components and parts formation of parameter regulating circuit among Fig. 2, it all is the total radio amplifier that directly is coupled, parameter regulating circuit 10 comprises: NPN triode 101, base resistance 102,103, collector resistance 104, negative feedback resistor 105 and power supply 106.Wherein: collector resistance 104 1 ends connect the collector electrode of NPN triode 101, the other end connects power supply 106, negative feedback resistor 105 is connected between the emitter and ground end of NPN triode 101, base resistance 103 is connected between the base stage and power supply 106 of NPN triode 101, one end of base resistance 102 is connected the tie point of the base stage of base resistance 103 and NPN triode 101, and the other end connects voltage signal.
Because the rising edge of the voltage signal of different clocks is different with trailing edge, voltage signal is through behind the rectification circuit 12 simultaneously, signal amplitude descends, therefore at first need the amplitude of voltage signal is increased oppositely, comprise a triode as rectification circuit among Fig. 6 12, signal pressure drop after the oversampling circuit has reduced a forward conduction voltage drop, i.e. 0.7V is when voltage signal is that high level is 3.3V, low level is 0V, cycle is the square-wave signal of 250ns, and through behind the rectification circuit 12, voltage falls 0.7V, become 2.6V, so be lower than the voltage signal amplitude for fear of signal through rectification circuit 12 back amplitudes, therefore, the amplitude of voltage signal need be increased.Behind the voltage signal process parameter regulating circuit 10, its amplitude rises to 4V in the embodiment of the invention.Simultaneously, signal reduces 0.7V in order to guarantee voltage during through second inverter in the rectification circuit 12, and therefore, the driving voltage of first inverter is than the high 0.7V of driving voltage of second inverter.
In addition, except needing the amplitude of regulation voltage signal, also need rising edge and trailing edge are adjusted to preset value, for example: use the high frequency low-power transistor, make the rising edge of voltage signal become 5ns, trailing edge becomes 10ns.In order to realize the function of parameter regulating circuit 10, selecting by the requirement decision of host-host protocol to characteristics of signals of triode, such as: the voltage signal of transmission 1MHz, duty ratio is 50%, delay requirement is less than 20ns, and the ON time minimum value of so selected triode is 20ns.
Electric capacity buffer circuit 11 comprises first isolation capacitance 111, second isolation capacitance 112 and first inductance 113, and wherein, first isolation capacitance 111 is connected the signal of parameter regulating circuit 10 and exports between the end of positive terminal and first inductance 113.Second isolation capacitance 112 is connected the signal of parameter regulating circuit 10 and exports between the other end of negative phase end and first inductance 113.
After the conditioning signal of parameter regulating circuit 10 output is isolated through first isolation capacitance 111 and second isolation capacitance 112, be coupled to the utmost point behind the electric capacity, and produce the spike signals at first inductance 113.At this moment, the waveform of gauge point 3 places spike signal sees also the C waveform among Fig. 7.
After spike signal shown in the C waveform among Fig. 7 is input to rectification circuit 12, signal is through second inverter 121, input value is during greater than second inverter, 121 threshold values, second inverter, 121 output low levels, otherwise output high level, therefore, the spike signal is through second inverter 121 signal shown in the D waveform in gauge point 4 place's output maps 7.Simultaneously, the spike signal is input to the emitter of positive-negative-positive triode 124 by first coupling capacitance 122, when the level at emitter place is low level, 124 conductings of positive-negative-positive triode, at this moment, the output of gauge point 5 places be low level, otherwise, export high level.The oscillogram of gauge point 5 place's output signals is shown in the E waveform among Fig. 7.
The output of second inverter 121 and positive-negative-positive triode 124 is connected or a door input of 127 separately.Well-known, or two inputs of door are output as low level, otherwise be high level when be high level simultaneously, therefore, signal pass through or 127 after, the signal shown in the F waveform in gauge point 6 place's output maps 7.
Frequency-halving circuit 13 triggers d type flip flop for rising edge, and the clock end that described rising edge triggers d type flip flop connects output described or door 127, and input connects the negative output; Rising edge triggers the output output frequency division signal of d type flip flop.The clock pulse that is to say rising edge triggering d type flip flop is the F waveform, and the output of d type flip flop at the rising edge of pulse saltus step takes place constantly, and therefore, d type flip flop has been realized two divided-frequency to signal, and its signal output waveform is the G waveform among Fig. 7.Contrast G waveform and A waveform as can be seen, both are identical, have guaranteed the normal use of signal.
Certainly, frequency-halving circuit 13 can adopt other triggers, for example: the T trigger.Can also adopt the combination of trailing edge d type flip flop and inverter.
Use technique scheme, when guaranteeing the normal use of signal, realize the isolating and protecting to dangerous circuit, and then guarantee user's safety.In addition, be the basic components and parts of using always because the circuit of the signal processing system that provides of the embodiment of the invention constitutes what choose, and do not use the special chip of optical coupler and other logic loads, therefore, reduced the cost of system.
See also Fig. 8 and Fig. 9, Fig. 8 is another circuit diagram of the signal processing system that provides of the embodiment of the invention, and Fig. 9 is the oscillogram of signal among Fig. 8.
The circuit of electric capacity buffer circuit 11, rectification circuit 12 and frequency-halving circuit 13 constitutes identically in circuit diagram shown in Figure 8 and the circuit diagram shown in Figure 6, and this embodiment of the invention is no longer set forth.Both differences are, parameter regulating circuit 10 in the circuit diagram shown in Figure 8 is first inverter, first inverter can be TTL inverter or CMOS inverter, voltage signal through first inverter after, when the amplitude of voltage signal surpasses the threshold value of first inverter, output low level signal, otherwise output high level signal.
After voltage signal was handled through circuit diagram shown in Figure 8, the oscillogram of the signal of institute's gauge point as shown in Figure 9 in the circuit diagram.Wherein: the signal of gauge point 1 is voltage signal, and its waveform is shown in the A waveform among Fig. 9.Voltage signal through first inverter after at the reverse conditioning signal of gauge point 2 output amplification, the B waveform among conditioning signal waveform such as Fig. 9.Conditioning signal is input to the electric capacity buffer circuit 11 that comprises first isolation capacitance 111, second isolation capacitance 112 and first inductance 113, conditioning signal is through the charging and discharging of first isolation capacitance 111 and second isolation capacitance 112, and produce the spike signal at first inductance simultaneously, at gauge point 3 places output spike signal, the waveform of spike signal is referring to the C waveform among Fig. 9.The spike signal be input to again comprise second inverter 121, first coupling capacitance 122, power supply 123, positive-negative-positive triode 124, first resistance 125, second resistance 126 and or the rectification circuit 12 of door 127, the signal shown in the D waveform in gauge point 4 place's output maps 9, the signal shown in the E waveform in gauge point 5 place's output maps 9, the process of signal shown in signal shown in the D waveform and E waveform NAND gate 127 is at the signal of gauge point 6 places output shown in F waveform among Fig. 9.This signal is again by frequency-halving circuit 13 two divided-frequencies, at gauge point 7 output square-wave signal, the waveform of square-wave signal such as the G waveforms among Fig. 9.Contrast G waveform and A waveform as can be seen, both are identical, have guaranteed the normal use of signal.
Need to prove: in the embodiment of the invention, it is identical with the value requirement of first isolation capacitance and second isolation capacitance among Fig. 6 that the value of first isolation capacitance 111 and second isolation capacitance 112 requires, that is: the withstand voltage 2kv that is greater than of both isolation, capacity will be adjusted according to the frequency of voltage signal, when being 2MHz such as the frequency when voltage signal, the capacity of first isolation capacitance 111 and second isolation capacitance 112 is 680pf, when frequency raises, capacity reduces, capacitive reactance with assurance buffer circuit 11 is bigger, thereby guarantee that output current is very little, not the entail dangers to user security.
Use technique scheme, guaranteeing that signal normally uses simultaneously, realize the isolating and protecting to dangerous circuit, and then guarantee user's safety.In addition, be the basic components and parts of using always because the circuit of the signal processing system that provides of the embodiment of the invention constitutes what choose, and do not use the special chip of optical coupler and other logic loads, therefore, reduced the cost of system.
Need to prove, in this article, relational terms such as first and second grades only is used for an entity or operation are made a distinction with another entity or operation, and not necessarily requires or hint and have the relation of any this reality or in proper order between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make and comprise that process, method, article or the equipment of a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.Do not having under the situation of more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
In several embodiment that the application provides, should be understood that disclosed circuit diagram not surpassing in the application's the spirit and scope, can be realized in other way.Current embodiment is a kind of exemplary example, should be as restriction, and given particular content should in no way limit the application's purpose.
The above only is the specific embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1. a signal processing system is characterized in that, comprising:
The parameter regulating circuit, the parameter that is used for regulation voltage signal, obtain conditioning signal, the cycle of described conditioning signal is identical with the cycle of described voltage signal, described parameter comprises amplitude at least, the parameter of described regulation voltage signal comprises the amplitude that improves voltage signal to default setting, and high-low level is carried out oppositely;
The electric capacity buffer circuit that links to each other with described parameter regulating circuit is used for isolating described conditioning signal, obtains the spike signal, and the amplitude of described spike signal is identical with amplitude and the cycle of described conditioning signal respectively with the cycle;
The rectification circuit that links to each other with described electric capacity buffer circuit is used for described spike signal rectification, obtains forward signal, and the difference of the amplitude of described forward signal and described voltage signal amplitude is in predetermined threshold value, and the cycle is 1/2 of the described voltage signal cycle;
The frequency-halving circuit that links to each other with described rectification circuit is used for the clock pulse of described forward signal as frequency dividing circuit, the output frequency division signal, and the amplitude of described fractional frequency signal is identical with described forward signal amplitude, and the cycle is identical with the cycle of described voltage signal.
2. signal processing system according to claim 1 is characterized in that, described parameter regulating circuit is the total radio amplifier that directly is coupled.
3. signal processing system according to claim 1 is characterized in that, described parameter regulating circuit is first inverter, the described voltage signal of input termination of described first inverter, and the output of described first inverter is exported described conditioning signal.
4. according to claim 2 or 3 described signal processing systems, it is characterized in that,
Described rectification circuit comprises full-bridge rectification bridge circuit and load resistance, and described load resistance connects between two dc output ends of full-bridge rectification bridge circuit;
The voltage signal at described load resistance two ends is described forward signal.
5. signal processing system according to claim 4 is characterized in that,
Described electric capacity buffer circuit comprises first electric capacity and second electric capacity, described first electric capacity is connected the signal of parameter regulating circuit and exports between the positive input of positive terminal and full-bridge rectification bridge circuit, and described second electric capacity is connected the signal of parameter regulating circuit and exports between the negative input of negative phase end and described full-bridge rectification bridge circuit;
Described frequency-halving circuit is that rising edge triggers d type flip flop, and the clock end of described rising edge triggering d type flip flop connects the output of described load resistance, and the input end connects negative output end; Described rising edge triggers the output of d type flip flop and exports described fractional frequency signal.
6. signal processing system according to claim 5, it is characterized in that, the pass of described first electric capacity, second electric capacity and load resistance is: the time of the series capacitance of first electric capacity and second electric capacity and the product gained of load resistance, and less than the shared time of low level in the one-period in the spike signal.
7. according to claim 2 or 3 described signal processing systems, it is characterized in that,
Described electric capacity buffer circuit comprises first isolation capacitance, second isolation capacitance and first inductance, wherein, described first isolation capacitance is connected the signal of parameter regulating circuit and exports between the end of positive terminal and described first inductance, and described second isolation capacitance is connected the signal of parameter regulating circuit and exports between the other end of negative phase end and described first inductance;
Described rectification circuit comprise second inverter, first coupling capacitance, power supply, positive-negative-positive triode, first resistance, second resistance and or door; Wherein: the input of second inverter connects the tie point of first isolation capacitance and first inductance, first resistance is connected between the base stage of power supply and positive-negative-positive triode, second resistance is connected between the emitter of power supply and positive-negative-positive triode, the grounded collector of positive-negative-positive triode, first coupling capacitance is connected between the base stage of the input of second inverter and positive-negative-positive triode, or two inputs of door connect the output of second inverter and the emitter of positive-negative-positive triode respectively.
8. signal processing system according to claim 7 is characterized in that, described frequency-halving circuit is that rising edge triggers d type flip flop, and described rising edge triggers the output of the clock end connection NAND gate of d type flip flop, and input connects the negative output; Described rising edge triggers the output of d type flip flop and exports described fractional frequency signal.
9. signal processing system according to claim 7 is characterized in that, the isolation of described first isolation capacitance and described second isolation capacitance is withstand voltage greater than 2kv.
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| CN102769445A (en) * | 2012-08-08 | 2012-11-07 | 中国科学院东北地理与农业生态研究所 | Ultra-narrow pulse sampling circuit |
| CN105429617B (en) * | 2015-11-13 | 2018-11-09 | 武汉衡伟信息技术有限公司 | Gate drive signal transmission circuit and its transmission method suitable for IGBT |
| CN108011566A (en) * | 2017-12-29 | 2018-05-08 | 天津职业技术师范大学 | Electric motor saver |
| CN110868303A (en) * | 2019-12-05 | 2020-03-06 | 杭州协能科技股份有限公司 | Isolated communication wake-up circuit and wake-up method |
| CN111245426B (en) * | 2020-01-14 | 2023-04-28 | 华源智信半导体(深圳)有限公司 | Isolation capacitor communication circuit and failure protection method thereof |
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| CN101640527A (en) * | 2009-08-19 | 2010-02-03 | 广州金升阳科技有限公司 | IGBT driving circuit capable of realizing signal transmission by pulse modulation demodulation system |
| CN201435683Y (en) * | 2009-03-31 | 2010-03-31 | 深圳市安邦信电子有限公司 | Magnetic coupling digital signal bidirectional transmission circuit |
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| JP4826795B2 (en) * | 2007-02-20 | 2011-11-30 | Ｔｄｋラムダ株式会社 | Synchronous circuit |
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| CN201435683Y (en) * | 2009-03-31 | 2010-03-31 | 深圳市安邦信电子有限公司 | Magnetic coupling digital signal bidirectional transmission circuit |
| CN101640527A (en) * | 2009-08-19 | 2010-02-03 | 广州金升阳科技有限公司 | IGBT driving circuit capable of realizing signal transmission by pulse modulation demodulation system |
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