CN102148254A - Deep energy level impurity ionizing collision transistor - Google Patents
Deep energy level impurity ionizing collision transistor Download PDFInfo
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- CN102148254A CN102148254A CN2011100240745A CN201110024074A CN102148254A CN 102148254 A CN102148254 A CN 102148254A CN 2011100240745 A CN2011100240745 A CN 2011100240745A CN 201110024074 A CN201110024074 A CN 201110024074A CN 102148254 A CN102148254 A CN 102148254A
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Abstract
The invention provides a deep energy level impurity ionizing collision transistor belonging to the fields of field effect transistor logic devices and circuits in a CMOS (Complementary Metal Oxide Semiconductor) ultra large scale integrated circuit (ULSI). The transistor comprises the same N-type or P-type doped source electrode and drain electrode, a control gate and a high-resistance drift region, wherein the drift region comprises deep energy level impurities which can ionize carriers under a high field; leakage current of the device can be reduced by the high-resistance drift region in an off state; and a large amount of carriers can be instantly provided when the device is in an on state, so that the on of the device is promoted. Compared with the conventional low-power-consumption device TFET (Tunneling Field Effect Transistor), since drift diffusion current is adopted, larger on current and steeper sub-threshold frequency can be achieved. Compared with the conventional low-power-consumption device IMOS (Ion Implanted Metal Oxide Semiconductor), since a critical electric field of deep energy level impurity ionization is far lower than an avalanche critical electric field, the reliability of the device can be enhanced while working points of the device are greatly reduced.
Description
Technical field
The invention belongs to FET logic device and circuit field in the CMOS super large integrated circuit (ULSI), be specifically related to a kind of field-effect transistor of novel conducting mechanism, deep-level impurity ionizing collision transistor (DIMOS).
Background technology
Along with the micro-nano size of electronic devices is constantly dwindled, level of integrated system is more and more higher, and the power consumption of whole system will limit the principal element that the micro-nano electronics continues development.Conventional MOS FET is owing to short-channel effect, and along with the shortening of channel length, the leakage current of device is in continuous rising, so the quiescent dissipation of system can constantly rise.In addition, because conventional MOS FET sub-threshold slope is subjected to the one theory of KT/q and can't reduces synchronously along with dwindling of device size, so the dynamic power consumption of whole system can not further reduce.Therefore we need adopt the fieldtron of novel working mechanism to break through the one theory of MOSFET, realize that super steep sub-threshold slope reduces the device dynamic power consumption, reduce the device static leakage current simultaneously, reduce quiescent dissipation.In this field, having of successively being suggested worn field-effect transistor (TFET), snowslide impact-ionization field effect transistor (IMOS) then.TFET be a kind of field-effect transistor of utilizing the band band to wear then to provide charge carrier to raceway groove as shown in Figure 1, it is low that it has quiescent dissipation, the device working point is also lower, sub-threshold slope can break through advantages such as the MOSFET limit.But its sub-threshold slope is along with the increase meeting of gate voltage progressively worsens.Realize more satisfactory sub-threshold slope for final, not only need extremely thin gate dielectric layer thickness, and harsh requirement is also arranged, suitable big of technology difficulty for the abrupt change degree of source end metallurgical junction.IMOS be a kind of utilize drift region avalanche multiplication effect and the field-effect transistor of conducting as shown in Figure 2.It has advantages such as leakage current is little, and sub-threshold slope is extremely low.But owing in silicon-based devices, in order to make snowslide take place, must provide very high outer bias voltage, this has just limited its application in the low-power consumption field.In addition, because snowslide can produce a large amount of hot carriers when taking place, the charge carrier of these high energy brings the problem of reliability aspect for the application of device.Therefore, the invention of other novel working mechanism devices has highlighted its necessity.
Summary of the invention
The object of the present invention is to provide a kind of deep-level impurity ionization by collision under high field action of utilizing to go out electronics and the type field-effect transistor of conducting.
Technical scheme of the present invention is as follows:
Deep-level impurity ionizing collision transistor comprises that source, leakage, control gate also have the drift region as shown in Figure 3.For N moldeed depth energy level impurity ionization collision transistor, source transistor leaks and is all highly doped N type semiconductor, and for P moldeed depth energy level impurity ionization collision transistor, source-drain area is all the P type semiconductor material.The transistor drift district is near the source region, and control gate covers edge, drift region and drain junction edge.Be doped with the deep-level impurity of field-ionization in the drift region.
Described deep-level impurity is can ionization go out the alms giver of electronics or the main deep-level impurity that is subjected to that ionization goes out the hole under High-Field, is applied to respectively in N transistor npn npn and P transistor npn npn.This electric field is 10
4The order of magnitude of V/cm is 1/10th of a snowslide critical field.
Described deep-level impurity can be the deep energy level acceptor impurity that itself has been compensated by the shallow energy level alms giver and itself has been subjected to the deep energy level donor impurity of main compensation by shallow energy level, be applied to respectively in N transistor npn npn and P transistor npn npn.
Described deep-level impurity can adopt the ion injection mode to introduce, and also can adopt the substrate with deep-level impurity to design.
At silica-based N moldeed depth energy level impurity ionization collision transistor transistor, the deep-level impurity that mixes in its drift region can be subjected to main nickel for the deep energy level for shallow energy level alms giver phosphorus or the compensation of shallow energy level alms giver arsenic.
For silica-based P moldeed depth energy level impurity ionization collision transistor transistor, the deep-level impurity that mixes in its drift region can be subjected to main indium for deep energy level.
When deep-level impurity ionizing collision transistor is in OFF state, these deep-level impurities or the shallow level impurity compensation that does not have ionization or be introduced into.Whole drift region is in neutral high-impedance state.Electronics under described electric field strength in the deep energy level or hole can be ionized, and moment produces a large amount of charge carriers and provides charge carrier for break-over of device.
Technique effect of the present invention is as follows:
One, owing to have the such high resistance area in drift region between source knot and raceway groove, it can play the static leakage current that reduces device, reduces the effect of device quiescent dissipation.
Two, utilize electric field strength in the grid voltage modulation drift region, when electric field strength reaches the critical value of deep-level impurity ionization (about 10
4The order of magnitude of V/cm), the electronics on the deep-level impurity or hole moment are ionized out, and for raceway groove provides a large amount of charge carriers, transistor is opened rapidly.Can obtain very steep sub-threshold slope.
The existing low energy-consumption electronic device TFET of deep-level impurity ionizing collision transistor AND gate compares, because employing is the drift dissufion current, therefore can obtain bigger conducting electric current, and more precipitous sub-threshold slope.Compare with existing low energy-consumption electronic device IMOS,, can reduce the reliability that the device working point increases device simultaneously greatly because the critical electric field of deep-level impurity ionization approximately is 1/10th of a snowslide critical electric field.
Description of drawings
Fig. 1 is a plane TFET structural representation;
Fig. 2 is a planar I MOS structural representation;
Deep-level impurity ionizing collision transistor (DIMOS) structural representation that Fig. 3 proposes for the present invention;
Fig. 4 is the low field ionization (FI) collision of the silica-based N type of preparation transistor main technique step;
Wherein Fig. 4 a is the silicon chip behind growth oxide layer and the deposit polysilicon; Fig. 4 b is the substrate behind the photoetching active area; Fig. 4 c source is leaked and is injected; Fig. 4 d nickel impurity and phosphorus inject; Fig. 4 e is the low field ionization (FI) collision of the silica-based N type after source-and-drain junction forms a transistor junction composition.
The polygate electrodes of 1-TFET among the figure; The 2-TFET gate oxide; The source of 3-TFET; The substrate of 4-TFET; The leakage of 5-TFET; The 6-IMOS polygate electrodes; The 7-IMOS gate dielectric layer, the source electrode of 8-IMOS, the substrate of 9-IMOS, the drain electrode of 10-IMOS.The low field ionization (FI) collision of the silica-based N type of 11-the present invention transistor oxide layer, the low field ionization (FI) collision of the silica-based N type of 12-the present invention transistor source, the low field ionization (FI) collision of the silica-based N type of 13-the present invention transistor substrate, the low field ionization (FI) collision of the silica-based N type of 14-the present invention transistor drain, the low field ionization (FI) collision of the silica-based N type of 15-the present invention transistor drift district, the low field ionization (FI) collision of the silica-based N type of 16-the present invention transistor gate, the 17-photoresist.
Embodiment
The present invention will be further described below by example.It should be noted that the purpose of publicizing and implementing example is to help further to understand the present invention, but it will be appreciated by those skilled in the art that: in the spirit and scope that do not break away from the present invention and claims, various substitutions and modifications all are possible.Therefore, the present invention should not be limited to the disclosed content of embodiment, and the scope of protection of present invention is as the criterion with the scope that claims define.
With the low field ionization (FI) collision of N type transistor is example, and as shown in Figure 4, concrete implementation step comprises:
1, growth gate oxide 11 on silicon substrate 13, grid thickness gadget grid-control ability more is just good more, and between 4nm-20nm, the deposit polysilicon 16 then greatly for desired quantity, shown in Fig. 4 a;
2, make gate figure 16 by lithography, wherein the source end is reserved source region injection and deep-level impurity injection window, and drain terminal is reserved and leaked the injection window, shown in Fig. 4 b;
3, the deposit photoresist 17, and window is injected in the source that makes by lithography, and drain terminal is generally reserved the leakage injection window that polysilicon is hard mask, carries out the source then and leaks the N injection, shown in Fig. 4 c;
4, deposit photoresist 17 and make nickel by lithography and inject window, implanted dopant nickel (dosage is as the criterion with the final activator impurity that can form), and then inject the phosphorus or the arsenic of Isodose, shown in Fig. 4 d;
5, carry out the thermal annealing activator impurity one time, the drift region 15 that forms source-and-drain junction (12,14) and contain nickel impurity is shown in Fig. 4 e.
For P type silicon-based devices, need in the drift region, introduce the impurity indium, the upper limit of concentration of impurity indium does not surpass it and have electroactive property concentration in semiconductor.Indium can be introduced an acceptor level at top of valence band 0.16eV place, under normal temperature condition, and acceptor level in the indium and unionization, so the drift region presents high-impedance state.But indium is subjected to the master can ionization under certain electric field strength, and moment is introduced a large amount of holes in valence band, for break-over of device provides charge carrier.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (5)
1. deep-level impurity ionizing collision transistor, comprise source, leakage, control gate and drift region, the drift region is near the source region, control gate covers edge, drift region and drain junction edge, it is characterized in that, the source of N transistor npn npn is leaked and is all highly doped N type semiconductor, the deep energy level acceptor impurity that the drift region is doped with the deep energy level donor impurity or is compensated by the shallow energy level alms giver; The source of P transistor npn npn is leaked and is all highly doped P type semiconductor, and the drift region is doped with the deep energy level acceptor impurity or is subjected to the deep energy level donor impurity of main compensation by shallow energy level.
2. deep-level impurity ionizing collision transistor as claimed in claim 1 is characterized in that, is subjected to main nickel in the deep energy level of silica-based N transistor npn npn drift region doped shallow energy level alms giver's phosphorus or shallow energy level alms giver arsenic compensation.
3. deep-level impurity ionizing collision transistor as claimed in claim 1 is characterized in that, described silica-based P transistor npn npn drift region doping deep energy level is subjected to main indium.
4. as the described deep-level impurity ionizing collision of claim 1-3 transistor, it is characterized in that described deep-level impurity adopts the ion injection mode to introduce, or adopt substrate to realize with deep-level impurity.
5. deep-level impurity ionizing collision transistor as claimed in claim 1 is characterized in that described transistor is realized, or realized on materials such as SOI, nano wire on body silicon.
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| CN102800697A (en) * | 2012-08-24 | 2012-11-28 | 电子科技大学 | IGBT (insulated gate bipolar translator) device with high-temperature self-protection function |
| CN103426909A (en) * | 2012-05-18 | 2013-12-04 | 英飞凌科技股份有限公司 | Semiconductor device including first and second semiconductor materials |
| CN106847835A (en) * | 2017-04-01 | 2017-06-13 | 厦门天马微电子有限公司 | The preparation method and display device of a kind of display panel, display panel |
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Application publication date: 20110810 |