CN102148186A - Method for manufacturing semiconductor device - Google Patents
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- CN102148186A CN102148186A CN2010101104705A CN201010110470A CN102148186A CN 102148186 A CN102148186 A CN 102148186A CN 2010101104705 A CN2010101104705 A CN 2010101104705A CN 201010110470 A CN201010110470 A CN 201010110470A CN 102148186 A CN102148186 A CN 102148186A
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Abstract
The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps of: providing a front end device layer; forming an etching stop layer on the surface of the front end device layer; forming an interlayer dielectric layer on the surface of the etching stop layer; etching the interlayer dielectric layer and the etching stop layer by using a first mask to form a first through hole; forming a first metal layer in the first through hole; forming a first transition layer on the surfaces of the first metal layer and the interlayer dielectric layer; forming a second metal layer on the surface of the first transition layer; forming a second transition layer on the surface of the second metal layer; etching the second transition layer, the second metal layer and the first transition layer in sequence by using a second mask; forming a passivation layer on the surfaces of the interlayer dielectric layer and the second transition layer; and etching the passivation layer above the second transition layer by using a third mask to form a passivation layer through hole.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of methods of making semiconductor devices.
Background technology
The performance of high-end little process chip more and more is subjected to the restriction of the signal transferring lag in the interconnection wiring, and each equipment room that this interconnection wiring is used in this chip keeps connecting.In the interconnection that is referred to as backend process (BEOL) usually, the delay in these leads is represented by the product of associated resistance R and capacitor C.Along with improving constantly of chip integration, copper has replaced aluminium becomes the main flow interconnection technique of very lagre scale integrated circuit (VLSIC) in making.As the substitute of aluminium, copper conductor can reduce interconnection impedance, reduces power consumption and cost, improves integrated level, device density and the clock frequency of chip.When adopting copper to replace aluminium to reduce R in BEOL wiring, the minimizing of C can realize by reducing around the dielectric constant of the dielectric of interconnection wiring.Adopted the IMD that inter-metal dielectric (IMD) is changed over lower k from silicon dioxide (dielectric constant k is about 4), as fluoro silicon dioxide (k is about 3.6) and spin coating forms by CVD or on film organosilicate (k is greatly about 2.7～3.2), with the electric capacity of further reduction BEOL.In the technology of making semiconductor interconnect structure, the aluminum cushion layer that the aluminium lamination of last layer patternization forms array is that I/O (I/O) or power supply/ground signalling provide connection.
The method of traditional making interconnection structure is shown in Figure 1A to 1F.
At first, shown in Figure 1A, one front end device layer 101 is provided, this front end device layer 101 comprises formed device architecture layer in the preorder technology, metal interconnect structure layer etc. for example, the concrete conductor layer 100 that is exemplified as is formed in the front end device layer 101, and conductor layer 100 is the metal level that need be drawn out to device surface, for example copper.Form first etching stop layer 102 on front end device layer 101, material can be chosen as silicon nitride, and generation type can be chosen as CVD (chemical vapour deposition (CVD)) method.Then, form one deck interlayer dielectric layer 103 on the surface of first etching stop layer 102, material can be but be not limited to a kind of or its combination in silica, carborundum, silicon nitride, carbon silicon oxide compound, the nitrogen-doped silicon carbide.
Then, shown in Figure 1B, use Damascus technics, adopt the first mask plate (not shown) earlier, interlayer dielectric layer 103 is carried out etching, form through hole with the dry etching method.Adopt the second mask plate (not shown) again, interlayer dielectric layer 103 is carried out dry etching, form Damascus through hole 104.Again first etching stop layer 102 is carried out etching, with first etching stop layer, 102 openings.
Then, shown in Fig. 1 C, adopt and electroplate or the CVD method, in Damascus through hole 104, fill the copper metal, and adopt chemico-mechanical polishing (CMP) technology, make the top of copper metal concordant, form the first metal layer 105 with the top of interlayer dielectric layer 103.
Next, shown in Fig. 1 D, at interlayer dielectric layer 103 and deposition one deck second etching stop layer 106 above the first metal layer 105, material can be but be not limited to silicon nitride.Then form first passivation layer 107 on the surface of second etching stop layer 106.Adopt the 3rd mask plate (not shown), use the dry etching method, etching first passivation layer 107 and second etching stop layer 106 form first through hole 108 successively.
Then, shown in Fig. 1 E, deposition one deck tantalum nitride 109 in first through hole 108, at the surface deposition layer of metal layer of first through hole 108 and first passivation layer 107, material is chosen as aluminium then.Form one deck titanium nitride layer on the surface of aluminum metal then.Adopt the 4th mask plate (not shown), successively titanium nitride layer and metal level are carried out etching, form aluminum cushion layer 110 and titanium nitride layer 111 with pattern.
Next, shown in Fig. 1 F, the mode on the surface of the titanium nitride layer 111 and first passivation layer with CVD forms second passivation layer 112, adopts the CVD method to form layer protective layer 113 on the surface of second passivation layer, and material can be but be not limited to silicon nitride.Adopt the 5th mask plate (not shown), successively the protective layer 113 and second passivation layer 112 are carried out etching, form second through hole 114, expose titanium nitride layer 111, so that carry out follow-up technologies such as detection.
Yet the manufacture method of this traditional interconnection structure makes that the cost of manufacture of semiconductor device is higher.This be because, the price of the mask that is adopted in the interconnection process is very expensive, and generally can use five masks in traditional interconnection process, this has increased the cost of making semiconductor device greatly, changing lamina membranacea has also increased the step that technology is made.And owing to need carry out multiple etching technology, not only improved the cost of manufacture of semiconductor device more, make product not have competitiveness, more can cause potential harm to the structure of semiconductor device owing to etching technics, plasma damage etc. for example, this can reduce the yields of semiconductor device, destroys the overall performance of semiconductor device.
Therefore, need a kind of method, can make the interconnection structure in the semiconductor device better, its production cost is descended, work simplification so that improve the overall performance of semiconductor device, improves yields.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to make the interconnection structure in the semiconductor device better, the present invention proposes the manufacture method of interconnection structure in a kind of semiconductor device, comprise step: provide a front end device layer; Surface at described front end device layer forms one deck etching stop layer; Surface at described etching stop layer forms one deck interlayer dielectric layer; Adopt first mask that described interlayer dielectric layer and described etching stop layer are carried out etching, form first through hole; In described first through hole, form the first metal layer; Form first transition zone on the surface of described the first metal layer and described interlayer dielectric layer; Form second metal level on the surface of described first transition zone; Form second transition zone on the surface of described second metal level; Adopt second mask, successively etching second transition zone, second metal level and first transition zone; Surface at described interlayer dielectric layer and described second transition zone forms one deck passivation layer; Adopt the 3rd mask etching passivation layer above described second transition zone, form the passivation layer through hole.
Preferably, also comprise,
Surface at described passivation layer also forms layer protective layer, when adopting described the 3rd mask to carry out etching described passivation layer and described protective layer is carried out etching together.
Preferably, the material of described second metal level is an aluminium.
Preferably, the material of described first transition zone is a tantalum nitride, and the material of described second transition zone is a titanium nitride.
Preferably, described front end device layer includes a conductor layer, and the below that described conductor layer is positioned at described the first metal layer contacts with described the first metal layer.
Preferably, second transition zone after the described etching, described second metal level and described first transition zone cover described the first metal layer and the described interlayer dielectric layer of part.
The present invention also provides a kind of semiconductor device, comprising: the front end device layer; One deck etching stop layer that forms on the surface of described front end device layer; One deck interlayer dielectric layer that forms on the surface of described etching stop layer; First through hole that connects described etching stop layer upper and lower surface and connect described interlayer dielectric layer upper and lower surface; The first metal layer that in described first through hole, forms; First transition zone that forms on the surface of described the first metal layer and the described interlayer dielectric layer of part; Second metal level that forms on the surface of described first transition zone; Second transition zone in described second layer on surface of metal formation; The passivation layer that forms on the surface of described interlayer dielectric layer and described second transition zone; On described second transition zone and connect the passivation layer through hole of described passivation layer upper and lower surface.
Preferably, also comprise,
The layer protective layer that also forms on the surface of described passivation layer also has the protective layer through hole that run through passivation layer consistent with the passivation layer lead to the hole site.
Preferably, the material of described second metal level is an aluminium.
Preferably, the material of described first transition zone is a tantalum nitride, and the material of described second transition zone is a titanium nitride.
Preferably, the conductor layer that described front end device layer includes, the described conductor layer below that is positioned at described the first metal layer contacts with described the first metal layer.
Preferably, described second transition zone, described second metal level and described first transition zone cover described the first metal layer and the described interlayer dielectric layer of part.
According to the present invention, can make the interconnection structure in the semiconductor device better, its production cost is descended, work simplification so that improve the overall performance of semiconductor device, improves yields.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 F is the cross-sectional view of the semiconductor device of traditional making interconnection structure;
Fig. 2 A to 2E is the cross-sectional view according to the making semiconductor interconnect structure of the embodiment of one aspect of the invention;
Fig. 3 is the process chart of making according to the making semiconductor interconnect structure of the embodiment of one aspect of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention adopts new process to make semiconductor device.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
With reference to Fig. 2 A to Fig. 2 E, the method according to the making semiconductor interconnect structure of the embodiment of one aspect of the invention is shown.
Shown in Fig. 2 A, provide a front end device layer 201.This front end device layer 201 comprises formed device architecture layer in the preorder technology, the metal interconnect structure layer that for example on substrate, forms etc., wherein substrate can be chosen as the silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, it also can be silicon-on-insulator (SOI), the material that can also comprise other, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.Be formed with a conductor layer 200 in the front end device layer 201.Conductor layer 200 is the metal levels that need be drawn out to device surface, copper for example, and conductor layer 200 is positioned at the below of the first metal layer that next will deposit and contacts with the first metal layer.。Surface at front end device layer 201 forms one deck etching stop layer 202, and material can be chosen as silicon nitride, and generation type can be chosen as the CVD method.Then, form one deck interlayer dielectric layer 203 on the surface of etching stop layer 202, material can be but be not limited to a kind of or its combination in silica, carborundum, silicon nitride, carbon silicon oxide compound, the nitrogen-doped silicon carbide.
Shown in Fig. 2 B, adopt the first mask plate (not shown), interlayer dielectric layer 203 and etching stop layer 202 are carried out etching, form first through hole 204, promptly connect first through hole 204 of interlayer dielectric layer 203 upper and lower surfaces and etching stop layer 202 upper and lower surfaces, make interlayer dielectric layer 203 and etching stop layer 202 have patterns of openings.
Shown in Fig. 2 C, adopt CVD or PVD method, in first through hole 204, form the first metal layer 205, material is chosen as copper.Form first transition zone 206 on the surface of the first metal layer 205, thickness is approximately 500～1000 dusts, is preferably 850 dusts.First transition zone 206 can be individual layer or multilayer, can adopt PVD (physical vapour deposition (PVD)), CVD, vacuum evaporation, pulsed laser deposition (PLD) or other existing plated film mode to form.Material can be but be not limited to tantalum nitride.For example, select for use the PVD method to prepare first transition zone 203, the employing metal tantalum is a target, and the atmosphere of deposition is the mist of argon gas and nitrogen, forms tantalum nitride down at 100～120 degrees centigrade.The effect of first transition zone 206 is that can to make with copper be the first metal layer 205 of material and what next will form is to form good transition between second metal level 207 of material with aluminium, and has stopped the mutual diffusion between copper metal and the aluminum metal.The material that forms one deck second metal level 207, the second metal levels 207 on the surface of first transition zone 206 is chosen as aluminium, and thickness is approximately 5000～8000 dusts.Then form second transition zone 208 on the surface of second metal level 207, material can be but be not limited to titanium nitride that generation type can be PVD, CVD, vacuum evaporation, pulsed laser deposition or other existing plated film mode.Second transition zone 208 can protect second metal level 207 better.At surface applied one deck photoresist layer of second transition zone 208, adopt the second mask plate (not shown) then, form first photoresist layer 209 by patterns such as exposure imagings with pattern.
Shown in Fig. 2 D, with first photoresist layer 209 is mask, etching second transition zone 208, second metal level 207 and first transition zone 206 successively form and have second transition zone 208 ' of pattern, first transition zone 206 ' that has second metal level 207 ' of pattern and have pattern.Second transition zone 208 ' after the etching, second metal level 207 ' and first transition zone 206 ' cover described the first metal layer 205 and the described interlayer dielectric layer 203 of part.Used lithographic method adopts dry etching.Then, adopt the ashing mode to remove first photoresist layer 209.
Shown in Fig. 2 E, surface at second transition zone 208 ' and interlayer dielectric layer 203 forms one deck passivation layer 210, generation type is CVD method or PVD method, and thickness is approximately 7000～10000 dusts, and material can be but be not limited to silicon nitride, silica, silicon oxynitride, polyimides etc.Passivation layer 210 can be individual layer or sandwich construction, for example, using plasma chemical vapour deposition (CVD) (PECVD), sandwich construction comprises silicon nitride, silica and/or silicon oxynitride.Then, form layer protective layer 211 on the surface of passivation layer 210 with CVD or PVD mode, material can be but be not limited to silicon nitride.Then; adopt the 3rd mask (not shown); utilize the dry etching method successively protective layer 211 and passivation layer 210 to be carried out etching; form second through hole 212 in the top of second transition zone 208 '; second through hole 212 that promptly runs through passivation layer 210 and protective layer 211 makes passivation layer 210 and protective layer 211 have patterns of openings, and the hole of running through passivation layer 210 is the passivation layer through hole; the hole of running through protective layer 211 is the protective layer through hole, and passivation layer through hole and protective layer through hole have constituted second through hole 212 jointly.Then, carry out follow-up packaging technology, so that finish the making of entire chip.
Interconnection structure according to the present embodiment making, three mask plates have only been adopted, first mask plate that adopts when promptly forming first through hole, second mask plate that is adopted when making first photoresist layer 209 and the 3rd mask plate that is adopted when forming second through hole 212 with pattern, this has saved two mask plates compared with five mask plates that adopted in the traditional handicraft, has saved cost of manufacture greatly.And, reduced cost of manufacture more because the minimizing of the mask plate that is adopted makes associated processing step reduce.
The present invention adopts copper in the aluminium substitution traditional handicraft as the top layer metallic layer in the interconnection structure, be the first metal layer 105 in the traditional handicraft, this makes top layer metallic layer and passivation layer associativity better, and this helps follow-up packaging technology, and because the characteristic of aluminium itself is easier to patterning.Present embodiment merges making with aluminum cushion layer in the traditional manufacturing technique and top layer metallic layer, be in the traditional handicraft the first metal layer 105 and aluminum cushion layer 110 to realize with second metal level 207 in the present embodiment, this has significantly reduced processing step, saved cost of manufacture, shortened the production cycle, made output higher.
The flow chart of Fig. 3 shows making and adopts the process chart that improves technology making semiconductor interconnect structure according to an embodiment of the invention.In step 301, provide a front end device layer.In step 302, form one deck etching stop layer on the surface of front end device layer, form one deck interlayer dielectric layer on the surface of etching stop layer.In step 303, adopt first mask plate that interlayer dielectric layer and etching stop layer are carried out etching, form first through hole.In step 304, in first through hole, form the first metal layer, form first transition zone on the surface of the first metal layer, form one deck second metal level on the surface of first transition zone, form second transition zone on the surface of second metal level.In step 305,, form first photoresist layer by patterns such as exposure imagings with pattern at surface applied one deck photoresist layer of second transition zone.In step 306, be mask with first photoresist layer, etching second transition zone, second metal level and first transition zone successively.In step 307, adopt the ashing mode to remove first photoresist layer.In step 308, form one deck passivation layer on the surface of second transition zone and interlayer dielectric layer, form layer protective layer on the surface of passivation layer.In step 309, adopt the 3rd mask successively protective layer and passivation layer to be carried out etching, form second through hole.
Adopt the semiconductor device of the semiconductor interconnect structure that new process makes to can be applicable in the multiple integrated circuit (IC) according to having of as above embodiment manufacturing.According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (14)
1. methods of making semiconductor devices comprises step:
One front end device layer is provided;
Surface at described front end device layer forms one deck etching stop layer;
Surface at described etching stop layer forms one deck interlayer dielectric layer;
Adopt first mask that described interlayer dielectric layer and described etching stop layer are carried out etching, form first through hole;
In described first through hole, form the first metal layer;
Form first transition zone on the surface of described the first metal layer and described interlayer dielectric layer;
Form second metal level on the surface of described first transition zone;
Form second transition zone on the surface of described second metal level;
Adopt second mask, successively etching second transition zone, second metal level and first transition zone;
Surface at described interlayer dielectric layer and described second transition zone forms one deck passivation layer;
Adopt the 3rd mask etching passivation layer above described second transition zone, form the passivation layer through hole.
2. method as claimed in claim 1 also comprises,
Surface at described passivation layer also forms layer protective layer, when adopting described the 3rd mask to carry out etching described passivation layer and described protective layer is carried out etching together.
3. method as claimed in claim 1 is characterized in that, the material of described second metal level is an aluminium.
4. method as claimed in claim 1 is characterized in that, the material of described first transition zone is a tantalum nitride, and the material of described second transition zone is a titanium nitride.
5. method as claimed in claim 1 is characterized in that, described front end device layer includes a conductor layer, and the below that described conductor layer is positioned at described the first metal layer contacts with described the first metal layer.
6. method as claimed in claim 1 is characterized in that, second transition zone after the described etching, described second metal level and described first transition zone cover described the first metal layer and the described interlayer dielectric layer of part.
7. semiconductor device comprises:
The front end device layer;
One deck etching stop layer that forms on the surface of described front end device layer;
One deck interlayer dielectric layer that forms on the surface of described etching stop layer;
First through hole that connects described etching stop layer upper and lower surface and connect described interlayer dielectric layer upper and lower surface;
The first metal layer that in described first through hole, forms;
First transition zone that forms on the surface of described the first metal layer and the described interlayer dielectric layer of part;
Second metal level that forms on the surface of described first transition zone;
Second transition zone in described second layer on surface of metal formation;
The passivation layer that forms on the surface of described interlayer dielectric layer and described second transition zone;
On described second transition zone and connect the passivation layer through hole of described passivation layer upper and lower surface.
8. the device described in claim 7 also comprises,
The layer protective layer that also forms on the surface of described passivation layer also has the protective layer through hole that run through passivation layer consistent with the passivation layer lead to the hole site.
9. the device described in claim 7 is characterized in that, the material of described second metal level is an aluminium.
10. the device described in claim 7 is characterized in that, the material of described first transition zone is a tantalum nitride, and the material of described second transition zone is a titanium nitride.
11. the device described in claim 7 is characterized in that, the below that the conductor layer that described front end device layer includes, described conductor layer are positioned at described the first metal layer contacts with described the first metal layer.
12. the device described in claim 7 is characterized in that, described second transition zone, described second metal level and described first transition zone cover described the first metal layer and the described interlayer dielectric layer of part.
13. an integrated circuit that comprises the semiconductor device of making by method as claimed in claim 1, wherein integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
14. an electronic equipment that comprises the semiconductor device of making by method as claimed in claim 1, wherein electronic equipment personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| CN111128934A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad structure and device comprising aluminum pad structure |
| CN112752994A (en) * | 2019-08-30 | 2021-05-04 | 京东方科技集团股份有限公司 | Back plate, backlight source, display device and manufacturing method of back plate |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5275695A (en) * | 1992-12-18 | 1994-01-04 | International Business Machines Corporation | Process for generating beveled edges |
| US6218078B1 (en) * | 1997-09-24 | 2001-04-17 | Advanced Micro Devices, Inc. | Creation of an etch hardmask by spin-on technique |
| US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
| US6465297B1 (en) * | 2000-10-05 | 2002-10-15 | Motorola, Inc. | Method of manufacturing a semiconductor component having a capacitor |
| CN100539079C (en) * | 2006-12-27 | 2009-09-09 | 中芯国际集成电路制造(上海)有限公司 | Make the method for DRAM capacitor arrangement |
| CN100539016C (en) * | 2007-04-24 | 2009-09-09 | 中芯国际集成电路制造(上海)有限公司 | MIM capacitor and manufacture method thereof |
| CN101364565A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN101533767B (en) * | 2008-12-31 | 2013-07-31 | 昆山锐芯微电子有限公司 | Semiconductor device, metal-insulator-metal capacitor and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112752994A (en) * | 2019-08-30 | 2021-05-04 | 京东方科技集团股份有限公司 | Back plate, backlight source, display device and manufacturing method of back plate |
| CN112752994B (en) * | 2019-08-30 | 2022-08-02 | 京东方科技集团股份有限公司 | Back plate, backlight source, display device and manufacturing method of back plate |
| CN111128934A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad structure and device comprising aluminum pad structure |
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