CN102148166A - Method and structure for filling clearances among stacked multi-layer wafers - Google Patents
Method and structure for filling clearances among stacked multi-layer wafers Download PDFInfo
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- CN102148166A CN102148166A CN 201010111420 CN201010111420A CN102148166A CN 102148166 A CN102148166 A CN 102148166A CN 201010111420 CN201010111420 CN 201010111420 CN 201010111420 A CN201010111420 A CN 201010111420A CN 102148166 A CN102148166 A CN 102148166A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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Abstract
The invention discloses a method and a structure for filling clearances among stacked multi-layer wafers. According to the method, a wafer stacking structure is provided. The wafer stacking structure comprises a substrate and a plurality of wafers which are stacked on the substrate vertically. At least one primer clearance is formed between any two stacked wafers, and a height difference is formed between the primer clearance and the substrate. Then, the wafer stacking structure is overturned, and the wafers of the wafer stacking structure are dipped into an underfill material, wherein the underfill material is stored in an underfill material storage tank and keeps flowing to fill in the primer clearance. Finally, the wafer stacking structure is taken out and heated to solidify the underfill material in the primer clearance. Therefore, the problem that the clearances among the conventional stacked multi-layer wafers cannot be filled by dispensing can be solved, and a plurality of primer clearances can be filled once, so that production efficiency is improved greatly.
Description
Technical field
The present invention relates to a kind of manufacturing technology of semiconductor device, particularly relate to fill method and structure that a kind of multi-layer crystal chip piles up the gap.
Background technology
Existing crystalline substance (flip chip) or wafer scale wafer size encapsulation (the Wafer Level Chip ScalePackage of covering; WL-CSP) product is when dropping with reliability-test; solder joint between wafer and substrate suffers the acute variation of external force and thermal stress easily and produces rupture failure; and then cause the damage or the inner electrically connection failure of IC wafer, the former capital need use underfill (underfill material) to come the seal protection solder joint.The formation method of tradition underfill is to put the side of glue (dispensing) at substrate earlier, and suitably heated substrates makes underfill that flowability be arranged, and utilizes capillarity to make underfill flow to the gap of IC wafer and substrate.
In advanced encapsulation technology, the solid of chip elements (hereinafter to be referred as wafer) such as a plurality of for example chip bondings or wafer scale wafer size encapsulation kenel is stacked as inexorable trend, can utilize silicon perforation (Through Silicon Via, TSV) reach the electric connection that is stacked wafer, yet can be formed on the multilayer primer gap of differing heights position on the substrate between wafer and the wafer, and produce difference in height with substrate, so can't use a glue (dispensing) mode between three-dimensional stacked wafer, to insert underfill.
As shown in Figure 1, Fig. 1 is the schematic cross-section of existing known wafer combining structure primer when filling.In the wafer combining structure 110 that existing known amorphous sheet solid is piled up is to form underfill in a glue mode, by the side that a dispensing needle head 121 provides mobile and uncured underfill 120 and point to be coated in substrate 111, the substrate side brilliant wafer 112 that engages that must not be covered covers.Substrate 111 must be heated to can controlled temperature, make underfill 120 have that high fluidity is unlikely again to be cured, utilize its high fluidity and under predetermined temperature, produce capillarity in the primer gap between this substrate 111 and this wafer 112, and then fill up the primer gap, to seal for example splicing ear 114 of projection.Under a higher temperature, make after these underfill 120 curing, just finished the wafer combining structure 110 of flip chip type attitude.
Yet, when piling up, the wafer solid can form multilayer primer gap, and one difference in height is arranged with substrate, underfill just can't be formed in the multilayer primer gap in the spot printing mode, and temperature only according to the uncontrollable underfill of heated substrates, when the variation of temperature gradient or difference, capillary filling effect is also inequality, so form space (void) in the multilayer primer gap between the wafer easily, can be expanded and explosion in the space in follow-up high temperature test or manufacturing environment, unfavorable to the reliability of product.
This shows that above-mentioned existing multi-layer crystal chip piles up the fill method in gap and structure at method, product structure and use, and obviously still has inconvenience and defective, and demands urgently further being improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and conventional method and product do not have appropriate method and structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found fill method and the structure that a kind of new multi-layer crystal chip piles up the gap, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
Main purpose of the present invention is, overcome existing multi-layer crystal chip and pile up the fill method in gap and the defective that structure exists, and provide a kind of new multi-layer crystal chip to pile up the fill method and the structure in gap, technical problem to be solved is to make it can solve the primer gap that existing known multi-layer crystal chip piles up with substrate one difference in height to be arranged and can't put the problem of glue filling, is very suitable for practicality.
Another object of the present invention is to, overcome existing multi-layer crystal chip and pile up the fill method in gap and the defective that structure exists, and provide a kind of new multi-layer crystal chip to pile up the fill method and the structure in gap, technical problem to be solved is to make it break through the existing known restriction that glue only can be filled one deck primer gap with capillarity of putting on heated substrates, a plurality of primers gap is once filled finishes, significantly promoting production efficiency, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of multi-layer crystal chip that proposes according to the present invention piles up the fill method in gap, mainly comprise following steps: at first, one wafer-to-wafer stacking is provided, it comprises a substrate and a plurality of solid and is stacked on wafer on this substrate, be formed with at least one first primer gap between the folded wafer of two two-phases, itself and this substrate has a difference in height.Then, those wafers that overturn this wafer-to-wafer stacking and soak this wafer-to-wafer stacking are in a underfill, and wherein this underfill is to store in a storage glue groove and keep flow regime, to fill up this first primer gap.Afterwards, take out this wafer-to-wafer stacking.At last, heat this wafer-to-wafer stacking, to be solidificated in the underfill in this first primer gap.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein in the step of this wafer-to-wafer stacking was provided, this wafer-to-wafer stacking can more comprise a plurality of splicing ears that are positioned at this first primer gap, to electrically connect those wafers.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein each wafer can be provided with a plurality of silicon perforation that vertically electrically conduct.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein those wafers can be overlay crystal chip, and is provided with a reconfiguration line layer at the back side of each wafer.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein after taking out this wafer-to-wafer stacking, this underfill can those wafers of complete coating.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein in above-mentioned immersion process, a lower surface of this substrate can not covered by this underfill.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein said storage glue groove can be cylindrical shape, so that this underfill flows into the whirlpool shape.
Aforesaid multi-layer crystal chip piles up the fill method in gap, wherein is formed with one second primer gap between near the wafer of this substrate and this substrate, and in above-mentioned immersion process, this underfill can more fill up this second primer gap.
Aforesaid multi-layer crystal chip piles up the fill method in gap, and wherein in above-mentioned upset and soaking step, this wafer-to-wafer stacking can be in vacuum state in advance.
The object of the invention to solve the technical problems also realizes by the following technical solutions.Pile up the interstitital texture in gap according to a kind of multi-layer crystal chip of the present invention's proposition, it comprises: a wafer-to-wafer stacking, it comprises a substrate and a plurality of solid and is stacked on wafer on this substrate, between the folded wafer of two two-phases, be formed with at least one first primer gap, and one difference in height arranged with this substrate; And the underfill of an immersion formation, fill up this first primer gap.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid multi-layer crystal chip piles up the interstitital texture in gap, more comprises a plurality of splicing ears that are positioned at this first primer gap, to electrically connect those wafers.
Aforesaid multi-layer crystal chip piles up the interstitital texture in gap, and wherein each wafer is to be provided with a plurality of silicon perforation that vertically electrically conduct.
Aforesaid multi-layer crystal chip piles up the interstitital texture in gap, and wherein those wafers are overlay crystal chip, and is provided with a reconfiguration line layer at the back side of each wafer.
Aforesaid multi-layer crystal chip piles up the interstitital texture in gap, and wherein said underfill is those wafers of complete coating.
Aforesaid multi-layer crystal chip piles up the interstitital texture in gap, wherein is formed with one second primer gap between near the wafer of this substrate and this substrate, and this underfill more fills up this second primer gap.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, fill method and structure that multi-layer crystal chip of the present invention piles up the gap have following advantage and beneficial effect at least:
One, the present invention is soaked in by the wafer that makes wafer-to-wafer stacking in the underfill of flow regime as one of them technological means, has overcome that primer gap that existing known multi-layer crystal chip piles up and substrate have a difference in height and can't be with a problem that the glue mode is filled.
Two, the present invention is soaked in by the wafer that makes wafer-to-wafer stacking in the underfill of flow regime as one of them technological means, underfill is because of storing in storage glue groove and keeping flow regime when filling, the temperature of underfill is controlled, be difficult for producing the space, broken through the existing known restriction that glue only can be filled one deck primer gap with capillarity of on heated substrates, putting, a plurality of primers gap is once filled finish, significantly to promote production efficiency.
Three, the present invention can be by the complete coating wafer of underfill that will soak formation as one of them technological means, make wafer and electrical contact thereof avoid exposing and contact to air and then produce oxidation, and avoided attaching foreign object such as dust and cause problem of short-circuit to take place, so can omit existing known mould adhesive body, reach the slim encapsulation that the wafer solid is piled up.
In sum, the invention relates to that a kind of multi-layer crystal chip piles up the fill method and the structure in gap.According to this method, a wafer-to-wafer stacking is provided, comprise a substrate and a plurality of solid and be stacked on wafer on the substrate.Between the folded wafer of two two-phases, be formed with at least one primer gap, and one difference in height arranged with substrate.Then, the wafer that overturns wafer-to-wafer stacking and soak wafer-to-wafer stacking is in a underfill, and wherein underfill stores in a storage glue groove and keeps flow regime, to fill up the primer gap.Afterwards, take out wafer-to-wafer stacking and heating, to be solidificated in the underfill in the primer gap.By this, can solve the gap that existing known multi-layer crystal chip piles up and to put the problem that glue is filled, and a plurality of primers gap is once filled finish, significantly to promote production efficiency.The present invention has obvious improvement technically, has tangible good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic cross-section of existing known wafer combining structure primer when filling.
Fig. 2 is the schematic cross-section that the wafer-to-wafer stacking that is provided in the fill method in gap is provided according to a kind of multi-layer crystal chip of first specific embodiment of the present invention.
Fig. 3 A and Fig. 3 B are that the multi-layer crystal chip according to first specific embodiment of the present invention piles up upset wafer-to-wafer stacking in the fill method in gap and preparation and is soaked in schematic top plan view and schematic cross-section in the storage glue groove.
Fig. 4 is that the multi-layer crystal chip according to first specific embodiment of the present invention piles up in the fill method in gap at the schematic cross-section of wafer in underfill that soaks wafer-to-wafer stacking.
Fig. 5 be the multi-layer crystal chip according to first specific embodiment of the present invention pile up take out in the fill method in gap with the heated chip stacked structure after schematic cross-section.
Fig. 6 is that the multi-layer crystal chip that the multi-layer crystal chip according to first specific embodiment of the present invention piles up the fill method manufacturing in gap piles up the schematic cross-section of the interstitital texture in gap.
Fig. 7 is that the multi-layer crystal chip that the another kind of multi-layer crystal chip according to second specific embodiment of the present invention piles up the fill method manufacturing in gap piles up the schematic cross-section of the interstitital texture in gap.
Fig. 8 is that the multi-layer crystal chip according to second specific embodiment of the present invention piles up in the fill method in gap at the schematic cross-section of wafer in underfill that soaks wafer-to-wafer stacking.
110: wafer combining structure 111: substrate
112: wafer 114: splicing ear
120: underfill 121: dispensing needle head
200: multi-layer crystal chip piles up the interstitital texture 210 in gap: wafer-to-wafer stacking
211: substrate 211A: upper surface
211B: lower surface 212: wafer
212A: silicon perforation 213: splicing ear
214: splicing ear 220: underfill
221: storage glue groove 222: underfill
223: blender 230: suction nozzle
300: multi-layer crystal chip piles up the interstitital texture 312A in gap: reconfiguration line layer
S1: the first primer gap S2: the second primer gap
H: the first primer gap is to the difference in height of substrate
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the multi-layer crystal chip that foundation the present invention is proposed piles up fill method and its embodiment of structure, method, step, structure, feature and the effect thereof in gap, describe in detail as after.
Some embodiments of the present invention will be described in detail as follows.Yet except following description, the present invention can also be widely implements at other embodiment, and protection scope of the present invention is not subjected to the qualification of embodiment, and its protection range with claim is as the criterion.Moreover for clearer description being provided and being more readily understood the present invention, graphic interior each several part is not drawn according to its relative size, and some size is compared with other scale dependents and exaggerated; Incoherent detail section does not show fully yet, in the hope of graphic succinct.
The illustrating of fill method that a kind of multi-layer crystal chip of foundation first specific embodiment of the present invention piles up the gap sees also Fig. 2 to shown in Figure 6, wherein, Fig. 2 is the schematic cross-section that the wafer-to-wafer stacking that is provided in the fill method in gap is provided according to a kind of multi-layer crystal chip of first specific embodiment of the present invention.Fig. 3 A and Fig. 3 B are that the multi-layer crystal chip according to first specific embodiment of the present invention piles up upset wafer-to-wafer stacking in the fill method in gap and preparation and is soaked in schematic top plan view and schematic cross-section in the storage glue groove.Fig. 4 is that the multi-layer crystal chip according to first specific embodiment of the present invention piles up in the fill method in gap at the schematic cross-section of wafer in underfill that soaks wafer-to-wafer stacking.Fig. 5 be the multi-layer crystal chip according to first specific embodiment of the present invention pile up take out in the fill method in gap with the heated chip stacked structure after schematic cross-section.Fig. 6 is that the multi-layer crystal chip that the multi-layer crystal chip according to first specific embodiment of the present invention piles up the fill method manufacturing in gap piles up the schematic cross-section of the interstitital texture in gap.
The multi-layer crystal chip that the present invention discloses piles up the fill method in gap, mainly comprises following steps: at first, as shown in Figure 2, provide a wafer-to-wafer stacking 210.This wafer-to-wafer stacking 210 comprises a substrate 211 and a plurality of solids and is stacked on wafer 212 on this substrate 211.This substrate 211 has the effect of electrical transmission and bearing wafer, and (printed circuit board, PCB), ceramic circuit board or the wafer of a large-size, this substrate 211 has a upper surface 211A and a lower surface 211B to can be a printed circuit board (PCB).Those wafers 212 are this upper surface 211A that solid is stacked on this substrate 211.And the quantity of piling up of the wafer 212 of this wafer-to-wafer stacking 210 is what do not limit, can reach more than eight, reaches the memory body capacity or the expansion of function.In addition, those wafers 212 can be the identical semiconductor wafer of essence, have identical wafer size and structure.Usually those wafers 212 are overlay crystal chip or wafer scale wafer size packaging part.The splicing ear 213 that can utilize the silicon in the wafer to bore a hole between 212A and wafer between those wafers 212 reaches electrical interconnects.
Be formed with at least one first primer gap S1 between the folded wafer 212 of two two-phases, itself and this substrate 211 has a height difference H, and this height difference H is about the total height of below wafer and splicing ear 214, common thickness greater than a wafer.The first primer gap S1 is defined to be primer gap between wafer and wafer, is not included in the primer gap between wafer and the substrate.In addition, near being formed with one second primer gap S2 between the wafer 212 of this substrate 211 and this substrate 211.
Inside about this wafer-to-wafer stacking 210 electrically connects, and this wafer-to-wafer stacking 210 can more comprise a plurality of splicing ears 213 that are positioned at those first primers gap S1, to electrically connect those wafers 212.In addition, this wafer-to-wafer stacking 210 can more comprise a plurality of splicing ears 214 that are positioned at this second primer gap S2, to be electrically connected to this substrate 211.Those splicing ears 213 or/and the 214 active surface zones that can be positioned at those wafers 212, those wafers 212 can be upside-down mounting and towards this substrate 211.Specifically, those splicing ears 213,214 can be reflow projection (refl ow bump) or non-reflow projection (non-reflow bump), as solder projection, golden projection, copper bump, aluminium projection or conductive polymer projection, the shape of those splicing ears 213,214 can be square shape, cylindric, buttress shaft shape, hemispherical or spherical, can combine with the weld pad of wafer 212 or the contact of substrate 211 by hot pressing mode.Those splicing ears 213,214 can plating, electroless plating, evaporation, ball are put method (ball attach), plant ball method (ball placement), screen painting, au bump (Au studbumping) and scolder rifle (solder jet) form.Those splicing ears 213,214 have a height (for example 3-10 micron), are formed with this second primer gap S2 between those first primers gap S1 and undermost wafer 212 and this substrate 211 and be formed with between the wafer 212 that makes two two-phases fold.In addition, again as shown in Figure 2, each wafer 212 can be provided with a plurality of silicon perforation (Through Silicon Via that vertically electrically conduct, TSV) 212A, it is the through hole that through-wafer 212 is set in wafer 212, and in through hole filled conductive material, for example conducting resinl, scolder or other electric conducting material of spreading of electrodeposited coating, liquid state or the like.One splicing ear 213 or 214 and be positioned on the same vertical line can be set under each silicon perforation 212A, those wafer 212 vertical electrical conductings that solid is piled up, and can shorten signal transmission distance.
Then, see also shown in Fig. 3 A and Fig. 3 B, those wafers 212 that overturn this wafer-to-wafer stacking 210 and soak (dipping) this wafer-to-wafer stacking 210 are in a underfill 222, wherein this underfill 222 is to store in a storage glue groove 221 and keep flow regime, to fill up those first primers gap S1.In this step of present embodiment, this second primer gap S2 is filled simultaneously.This underfill 222 can be high fluidity liquid thermosetting insulating resin, for example can comprise epoxy compounds.Particularly, in this wafer-to-wafer stacking 210 of upset, be to utilize a suction nozzle 230 or sucker to fix this substrate 211 earlier in the mode of adsorbing this lower surface 211B, then, as shown in Figure 4, descend this suction nozzle 230 so that this wafer-to-wafer stacking 210 is dipped in this storage glue groove 221 the and soaking depth of this wafer-to-wafer stacking 210 of may command smoothly.Preferably, see also shown in Figure 4ly, in above-mentioned immersion process, this lower surface 211B of this substrate 211 can not covered by this underfill 222, with as the absorption surface that picks and places this wafer-to-wafer stacking 210.In the present embodiment, this substrate 211 can not exclusively immerse, but this second primer gap S2 also can be immersed in this underfill 222.
Please consult again shown in Fig. 3 A and Fig. 3 B, can insert smoothly among those first primers gap S1 and this second primer gap S2 for making this underfill 222, preferably, in this storage glue groove 221 blender 223 can be set, this blender 223 can be a stirring vane or stirring rod, the power with the motor of outside (figure does not draw) be coupling be located at after, can start this blender 223 rotations, these underfill 222 generations in this storage glue groove 221 are flowed, and help to fill the effect in gap.More preferably, as shown in Figure 3A, this storage glue groove 221 can be cylindrical shape, so that this underfill 222 flows into whirlpool shape (as the flow arrow of Fig. 3 A and Fig. 3 B), can make the peripheral flow speed stability of this underfill 222 and, be difficult for covering the lower surface 211B of this substrate 211 at the central liquid level stabilizing of the groove of this storage glue groove 221.Suitably controlled when the flow velocity and the temperature of this underfill 222, this underfill 222 is flowed among those first primers gap S1 and this second primer gap S2 equably.When filling, this underfill 222 is because of storing in this storage glue groove 221 and keeping flow regime, and the temperature of underfill 222 is controlled, be difficult for producing the space, use and break through the existing known restriction that glue only can be filled one deck primer gap with capillarity of on heated substrates, putting, a plurality of primers gap S1 or/and S2 are once filled finish, significantly to promote production efficiency.
In addition, in a preferred embodiment, in above-mentioned upset and soaking step, this wafer-to-wafer stacking 210 can be in vacuum state in advance, and after those first primers gap S1 and this second primer gap S2 are inserted via this underfill 222, avoid space (void) to produce.Perhaps, can under atmospheric pressure, shake this wafer-to-wafer stacking 210, to discharge the space bubble.
Afterwards, as shown in Figure 5, take out this wafer-to-wafer stacking 210, make it break away from this storage glue groove 221.After taking out this wafer-to-wafer stacking 210, be built-up in those wafers 212 of the just complete coating of underfill 220 of this wafer-to-wafer stacking 210, the active surface, side and the back side that comprise those wafers 212, particularly coat the back side of the superiors' wafer 212, and this upper surface 211A of this substrate 211 can be capped also.In addition, the figure number of the underfill that has attached is denoted as 220, and the underfill 222 of using and being stored in this storage glue groove 221 is made difference.So after finishing soaking step and taking out this wafer-to-wafer stacking 210, this underfill 220 is to fill up those first primers gap S1 and this second primer gap S2, overcomes that primer gap that existing known multi-layer crystal chip piles up and substrate have a difference in height and can't be with a problem that the glue mode is filled.
At last, as shown in Figure 5, heat this wafer-to-wafer stacking 210, to be solidificated in the underfill 220 in those first primers gap S1.The temperature that is heating and curing should be stored up the temperature of glue groove 221 greater than this, so that this underfill 220 produces irreversible permanent curing reaction, makes between those wafers 212 and the void-free tight filling of energy between lowermost layer wafer 212 and this substrate 211.At this moment; this underfill 220 is rendered as the solid resin that sealing is good, chemical stability is high and insulate; the splicing ear 213 and 214 of salable those wafers 212 and conduct welding end points; can not be subjected to the invasion of the thermal stress that difference caused of thermal coefficient of expansion between this wafer 212 and this substrate 211 and environmental contaminants and be damaged, protect between each splicing ear 213,214 and the silicon perforation 212A yet not because of exposing the situation that is short-circuited.Therefore, those wafers 212 of the complete coating of these underfill 220 energy after the curing and this upper surface 211A of this substrate 211, especially the back side of the superiors' wafer 212, promptly cover the end points of the silicon perforation 212A of the superiors' wafer 212 at surface exposure, make those wafers 212 and electrical contact thereof avoid exposing and contact to air and then produce oxidation, and avoid attaching foreign object such as dust and cause problem of short-circuit to take place, so can omit existing known mould adhesive body, reach the slim encapsulation that the wafer solid is piled up.
As shown in Figure 6, this wafer-to-wafer stacking 210 then forms the interstitital texture 200 that multi-layer crystal chip of the present invention piles up the gap after curing schedule.The interstitital texture 200 that this multi-layer crystal chip piles up the gap is to comprise an above-mentioned wafer-to-wafer stacking 210 and to soak the underfill 220 that forms, and its thin bilge construction is stated in said method, is no longer given unnecessary details at this.
According to first embodiment of the invention, above-mentioned steps is except can be embodied on the single substrate, the fill method that multi-layer crystal chip of the present invention piles up the gap also may be implemented in the substrate strip stage, promptly this substrate 211 is a substrate strip, and solid is piled up a plurality of wafers 212 in each cellular zone, can be applicable to make in a large number the slim packaging operation of semiconductor device.Utilize multi-layer crystal chip of the present invention to pile up the fill method in gap, can carry out gap filler technology, can avoid in wafer-to-wafer stacking 210, producing bubble simultaneously again the above wafer stacking body of two groups (containing) simultaneously.Even have excessive glue phenomenon can first overflow to the no encapsulation region of the lower surface of substrate strip, can be not directly do not cause excessive glue at the lower surface of base board unit.In immersion process, all wafers can the complete covering by the underfill in the same accumulator tank, uses the output capacity, reliability and the useful life that promote semiconductor device more.
The explanation that the another kind of multi-layer crystal chip of foundation second specific embodiment of the present invention piles up the fill method in gap sees also Fig. 7 and shown in Figure 8, wherein, Fig. 7 is that the multi-layer crystal chip that another kind of multi-layer crystal chip according to second specific embodiment of the present invention piles up the fill method manufacturing in gap piles up the schematic cross-section of the interstitital texture in gap.Fig. 8 is that the multi-layer crystal chip according to second specific embodiment of the present invention piles up in the fill method in gap at the schematic cross-section of wafer in underfill that soaks wafer-to-wafer stacking.This multi-layer crystal chip piles up the fill method in gap, and the key step and first embodiment are roughly the same.At first, provide a wafer-to-wafer stacking 210.Then, the wafer 212 that overturns this wafer-to-wafer stacking 210 and soak this wafer-to-wafer stacking 210 is in a underfill 222.Afterwards, take out this wafer-to-wafer stacking 210.At last, heat this wafer-to-wafer stacking 210 to solidify underfill.Those steps will be identical with first embodiment, and the main element identical with first embodiment will be with identical symbology, and can understand same function and purposes are arranged, and no longer be given unnecessary details at this.
In the present embodiment, those wafers 212 can be overlay crystal chip, and are provided with a reconfiguration line layer 312A at the back side of each wafer 212.Those reconfiguration line layer 312A be formed at the back side of wafer 212 and extend to via the wafer side under the active surface of wafer 212, use connecting those splicing ears 213,214, pile up and be electrically connected to each other and make those wafers 212 can be solid.Particularly, this reconfiguration line layer 312A can utilize electroless-plating, sputter or physical/chemical vapour deposition mode to form.
As shown in Figure 8, when soaking this wafer-to-wafer stacking 210, this underfill 222 is to flow into equably among those first primers gap S1 and this second primer gap S2.As shown in Figure 7, this underfill 220 is after solidifying and form the interstitital texture 300 that a multi-layer crystal chip piles up the gap.This upper surface 211A of these underfill 220 energy those wafers 212 of complete coating and this substrate 211, so cover the risk section that this reconfiguration line layer 312A may expose, make it avoid exposing and contact to air and then produce oxidation or cause problem of short-circuit to take place because of foreign object connects.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (15)
1. a multi-layer crystal chip piles up the fill method in gap, it is characterized in that it may further comprise the steps:
One wafer-to-wafer stacking is provided, and it comprises a substrate and a plurality of solid and is stacked on wafer on this substrate, is formed with at least one first primer gap between the folded wafer of two two-phases, and with this substrate one difference in height is arranged;
Those wafers that overturn this wafer-to-wafer stacking and soak this wafer-to-wafer stacking are in a underfill, and wherein this underfill is to store in a storage glue groove and keep flow regime, to fill up this first primer gap;
Take out this wafer-to-wafer stacking; And
Heat this wafer-to-wafer stacking, to be solidificated in the underfill in this first primer gap.
2. multi-layer crystal chip according to claim 1 piles up the fill method in gap, it is characterized in that wherein in the step of this wafer-to-wafer stacking is provided, this wafer-to-wafer stacking more comprises a plurality of splicing ears that are positioned at this first primer gap, to electrically connect those wafers.
3. multi-layer crystal chip according to claim 2 piles up the fill method in gap, it is characterized in that wherein each wafer is to be provided with a plurality of silicon perforation that vertically electrically conduct.
4. multi-layer crystal chip according to claim 2 piles up the fill method in gap, it is characterized in that wherein those wafers are overlay crystal chip, and is provided with a reconfiguration line layer at the back side of each wafer.
5. multi-layer crystal chip according to claim 1 piles up the fill method in gap, it is characterized in that wherein this underfill is those wafers of complete coating after taking out this wafer-to-wafer stacking.
6. pile up the fill method in gap according to the described multi-layer crystal chip of arbitrary claim in the claim 1 to 5, it is characterized in that wherein in above-mentioned immersion process, a lower surface of this substrate is not covered by this underfill.
7. multi-layer crystal chip according to claim 6 piles up the fill method in gap, it is characterized in that wherein said storage glue groove is a cylindrical shape, so that this underfill flows into the whirlpool shape.
8. pile up the fill method in gap according to the described multi-layer crystal chip of arbitrary claim in the claim 1 to 5, it is characterized in that wherein between near the wafer of this substrate and this substrate, being formed with one second primer gap, in above-mentioned immersion process, this underfill more fills up this second primer gap.
9. pile up the fill method in gap according to the described multi-layer crystal chip of arbitrary claim in the claim 1 to 5, it is characterized in that wherein in above-mentioned upset and soaking step, this wafer-to-wafer stacking is to be in vacuum state in advance.
10. a multi-layer crystal chip piles up the interstitital texture in gap, it is characterized in that it comprises:
One wafer-to-wafer stacking, it comprises a substrate and a plurality of solid and is stacked on wafer on this substrate, is formed with at least one first primer gap between the folded wafer of two two-phases, and with this substrate one difference in height is arranged; And
One soaks the underfill that forms, and fills up this first primer gap.
11. multi-layer crystal chip according to claim 10 piles up the interstitital texture in gap, it is characterized in that more comprising a plurality of splicing ears that are positioned at this first primer gap, to electrically connect those wafers.
12. multi-layer crystal chip according to claim 11 piles up the interstitital texture in gap, it is characterized in that wherein each wafer is to be provided with a plurality of silicon perforation that vertically electrically conduct.
13. multi-layer crystal chip according to claim 11 piles up the interstitital texture in gap, it is characterized in that wherein those wafers are overlay crystal chip, and is provided with a reconfiguration line layer at the back side of each wafer.
14. multi-layer crystal chip according to claim 10 piles up the interstitital texture in gap, it is characterized in that wherein said underfill is those wafers of complete coating.
15. pile up the interstitital texture in gap according to the described multi-layer crystal chip of arbitrary claim in the claim 10 to 14, it is characterized in that wherein being formed with one second primer gap between near the wafer of this substrate and this substrate, this underfill more fills up this second primer gap.
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| CN 201010111420 CN102148166A (en) | 2010-02-04 | 2010-02-04 | Method and structure for filling clearances among stacked multi-layer wafers |
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| CN 201010111420 CN102148166A (en) | 2010-02-04 | 2010-02-04 | Method and structure for filling clearances among stacked multi-layer wafers |
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Application publication date: 20110810 |