CN102141967B - Bus time sequence parameter configuration method and device - Google Patents
Bus time sequence parameter configuration method and device Download PDFInfo
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- CN102141967B CN102141967B CN 201010528473 CN201010528473A CN102141967B CN 102141967 B CN102141967 B CN 102141967B CN 201010528473 CN201010528473 CN 201010528473 CN 201010528473 A CN201010528473 A CN 201010528473A CN 102141967 B CN102141967 B CN 102141967B
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Abstract
The embodiment of the invention provides a bus time sequence parameter configuration method and a bus time sequence parameter configuration device for shortening a software development cycle and reducing the maintenance cost of equipment. The method comprises the following steps of: configuring a selected bus time sequence parameter to a controller of a central processing unit (CPU); and judging whether an access result of the CPU for initiating access to a peripheral device according to a bus time sequence corresponding to the configured bus time sequence parameter is abnormal, if so, selecting an unconfigured bus time sequence parameter and configuring the bus time sequence parameter to the controller. Compared with a method for manually debugging and configuring the bus time sequence parameter by finding a manual handbook in the prior art, the method for dynamically selecting the bus time sequence parameter has the advantages of accurately determining the bus time sequence parameter in a short time, shortening the software development cycle and improving the equipment maintainability.
Description
Technical field
The present invention relates to the communications field, relate in particular to bus time sequence parameter configuration method and device.
Background technology
Bus (Bus) is exactly one group of wire that shares in physical aspect, and many devices articulate signal transmission on it, realizes interconnection and message exchange.So-called bus timing, refer to central processing unit (CPU, Central Processing Unit) bus (is for example operated, read/write, release bus and interrupt response etc.) time, in time matching relationship between each signal on the bus, this matching relationship is relevant with the operating function of CPU.
Local bus (the Local Bus that docks with flash memory (Flash) chip with CPU, be also referred to as peripheral bus) be example, the read-write operation that CPU initiates Flash, must meet certain sequential, namely, necessarily require sheet choosing (CE), output enable (OE) and write signals such as enabling (WE) to keep the regular hour, and cooperatively interact and to work.For example, when CPU initiates read operation, after address, CE and OE signal send, peripheral components need to be within the time that limits return data, and the foundation/retention time of data also must be satisfied the requirement of CPU.
The CPU mini system of an electronic equipment may comprise various types of hardware memory device, CPLD (CPLD, Complex Programmable Logic Device), Application Specific Integrated Circuit (Application-specific integrated circuit, ASIC) and field programmable gate array (FPGA, Field Programmable Gate Array) etc., when the new veneer of exploitation, CPU needs different local bus time sequence parameters to the accessing operation of these devices.When the One's name is legion of veneer, when the device model is different, usually, the software developer need to by searching device handbook and CPU handbook, carry out the configuration of local bus time sequence parameter according to the wiring situation of hardware to CPU.After the measurement result that obtains the hardware feedback, further adjust the configuration of these parameters, finally draw suitable parameter, and be cured in the initialize routine.
Because hardware wiring, the actual local bus time sequence parameter that should dispose may there is some difference with the reference value that provides in the handbook, therefore needs manually repeatedly debugging.Yet the workload of manual debugging and these local bus time sequence parameters of configuration is huge, thereby has strengthened the cost of veneer exploitation.
Summary of the invention
The embodiment of the invention provides bus time sequence parameter configuration method and device, to shorten the construction cycle of a software, reduces the maintenance cost of equipment.
The embodiment of the invention provides a kind of bus time sequence parameter configuration method, comprising:
Select the bus timing parameter configuration to the controller of central processing unit;
Judge whether described central processing unit is unusual to the access result of peripheral components initiation access according to bus timing corresponding to the bus timing parameter of described configuration;
If described access results abnormity, the bus timing parameter configuration of then selecting not to be configured is to described controller;
If described central processing unit is according to multiple bus timing corresponding to different bus timing parameters, the access result who peripheral components is initiated access is all normal, access accuracy when then adding up described central processing unit and according to multiple bus timing corresponding to described different bus timing parameter peripheral components being initiated repeatedly to access respectively selects the high bus timing parameter configuration of access accuracy to described controller.
The embodiment of the invention provides a kind of bus timing parameter configuration device, comprising: first selects module, judge module, second to select module, statistical module and the 3rd to select module;
Described first selects module, is used for selecting the bus timing parameter configuration to the controller of central processing unit;
Described judge module is used for judging whether described central processing unit is unusual to the access result of peripheral components initiation access according to bus timing corresponding to the bus timing parameter of described configuration;
Described second selects module, when being used for described judge module and judging described access results abnormity, from the bus timing parameter configuration selecting not to be configured to described controller;
Described statistical module, if it is all normal to be used for the access result that described central processing unit initiates access according to multiple bus timing corresponding to different bus timing parameters to peripheral components, the access accuracy when then adding up described central processing unit and according to described different multiple bus timing corresponding to bus timing parameter peripheral components being initiated repeatedly to access;
The described the 3rd selects module, is used for selecting the high bus timing parameter configuration of described access accuracy to described controller.
From the invention described above embodiment as can be known, the bus timing parameter is to dispose controller to CPU by the mode of software program by searching loop, and according to the bus timing of configuration peripheral components is initiated the final foundation whether the access result of access correctly selects as the bus timing parameter with CPU, whole process does not need artificial participate in debugging and configuration.Therefore, come manual debugging to compare with the method for configuration bus time sequence parameter with prior art by searching handbook, the embodiment of the invention provides a kind of method of Dynamic Selection bus timing parameter, can accurately determine at short notice the bus timing parameter, shorten the construction cycle of a software, increase the maintainability of equipment.
Description of drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the below will do to introduce simply to the accompanying drawing of required use in prior art or the embodiment description, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain such as these accompanying drawings other accompanying drawing.
Fig. 1 is the bus time sequence parameter configuration method schematic flow sheet that the embodiment of the invention provides;
Fig. 2 is the central processing unit logical organization synoptic diagram that the embodiment of the invention provides;
Fig. 3 is the central processing unit logical organization synoptic diagram that another embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Seeing also accompanying drawing 1, is the bus time sequence parameter configuration method schematic flow sheet that the embodiment of the invention provides.Mainly comprise step:
S101 selects the bus timing parameter configuration to the controller of central processing unit.
Usually can be carried out by the network equipment to be configured the step of the embodiment of the invention, concrete, can be realized carrying out by the central processing unit of the network equipment to be configured.
The bus timing parameter is chip selection signal Time Created, output enable signal retention time, reads the enable signal retention time and write the isoparametric all or part of combination of enable signal retention time, and these chip selection signals, output enable signal and read-write enable signal etc. just consist of bus timing according to the output that cooperatively interacts of certain order in time.Can from possible bus timing parameter, select a kind of controller that disposes to central processing unit.So-called controller, refer to be formed by programmable counter, order register, command decoder, clock generator and operation control etc., its major function is to take out an instruction from internal memory, point out that next bar instruction position in internal memory deciphers or test instruction, produce corresponding operating control signal, in order to start the action of regulation, the direction that data flow between commander and control CPU, internal memory and the input-output apparatus.
Alternatively, can be determined by the related software developer the sub-bus timing parameter of several keys, select Tce and output enable retention time Toe etc. Time Created such as address Tadr Time Created, sheet.Then, adopt the method for searching loop, from all combinations that consisted of by each sub-bus timing parameter, select a kind of combination as the controller of bus timing parameter configuration to central processing unit.
For example, suppose address Tadr Time Created, sheet select Time Created Tce and the possible scope of output enable retention time Toe be 1 to 100 clock period, to the clock period be abbreviated as Tc in the following explanatory note, then possible bus timing parameter comprises 1(Tc), 1(Tc), 1(Tc), 1(Tc), 1(Tc), 2(Tc) ..., 100(Tc), 100(Tc), 100(Tc) etc.Wherein, 1(Tc), 1(Tc), 2(Tc) expression address Tadr Time Created, sheet select Time Created Tce and output enable retention time Toe be respectively 1 clock period, 1 clock period and 2 clock period, the rest may be inferred by analogy for it.When adopting searching loop, at first select bus timing parameter 1(Tc), 1(Tc), 1(Tc); Select for the second time bus timing parameter 1(Tc), 1(Tc), 2(Tc); , select at last bus timing parameter 100(Tc), 100(Tc), 100(Tc).
Alternative dispensing means is directly to select a controller that disposes to central processing unit from possible bus timing parameter.Above-mentioned possible bus timing parameter can be kept at the storer of the network equipment, can be kept at for instance volatibility (volatile) memory device, for example, in the dynamic RAM (DRAM, Dynamic Random Access Memory), also can be kept at non-volatile (non-volatile) memory device, for example, in the ROM (read-only memory) (ROM, Read-Only Memory), also can be kept in high-speed cache (Cache) or the hard disk in addition.For example, three possible bus timing parameters are arranged, be stored among the ROM of the network equipment, Tadr, Tce and the Toe of these three possible bus timing parameters are respectively 1(Tc), 1(Tc), 1(Tc), 1(Tc), 4(Tc), 4(Tc) and 3(Tc), 9(Tc), 9(Tc), then can select a controller that disposes to central processing unit from this this three possible bus timing parameters.
S102 judges whether described central processing unit is unusual to the access result of peripheral components initiation access according to bus timing corresponding to the bus timing parameter of configuration.
In the CPU mini system, with CPU in close relations and often with it mutual device can be called the peripheral components of CPU, for example, the IC of internal memory, Flash storer and some specific uses etc.Whether CPU is unusual to the bus timing of peripheral components, and being reflected to software view is exactly that whether data access is normal, whether device function is stable.Based on this principle, Basic Input or Output System (BIOS) (BIOS, Basic Input/Output System) when initialization, peripheral components is attempted conducting interviews, for example, read whether the data that the CFI interface verification of Flash returns normal, the version that reads CPLD/FPGA/ID register and verification etc.If correctly obtain these data, the bus timing that then shows the CPU peripheral components is correct, and CPU can organize bus timing according to this peripheral components is conducted interviews.
The identify label (ID) of considering the CPU peripheral components generally speaking is fixed value, in embodiments of the present invention, it specifically can be that bus timing according to configuration reads the identify label of peripheral components that CPU initiates access according to the bus timing of configuration to peripheral components, and judges that access result that CPU initiates access according to the bus timing of configuration to peripheral components judges whether mistake of identify label that CPU reads peripheral components according to bus timing corresponding to bus timing parameter that disposes.Certainly, if the CPU peripheral components does not have identify label (ID) can read the register that other have fixed value for reading yet, the present invention is not limited this.
S103 if the judged result of step S102 is the access results abnormity, then selects the bus timing parameter configuration be not configured to the controller of central processing unit.
For example, according to the embodiment of abovementioned steps S102, if select 1(Tc for the first time), 1(Tc), 1(Tc) this combination dispose to controller as one group of bus timing, CPU can not correctly read the ID of peripheral components according to this group bus timing, then the bus timing parameter selected of explanation is incorrect.So can select 1(Tc for the second time), 1(Tc), 2(Tc) this combination dispose to controller as one group of bus timing, CPU can organize the ID that bus timing removes to read peripheral components according to this, if still can not correctly read, then select again the bus timing parameter configuration of another kind of array configuration to controller.
Need to prove that the bus timing that adopts bus time sequence parameter configuration method provided by the invention to dispose out can be cured in the initialize routine, also can not be cured in the initialize routine.Be not cured in the initialize routine be because, when change of external conditions, for example when temperature, humidity and/or change in voltage, originally available bus timing may some can not be used again, at this moment, can adopt bus time sequence parameter configuration method provided by the invention to obtain correct bus timing.
From the invention described above embodiment as can be known, the bus timing parameter is to dispose controller to CPU by the mode of software program by searching loop, and the access result who peripheral components is initiated access according to the bus timing of configuration with the CPU correct foundation of selecting as final bus timing parameter whether, whole process does not need manually to participate in debugging and dispose.Therefore, come manual debugging to compare with the method for configuration bus time sequence parameter with prior art by searching handbook, the embodiment of the invention provides a kind of method of Dynamic Selection bus timing parameter, can accurately determine at short notice the bus timing parameter, shorten the construction cycle of a software, increase the maintainability of equipment.
According to the method that above-described embodiment provides, may obtain the combination of multiple available bus timing, that is, the access result that CPU initiates access according to the multiple bus timing of configuration to peripheral components is all correct, and this situation is that the characteristic by the CPU peripheral components determines.Yet when change of external conditions, for example when temperature, humidity and/or change in voltage, originally available bus timing may some can not be used again.
In embodiments of the present invention, can just stop to select new possible bus timing parameter after obtaining a bus timing parameter that can make CPU correctly access peripheral components, this moment, this bus timing parameter disposed the controller to CPU.Also can continue in the middle of the bus timing parameter that was not configured, to select new bus timing parameter to repeat above-mentioned flow process, until attempted all possible bus timing parameter, can make CPU correctly access the bus timing parameter configuration of peripheral components to the controller of CPU.When adopting the scheme of attempting all possible bus timing parameter, when the access result who peripheral components is initiated access according to multiple bus timing corresponding to different bus timing parameters as CPU is all correct, bus timing parameter configuration device can allow CPU do further pressure test, namely, CPU initiates large batch of read and write access test according to multiple bus timing corresponding to different bus timing parameters to peripheral components, and which kind of bus timing is still available when reexamining read and write access test in enormous quantities.Particularly, the access accuracy in the time of can adding up CPU and according to multiple bus timing configuration corresponding to different bus timing parameters peripheral components is initiated repeatedly to access respectively selects the high bus timing parameter configuration of access accuracy to the controller of CPU.
For example, suppose according to address Tadr Time Created, sheet select Time Created Tce and output enable retention time Toe be 1(Tc), 1(Tc), bus timing 1(Tc), CPU can correctly access its peripheral components; According to address Tadr Time Created, sheet select Time Created Tce and output enable retention time Toe be 1(Tc), 1(Tc), bus timing 3(Tc), CPU also can correctly access its peripheral components, so, adds up respectively CPU according to 1(Tc), 1(Tc), bus timing 1(Tc) and 1(Tc), 1(Tc), the access accuracy when bus timing 3(Tc) initiates repeatedly to access to peripheral components, if the former accesses the accuracy height, then select bus timing parameter 1(Tc), 1(Tc), 1(Tc) dispose to controller, if the latter accesses the accuracy height, select bus timing parameter 1(Tc), 1(Tc), 3(Tc) dispose to controller.
Seeing also Fig. 2, is a kind of bus timing parameter configuration device logical organization synoptic diagram that the embodiment of the invention provides.For convenience of explanation, only show the part relevant with the embodiment of the invention.Usually can be carried out by the network equipment to be configured the function of this bus timing parameter configuration device, particularly, can realize this bus timing parameter configuration device by the central processing unit of the network equipment to be configured.Central processing unit shown in Figure 2 comprises that first selects module 201, judge module 202 and second to select module 203, wherein:
First selects module 201, is used for selecting the bus timing parameter configuration to the controller of central processing unit;
Second selects module 203, is used for judge module 202 and judges that when accessing results abnormity, the bus timing parameter configuration of selecting not to be configured is to controller.
In the present embodiment, CPU initiates access according to bus timing corresponding to the bus timing parameter of configuration to peripheral components and is specifically as follows the identify label (ID) that CPU reads the CPU peripheral components according to the bus timing that disposes, judge module 202 is concrete to be used for judging whether mistake of identify label (ID) that described CPU reads described peripheral components according to the bus timing of described configuration, wherein, the bus timing parameter can be selected Tce and output enable retention time Toe Time Created for address Tadr Time Created, sheet.
Bus timing parameter configuration device shown in Figure 2 may further include statistical module 301 and the 3rd and selects module 302, the central processing unit that provides of another embodiment of the present invention as shown in Figure 3, wherein:
The 3rd selects module 302, is used for selecting the high bus timing parameter configuration of described access accuracy to described controller.
Need to prove, the contents such as the information interaction between each module/unit of said apparatus, implementation, since with the inventive method embodiment based on same design, its technique effect that brings is identical with the inventive method embodiment, particular content can referring to the narration among the inventive method embodiment, repeat no more herein.
One of ordinary skill in the art will appreciate that all or part of step in the whole bag of tricks of above-described embodiment is to come the relevant hardware of instruction finish by program, this program can be stored in the computer-readable recording medium, storage medium can comprise: ROM (read-only memory) (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), disk or CD etc.
More than bus time sequence parameter configuration method and a kind of central processing unit that the embodiment of the invention is provided be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. a bus time sequence parameter configuration method is characterized in that, described method comprises:
Select the bus timing parameter configuration to the controller of central processing unit;
Judge whether described central processing unit is unusual to the access result of peripheral components initiation access according to bus timing corresponding to the bus timing parameter of described configuration;
If described access results abnormity, the bus timing parameter configuration of then selecting not to be configured is to described controller;
If described central processing unit is according to multiple bus timing corresponding to different bus timing parameters, the access result who peripheral components is initiated access is all normal, access accuracy when then adding up described central processing unit and according to multiple bus timing corresponding to described different bus timing parameter peripheral components being initiated repeatedly to access respectively selects the high bus timing parameter configuration of access accuracy to described controller.
2. the method for claim 1, it is characterized in that, whether the described access result who judges that described central processing unit is initiated access according to bus timing corresponding to the bus timing parameter of described configuration to peripheral components is specially unusually, judges whether mistake of identify label that described central processing unit reads described peripheral components according to bus timing corresponding to the bus timing parameter of described configuration.
3. a bus timing parameter configuration device is characterized in that, described device comprises that first selects module, judge module, second to select module, statistical module and the 3rd to select module;
Described first selects module, is used for selecting the bus timing parameter configuration to the controller of central processing unit;
Described judge module is used for judging whether described central processing unit is unusual to the access result of peripheral components initiation access according to bus timing corresponding to the bus timing parameter of described configuration;
Described second selects module, and when judging described access results abnormity for described judge module, the bus timing parameter configuration of selecting not to be configured is to described controller;
Described statistical module, if it is all normal to be used for the access result that described central processing unit initiates access according to multiple bus timing corresponding to different bus timing parameters to peripheral components, the access accuracy when then adding up described central processing unit and according to described different multiple bus timing corresponding to bus timing parameter peripheral components being initiated repeatedly to access;
The described the 3rd selects module, is used for selecting the high bus timing parameter configuration of described access accuracy to described controller.
4. device as claimed in claim 3, it is characterized in that, whether the described access result who judges that described central processing unit is initiated access according to bus timing corresponding to the bus timing parameter of described configuration to peripheral components is specially unusually, judges whether mistake of identify label that described central processing unit reads described peripheral components according to bus timing corresponding to the bus timing parameter of described configuration.
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| CN102508149A (en) * | 2011-11-04 | 2012-06-20 | 中兴通讯股份有限公司 | Method and device for determining time sequence parameter of device |
| CN104881378A (en) * | 2015-05-15 | 2015-09-02 | 深圳市双翼科技有限公司 | Data bus and address bus processing method between Local Bus and peripheral equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5542055A (en) * | 1993-05-28 | 1996-07-30 | International Business Machines Corp. | System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices |
| CN1758232A (en) * | 2004-10-10 | 2006-04-12 | 中兴通讯股份有限公司 | Interface modular converter and method for configuration of FPGA |
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| TWI241522B (en) * | 2001-12-14 | 2005-10-11 | Mitac Technology Corp | Computer equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5542055A (en) * | 1993-05-28 | 1996-07-30 | International Business Machines Corp. | System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices |
| CN1758232A (en) * | 2004-10-10 | 2006-04-12 | 中兴通讯股份有限公司 | Interface modular converter and method for configuration of FPGA |
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