CN102130063B - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN102130063B CN102130063B CN201010034166.7A CN201010034166A CN102130063B CN 102130063 B CN102130063 B CN 102130063B CN 201010034166 A CN201010034166 A CN 201010034166A CN 102130063 B CN102130063 B CN 102130063B
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Abstract
The invention discloses a semiconductor device and a production method thereof. The method comprises the following steps of: providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a first surface and a second surface which are opposite to each other; forming a groove on the second surface and producing a capacitor through the groove; providing a second semiconductor substrate to allow the second semiconductor substrate to be joined with the first semiconductor substrate from one side of the second surface of the first semiconductor substrate; and forming other parts of the semiconductor device on the first surface. According to the method disclosed by the invention, the groove is easily formed in the semiconductor substrate, and thus a high-capacity capacitor is produced.
Description
Technical field
The application's relate generally to semiconductor fabrication process, more specifically, relates to particularly dynamic random access memory (DRAM) unit and preparation method thereof of a kind of semiconductor device.
Background technology
Dynamic random access memory (DRAM) is a kind ofly can protect stored semiconductor storage unit.Conventionally, typical DRAM unit comprises at least one transistor and holding capacitor.Due to advantages such as its high density, low costs, DRAM is widely used.
But people are for the demand of DARM storage density growing, this Design and manufacture to DRAM has proposed new challenge.On the one hand, in order to increase density, wish to reduce device size; On the other hand, the signal to noise ratio during in order to ensure the storage correctness of information and reading information, wishes that the electric capacity of holding capacitor is large as far as possible.In order to manufacture large electric capacity under the prerequisite of small-feature-size, for example, can use the material of high-k as the dielectric of capacitor, can also increase in addition the area of capacitor plate.
The example of a kind of capacitor arrangement of applying in DRAM unit is groove-shaped capacitor.By extending and to realize larger polar plate area to chip depth direction on limited chip area, groove-shaped capacitor can be take the less chip area electric capacity larger as cost obtains.Yet, along with day by day reducing of device size, on relatively little chip area, form deep trench and become more and more difficult.This has limited the performance of capacitor in DRAM unit.
Therefore, be desirable to provide a kind of particularly method of DRAM unit of semiconductor device of making, make it possible to easily form groove so that make capacitor.
Summary of the invention
In view of the above problems, the semiconductor device that the object of the present invention is to provide a kind of manufacturing method of semiconductor device and make by the method wherein easily forms groove in Semiconductor substrate, thereby makes the capacitor of large electric capacity.
According to an aspect of the present invention, provide a kind of method of making semiconductor device, having comprised: the first Semiconductor substrate is provided, and this first Semiconductor substrate has comprised each other relative first surface and second surface; On second surface, form groove, and make capacitor by this groove; The second Semiconductor substrate is provided, its second surface one side from the first Semiconductor substrate is engaged with the first Semiconductor substrate; And the miscellaneous part that forms this semiconductor device on first surface.
Preferably, first form insulating barrier in the second Semiconductor substrate, then this second Semiconductor substrate engages with the first Semiconductor substrate by this insulating barrier.
Preferably, after making capacitor and before the first Semiconductor substrate is engaged with the second Semiconductor substrate, the method also comprises: deposit insulating protective layer on the second surface of the first Semiconductor substrate.
Preferably, after making capacitor and before the first Semiconductor substrate is engaged with the second Semiconductor substrate, the method also comprises: form other groove on the second surface of the first Semiconductor substrate; And on the second surface of the first Semiconductor substrate depositing insulating layer, to fill formed other groove.Further preferably, first form insulating barrier in the second Semiconductor substrate, then this second Semiconductor substrate engages with the first Semiconductor substrate by this insulating barrier.And further preferably, form the miscellaneous part of this semiconductor device on first surface before, since the first surface of the first Semiconductor substrate, reduce the thickness of the first Semiconductor substrate, until expose the insulating barrier depositing in described other groove.
According to a further aspect in the invention, provide a kind of semiconductor device of making according to preceding method.
In semiconductor device according to the invention manufacture method and semiconductor device, owing to forming on the different surface (above-mentioned second surface) of face (above-mentioned first surface) and forming groove from parts, therefore the less restriction that is subject to chip surface area, can easily form groove, and can select the dielectric of capacitor, thereby can form the capacitor of large electric capacity.
Accompanying drawing explanation
By the description to the embodiment of the present invention referring to accompanying drawing, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1～6 show according to the middle junction composition in the manufacture method flow process of the embodiment of the present invention;
Fig. 7 shows the schematic diagram of the semiconductor device obtaining according to the manufacture method of the embodiment of the present invention;
Fig. 8 shows according to the schematic diagram of the formation capacitor connecting portion of the embodiment of the present invention;
Fig. 9 shows according to the schematic diagram of the optional groove of the embodiment of the present invention;
Figure 10～11 show the middle junction composition in manufacture method flow process according to another embodiment of the present invention; And
Figure 12 shows the schematic diagram of semiconductor device according to another embodiment of the present invention.
Embodiment
Below, by the specific embodiment shown in accompanying drawing, the present invention is described.But should be appreciated that, these descriptions are exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, omitted the description to known configurations and technology, to avoid unnecessarily obscuring concept of the present invention.
Shown in the drawings according to various structure charts and the sectional view of the semiconductor device of the embodiment of the present invention.These figure not draw in proportion, wherein for purposes of clarity, have amplified some details, and may omit some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, may be due to manufacturing tolerance or technical limitations in reality and deviation to some extent, and those skilled in the art according to reality required can design in addition there is difformity, the regions/layers of size, relative position.
According to embodiments of the invention, provide a kind of manufacturing method of semiconductor device of novelty.The method comprises: the first Semiconductor substrate is provided, and this first Semiconductor substrate comprises each other relative first surface and second surface; On second surface, form groove, and make capacitor by this groove; The second Semiconductor substrate is provided, its second surface one side from the first Semiconductor substrate is engaged with the first Semiconductor substrate; And the miscellaneous part that forms this semiconductor device on first surface.Described semiconductor device is dynamic random access memory (DRAM) unit particularly.Owing to forming miscellaneous part on first surface, therefore on second surface, (for example form, etching) during groove, impact groove being formed without the layout of too much considering miscellaneous part in wafer surface, thereby can more easily form darker groove, and can control neatly the shape of groove and to the dielectric of filling in groove.
Fig. 1～6 show according to the middle junction composition in the manufacture method flow process of the embodiment of the present invention.
As shown in Figure 1, provide semi-conductive substrate 1001, as Si substrate.This Semiconductor substrate 1001 comprises each other relative first surface (upper surface in figure) and second surface (lower surface in figure), and wherein first surface is that parts form face, and second surface is groove formation face.Particularly, as shown in Figure 1, on second surface, for example by etching, form groove 1002.Although only show single groove 1002 in figure, should be appreciated that, can form two and even more groove, this depends on device design.
After having formed groove 1002, for example, can utilize this groove 1002 to make capacitor.Those of ordinary skills can expect that several different methods makes groove-shaped capacitor, take a single example to describe in detail enforcement of the present invention here.But it is pointed out that the capacitor fabrication step the following describes is not limitation of the present invention.
First, as shown in Figure 2, on the second surface of Semiconductor substrate 1001, deposit a metal level 1003, and this metal level is carried out to composition (for example, by photoetching), make its inwall of staying groove 1002 comprise bottom.This metal level 1003 for example serves as the first pole plate of the capacitor that will form.
Then, as shown in Figure 3, dielectric layer deposition 1004 and another metal level 1005 successively on the second surface of Semiconductor substrate 1001.Then, as shown in Figure 4, dielectric layer 1004 and metal level 1005 are carried out to composition, their parts in groove place are retained, and other parts are removed.The dielectric layer 1004 staying and metal level 1005 for example serve as respectively dielectric and second pole plate of formed capacitor.
Like this, by metal level 1003, dielectric layer 1004 and metal level 1005, formed a trench capacitor.The metal material, the dielectric substance that in routine techniques, can be used to form capacitor can be used for respectively forming metal level 1003,1005 and dielectric layer 1004.
It is pointed out that and it may occur to persons skilled in the art that several different methods forms this capacitor.And the form of capacitor is also not limited to shown in figure.For example, the pole plate shape of capacitor can be different from the shape shown in figure, or can also form the pole plate of multilayer to further increase electric capacity (for example, referring to accompanying drawing 12).
Preferably, after having formed capacitor, can on second surface, further deposit as shown in Figure 5 for example SiO of an insulating protective layer 1006
2, in order to protect formed capacitor arrangement.
Then, as shown in Figure 6, provide second half conductive substrate 1007.This Semiconductor substrate 1007 can be for example Si substrate.This Semiconductor substrate 1007 is engaged as shown by the arrows in Figure 6 with the Semiconductor substrate 1001 that is formed with capacitor.Now, see on the whole, be equivalent to form a darker groove-shaped capacitor in semi-conductive substrate (first Semiconductor substrate 1001+ the second Semiconductor substrate 1007).
Preferably, in this Semiconductor substrate 1007, also form for example SiO of an insulating barrier 1008
2.In this case, insulating barrier 1008 is contacted with second surface one side of Semiconductor substrate 1001, thereby after combination, form the structure of silicon-on-insulator (SOI), further to improve device performance.
Fig. 7 shows the schematic diagram of the semiconductor device obtaining according to the manufacture method of the embodiment of the present invention.As shown in Figure 7, after as mentioned above two Semiconductor substrate being engaged, just can on the first surface of the first Semiconductor substrate 1001, form the miscellaneous part of this semiconductor device.For example, in the situation that making DRAM unit, can on the first surface of the first Semiconductor substrate 1001, make transistor 1009 (only having schematically shown this transistor in figure).The source electrode of transistor 1009 or drain electrode can be connected by wire with a pole plate of electric capacity.Transistor 1009 can be realized by modern lithography alignment technology with the arrangement of electric capacity.
Alternatively, make parts on first surface before, can, as required since first surface skiving first Semiconductor substrate of the first Semiconductor substrate, for example, by chemico-mechanical polishing (CMP), make the first Semiconductor substrate 1001 there is suitable thickness.
After having obtained as mentioned above the semiconductor device shown in Fig. 7, can also make interconnection (not shown) between all parts (as transistor 1009, capacitor) etc.Like this, just completed the making of this semiconductor device.
As for the capacitor part forming as mentioned above and the connecting portion between miscellaneous part, can there is various ways to make.For example, Fig. 8 shows the schematic diagram that forms according to an embodiment of the invention capacitor connecting portion.As shown in Figure 8, the first connecting portion 1010 contacting with the first pole plate 1003 of capacitor and the second connecting portion 1011 contacting with the second pole plate 1005 of capacitor have been formed.Particularly, for example, the second connecting portion 1011 by above make flow process in to the structure shown in Fig. 5 in insulating protective layer 1006 carry out etching and deposits conductive material (for example, metal) forms; The first connecting portion 1010 by above make flow process in to the structure shown in Fig. 7 in the first surface of the first Semiconductor substrate 1001 carry out etching and deposits conductive material (for example, polysilicon) forms.Certainly, the invention is not restricted to this, those of ordinary skill in the art it is contemplated that the capacitor connecting portion of various ways and the various ways that forms them.
According to embodiments of the invention, the second surface relative with first surface (parts formation face) from the first Semiconductor substrate forms groove, thereby greatly facilitates the making of groove.Fig. 9 shows according to the schematic diagram of the optional groove of the embodiment of the present invention.As shown in Figure 9, because do not form miscellaneous part on second surface, be equivalent to chip area on second surface and be almost " freedom ", thus can form the groove 1002 of various shapes ', to increase the electric capacity of capacitor.Particularly, what the opening of groove on second surface can be formed is larger, can be formed on groove larger on depth direction like this, has overcome the shortcoming that is not easy etching deep trench in routine techniques.
Therefore in addition, owing to not forming miscellaneous part on second surface, can easily select the dielectric that will use in capacitor, and needn't consider these dielectrics and be used for forming the compatibility between the technique of miscellaneous part.
Preferably, according to embodiments of the invention, can also form shallow trench isolation from (STI) structure.Figure 10 shows according to the middle junction composition in the manufacture method flow process of the embodiment of the present invention.As shown in figure 10, after forming capacitor arrangement as shown in Figure 4, at the position that need to form STI, form groove 1012.This groove 1012 is also to form on second surface, thereby can obtain equally the effect similar to above-mentioned effect.
Figure 11 shows according to the middle junction composition in the manufacture method flow process of the embodiment of the present invention.As shown in figure 11, depositing insulating layer 1013 SiO for example on the second surface of the first Semiconductor substrate 1001
2, to fill formed groove, to form STI.Afterwards, can process according to the flow process shown in Fig. 6～7, until obtain final semiconductor device.Wherein, make miscellaneous part on the first surface of the first Semiconductor substrate 1001 before, can start skiving the first Semiconductor substrate 1001 (for example, CMP) from this first surface, until expose formed insulating barrier 1013 in groove 1012, to form final sti structure.The degree of depth of groove 1012 is guaranteed can not destroy formed capacitor arrangement in CMP process.
In this embodiment, first formed STI (referring to Figure 11), and then formed SOI (referring to Fig. 8).Like this, in whole technological process to STI in the corrosiveness of insulating barrier less, thereby can between Semiconductor substrate 1001 and insulating barrier, not form groove.
It is to be noted, feature of the present invention is mainly in Semiconductor substrate to form and on another surface that face is relative, form groove and form accordingly capacitor part (and/or STI) with device, and and do not lie in the concrete form of capacitor and/or specifically form method.Those of ordinary skill in the art it is contemplated that the capacitor of various ways and the various ways that forms them.For example, referring to Figure 12, wherein show the schematic diagram of optional semiconductor device according to another embodiment of the present invention.In this structure, capacitor forms and comprises multilayer pole plate.Particularly, the first pole plate of this capacitor comprises a plurality of lateral part 1003b that coupled together by the longitudinal component 1003a that is formed on groove one side, and the second pole plate comprises a plurality of lateral part 1005b that coupled together by the longitudinal component 1005a that is formed on groove opposite side; Between the lateral part of the first pole plate 1003b and the lateral part 1005b of the second pole plate, filled dielectric 1004a, and by insulant 1004b, be spaced from each other between the lateral part 1003a/ longitudinal component 1003b of the first pole plate and the longitudinal component 1005b/ lateral part 1005a of the second pole plate.In addition, the first pole plate and the second pole plate are respectively by connecting portion 1010 ' with 1011 ' be connected with miscellaneous part.This capacitor arrangement can form by each pole plate layer of layer by layer deposition in groove, insulating barrier.By this structure, can greatly increase the capacitance of capacitor.
Although it is pointed out that take in the above description DRAM unit is that example comes that the present invention will be described, the present invention can need to form the semiconductor device of trench capacitor for other equally.
In above description, for ins and outs such as the composition of each layer, etchings, be not described in detail.Can be by various means of the prior art but it will be appreciated by those skilled in the art that, form layer, region of required form etc.In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above.
With reference to embodiments of the invention, the present invention has been given to explanation above.But these embodiment are only used to the object of explanation, and are not intended to limit the scope of the invention.Scope of the present invention is limited by claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (6)
1. a method of making semiconductor device, comprising:
The first Semiconductor substrate is provided, and this first Semiconductor substrate comprises each other relative first surface and second surface;
On second surface, form groove, and in this groove, make groove-shaped capacitor, this groove-shaped capacitor comprises the first pole plate, insulating barrier and the second pole plate, and wherein insulating barrier is sandwiched between the first pole plate and the second pole plate, and the first pole plate, insulating barrier and the second pole plate are contained in groove;
On the second surface of the first Semiconductor substrate, form other groove;
Depositing insulating layer on the second surface of the first Semiconductor substrate, to fill formed other groove;
The second Semiconductor substrate is provided, its second surface one side from the first Semiconductor substrate is engaged with the first Semiconductor substrate; And
On first surface, form the miscellaneous part of this semiconductor device.
2. the method for claim 1, wherein in the second Semiconductor substrate, first form insulating barrier, then this second Semiconductor substrate engages with the first Semiconductor substrate by this insulating barrier.
3. the method for claim 1, wherein after making capacitor and before the first Semiconductor substrate is engaged with the second Semiconductor substrate, the method also comprises:
On the second surface of the first Semiconductor substrate, deposit insulating protective layer.
4. the method for claim 1, wherein, form the miscellaneous part of this semiconductor device on first surface before, since the first surface of the first Semiconductor substrate, reduce the thickness of the first Semiconductor substrate, until expose the insulating barrier depositing in described other groove.
5. a semiconductor device, makes according to the method described in any one in claim 1～4.
6. semiconductor device as claimed in claim 5, wherein, described semiconductor device is dynamic random access storage unit.
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| CN201010034166.7A CN102130063B (en) | 2010-01-13 | 2010-01-13 | Semiconductor device and production method thereof |
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| CN201010034166.7A CN102130063B (en) | 2010-01-13 | 2010-01-13 | Semiconductor device and production method thereof |
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| CN102130063A CN102130063A (en) | 2011-07-20 |
| CN102130063B true CN102130063B (en) | 2014-03-12 |
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| KR20170066321A (en) | 2014-09-26 | 2017-06-14 | 인텔 코포레이션 | Integrated circuit die having backside passive components and methods associated therewith |
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| US5077232A (en) * | 1989-11-20 | 1991-12-31 | Samsung Electronics Co., Ltd. | Method of making stacked capacitor DRAM cells |
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| CN1245349A (en) * | 1998-08-14 | 2000-02-23 | 三星电子株式会社 | Method for manufacturing high-density semiconductor storage device |
| CN1341960A (en) * | 2000-08-28 | 2002-03-27 | 因芬尼昂技术股份公司 | Method for manufacturing conductive connecting wire |
| CN1819199A (en) * | 2005-01-21 | 2006-08-16 | 因芬尼昂技术股份公司 | Semiconductor product with semiconductor substrate and testing structure and method |
| CN2906929Y (en) * | 2006-04-24 | 2007-05-30 | 联华电子股份有限公司 | Groove capacitor structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7060619B2 (en) * | 2003-03-04 | 2006-06-13 | Infineon Technologies Ag | Reduction of the shear stress in copper via's in organic interlayer dielectric material |
| US7547598B2 (en) * | 2006-01-09 | 2009-06-16 | Hynix Semiconductor Inc. | Method for fabricating capacitor in semiconductor device |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0282716A1 (en) * | 1987-03-16 | 1988-09-21 | Texas Instruments Incorporated | Dram cell and method |
| US5077232A (en) * | 1989-11-20 | 1991-12-31 | Samsung Electronics Co., Ltd. | Method of making stacked capacitor DRAM cells |
| CN1180934A (en) * | 1996-07-31 | 1998-05-06 | Sgs-汤姆森微电子有限公司 | Semiconductor integrated capacitive acceleration sensor and relative fabrication method |
| CN1245349A (en) * | 1998-08-14 | 2000-02-23 | 三星电子株式会社 | Method for manufacturing high-density semiconductor storage device |
| CN1341960A (en) * | 2000-08-28 | 2002-03-27 | 因芬尼昂技术股份公司 | Method for manufacturing conductive connecting wire |
| CN1819199A (en) * | 2005-01-21 | 2006-08-16 | 因芬尼昂技术股份公司 | Semiconductor product with semiconductor substrate and testing structure and method |
| CN2906929Y (en) * | 2006-04-24 | 2007-05-30 | 联华电子股份有限公司 | Groove capacitor structure |
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