CN102129998B

CN102129998B - Method for forming polysilicon P type column in N type super-junction VDMOS (Vertical Double Diffused Metal Oxide Semiconductor)

Info

Publication number: CN102129998B
Application number: CN2010100273034A
Authority: CN
Inventors: 钱文生; 韩峰
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-01-18
Filing date: 2010-01-18
Publication date: 2012-08-01
Anticipated expiration: 2030-01-18
Also published as: CN102129998A

Abstract

The invention discloses a method for forming a polysilicon P type column in an N type super-junction VDMOS (Vertical Double Diffused Metal Oxide Semiconductor), comprising the following steps of: firstly, forming an N type drain region and an N type silicon epitaxial layer on an N type silicon substrate and etching a V-shaped groove or a conical hole on the N type silicon epitaxial layer; secondly, depositing three layer of polysilicon to fully fill the V-shaped groove or the conical hole, wherein a P type impurity is injected after the second layer of polysilicon is deposited, the total amount of the P type impurity in the N type silicon epitaxial layer is equal to that of an N type impurity after the P type impurity injected, and after the three layers of polysilicon is deposited, the surface of the substrate is ground to be flatted; thirdly, annealing and advancing the injected P type impurity to form the polysilicon P type column; and fourthly, forming a source region and a grid electrode of the N type super-junction VDMOS as well as metal contacts of a source electrode, a drain electrode and the grid electrode. By using the forming method, the process cost can be reduced, and the characteristics of low-conducting resistance and high voltage resistance endowed by the device can be achieved; and in addition, the method has strong process adjustability of process parameters and wide application range.

Description

The formation method of polysilicon P type post in the N type hyperconjugation VDMOS

Technical field

The present invention relates to a kind of semiconductor integrated circuit manufacturing process, particularly relate to the formation method of polysilicon P type post in a kind of N type hyperconjugation VDMOS.

Background technology

The P type and the N type semiconductor thin layer that are distributing in the super node MOSFET and alternately arranging; Its electric charge compensates each other; So when device is in cut-off state, applies low voltage thin layer is exhausted, thereby make p type island region and N type drift region when adopting higher-doped concentration, can realize high puncture voltage; Obtain low on-resistance simultaneously, broken through conventional power MOSFET theoretical limit.Fig. 1 is the structure chart of existing N type hyperconjugation VDMOS; Comprised the N type epitaxial loayer on being formed at N type substrate and leaking; Be formed at the P type post in the said N type epitaxial loayer; And be formed at the P trap of P type post top and the source region in the P trap, and the P trap is as the back of the body grid of device, and the N type epitaxial loayer between P trap and drain terminal is as the drift region of device; One polysilicon gate is formed on said back of the body grid and the drift region and through a gate oxide and does separator.Source region and P type post form ohmic contact and draw source electrode and back grid through Metal Contact through a P type heavily doped region; Grid is directly drawn through a Metal Contact with drain electrode.

Wherein the implementation method of P type post mainly contains two types, and a kind of is that limit growth N type epitaxial loayer limit is injected the P columnar region, and another kind is that N type outer layer growth finishes the back to P columnar region etching deep trouth and growing P-type epitaxial loayer.But the epitaxial growth cost of this dual mode is higher, and process time is longer, and the controllability of the technological parameter relevant with withstand voltage properties and conducting resistance is poor.

Summary of the invention

Technical problem to be solved by this invention provides the formation method of polysilicon P type post in a kind of N type hyperconjugation VDMOS, can reduce the technology cost, and can realize the high voltage endurance of low on-resistance of device, and the controllability of technological parameter is strong, and is applied widely.

For solving the problems of the technologies described above, the formation method of polysilicon P type post comprises the steps: in the N type hyperconjugation VDMOS provided by the invention

Step 1, on a N type silicon substrate, form N type drain region and N type silicon epitaxy layer, the foreign body concentration of said N type epitaxial loayer is 1E14～1E15cm ^-3On said N type epitaxial loayer, etch V-type groove or bellmouth; On said N type epitaxial loayer, adopt anisotropic etching to form V-type groove or bellmouth; The opening subtended angle is 15 °～30 °, and A/F is 2～5 μ m, and separation is 10 μ m; Groove depth is than shallow 0～10 μ m of epitaxy layer thickness, and A/F, the degree of depth and the spacing of said V-type groove or bellmouth are adjusted according to different demands.

Step 2, three layers of polysilicon of deposit fill up said V-type groove or bellmouth; After the deposit of wherein said second layer polysilicon; Carry out the injection of p type impurity, the impurity that said p type impurity injects is that boron, injection energy are 1000keV～2000keV, and dosage is 1E12～1E13cm ^-2, the p type impurity total amount of injecting the said N type epitaxial loayer in back equates with N type total impurities, after said three layers of polysilicon deposit are accomplished, said substrate surface is ground leveling.

Step 3, to the propelling of annealing of the p type impurity of said injection, form said polysilicon P type post; The temperature that said annealing advances is 800～1000 ℃, and the time is 30 minutes～3 hours.

The Metal Contact of source region, grid and source, leakage and the grid of step 4, the said N type hyperconjugation VDMOS of formation.

The present invention is through inserting polysilicon to the V-type groove or the bellmouth of N type epitaxial loayer, and injection and high temperature that polysilicon carries out p type impurity advanced forms polysilicon P type post, and N type extension can be accomplished in a deposit; Its foreign body concentration is adjustable, and P type post does not need the higher P type epitaxial deposition process of cost, and the condition of p type impurity can be regulated according to application demand; The technology cost is low; Modulability is good, has higher cellular density simultaneously, can be used for the manufacturing of the high withstand voltage VDMOS of low on-resistance.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is the structure chart of existing N type hyperconjugation VDMOS;

Fig. 2 is the formation method flow diagram of polysilicon P type post in the N type hyperconjugation VDMOS of the present invention;

Fig. 3-Figure 14 is the structure chart of N type hyperconjugation VDMOS in each step of the present invention.

Embodiment

As shown in Figure 2, the formation method of polysilicon P type post comprises the steps: in the N type hyperconjugation VDMOS that the embodiment of the invention provides

Step 1, as shown in Figure 3 is 1E19～1E20cm at bulk concentration ^-3N type silicon substrate on growth one deck lightly doped N type silicon epitaxy layer, the foreign body concentration of said N type silicon epitaxy layer is 1E14～1E15cm ^-3, epitaxy layer thickness is determined that by range of application wherein said N type substrate is used as the drain region of device.As shown in Figure 4, the growing silicon oxide mask layer, lithographic definition goes out V-type groove zone, and etching formation is the V-type groove zone of hard mask with said silica.As shown in Figure 5; With said silica is the said N type of hard mask etching silicon epitaxy layer, forms the V-type groove, and its groove depth, opening size and separation can be regulated according to practical application; The opening subtended angle is 15 °～30 °; A/F is 2～5 μ m, and separation is 10 μ m, and groove depth is than shallow 0～10 μ m of epitaxy layer thickness.As shown in Figure 6, remove said silicon oxide masking film layer; As shown in Figure 7, growth one deck sacrificial oxide layer; As shown in Figure 8, remove said sacrificial oxide layer, repair the defective of deep trouth side epitaxial loayer.

Step 2, as shown in Figure 9, the ground floor undoped polycrystalline silicon of deposit; Shown in figure 10, deposit second layer polysilicon, and carry out the high-energy p type impurity and inject, the impurity that said p type impurity injects is that boron, injection energy are 1000keV～2000keV, dosage is 1E12～1E13cm ^-2, to look and use and design and decide, the p type impurity total amount of injecting the said N type epitaxial loayer in back equates with N type total impurities.Shown in figure 11, the 3rd layer of undoped polycrystalline silicon of deposit, promptly this layer polysilicon do not need to mix.Shown in figure 12, polysilicon fills up to grind behind the said V-type groove and makes surfacingization.

Step 3, shown in figure 13, annealing advances, and the p type impurity in the polysilicon is evenly distributed, and forms said polysilicon P type post; The temperature that said annealing advances is 800～1000 ℃, and the time is 30 minutes～3 hours, looks and uses and design and decide.

Step 4, shown in figure 14 forms the P trap in said polysilicon P type post, in the P trap, form the source region, in said P trap, forms P type heavily doped region, and this P type heavily doped region is in order to form the ohmic contact of said P trap and source region electrode.Form the Metal Contact of grid and source, leakage and grid at last, accomplish the making of the super VDMOS of said N type.

More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.

Claims

1. the formation method of polysilicon P type post in the N type hyperconjugation VDMOS is characterized in that, comprises the steps:

Step 1, on a N type silicon substrate, form N type drain region and N type silicon epitaxy layer, on said N type silicon epitaxy layer, etch V-type groove or bellmouth;

Step 2, three layers of polysilicon of deposit fill up said V-type groove or bellmouth; Wherein after the deposit of second layer polysilicon; Carry out the injection of p type impurity; The p type impurity total amount of injecting the said N type silicon epitaxy layer in back equates with N type total impurities, after said three layers of polysilicon deposit are accomplished, said substrate surface is ground leveling;

Step 3, to the propelling of annealing of the p type impurity of said injection, form said polysilicon P type post;

2. the formation method of polysilicon P type post in the N type hyperconjugation VDMOS as claimed in claim 1 is characterized in that: the foreign body concentration of the type of N described in step 1 silicon epitaxy layer is 1E14～1E15cm ^-3

3. the formation method of polysilicon P type post in the N type hyperconjugation VDMOS as claimed in claim 1; It is characterized in that: groove of V-type described in the step 1 or bellmouth adopt anisotropic etching to form; The opening subtended angle is 15 °～30 °; A/F is 2～5 μ m, and separation is 10 μ m, and groove depth is than shallow 0～10 μ m of epitaxy layer thickness.

4. the formation method of polysilicon P type post in the N type hyperconjugation VDMOS as claimed in claim 1 is characterized in that: the impurity that p type impurity described in the step 2 injects is that boron, injection energy are 1000keV～2000keV, and dosage is 1E12～1E13cm ^-2

5. the formation method of polysilicon P type post in the N type hyperconjugation VDMOS as claimed in claim 1 is characterized in that: the temperature that annealing advances described in the step 3 is 800～1000 ℃, and the time is 30 minutes～3 hours.