CN102122894B - Method for detecting synchronous signal of direct current speed regulator - Google Patents

Abstract

The invention relates to a method for detecting a synchronous signal of a direct current speed regulator, which is used for accurately detecting a three-phase power-supply zero-crossing point in a three-phase full-control thyristor rectification circuit. The method can be used for calculating period and judging phase sequence of the three-phase power supply while detecting the three-phase power zero-crossing point, also used for performing reliable phase shift control. The method comprises the following steps: acquiring three-phase synchronous square wave signals by carrying out the zero balancing on the three-phase synchronous voltages; inputting the square wave signals into a processor and detecting rising edge interruption; dividing a three-phase synchronous level signal into six sections at 60-degree time intervals, wherein the level state of each section is fixed; polling the level state every 10 microseconds; if continuously detecting the same level state 50 times, judging that the section position is correct; and calculating a power supply period according to an inertia filter formula, judging the phase sequence, acquiring a natural phase exchange point, and performing the phase shift trigger.

Description

A kind of detecting synchronous signal of direct current speed regulator

Technical field

The present invention relates to a kind of detecting synchronous signal of direct current speed regulator, specifically a kind of for the three-phase fully-controlled scr rectification circuit, can overcome noise jamming, carry out the control method that zero passage detection, judging phase order, power cycle calculating and phase shift trigger.

Background technology

At present, DC speed regulator generally uses three-phase fully-controlled scr rectification circuit and phase shift to trigger control.The key that phase shift triggers is to find exactly the zero crossing of three phase mains, and with zero crossing as time reference, the trigger angle of delaying time obtains an adjustable dc voltage at output.The detection of phase control rectifier circuit requirement zero crossing must be accurate, otherwise just can not trigger thyristor in correct phase place.

Traditional zero-crossing detection circuit uses synchrotrans with the step-down of three-phase forceful electric power and isolation, uses analog circuit to carry out zero balancing, exports the three-phase square wave signal, then these signals is sent into the interrupt pin of microprocessor.The rising edge of these signals indicates the appearance of zero crossing as interrupt trigger signal.In the switching process of thyristor, three phase mains can produce very large noise jamming, shows as larger burr.Traditional zero-crossing detection circuit can produce because of these noise jamming pulse output, causes speed regulator can not correctly carry out phase control, even the generation false triggering causes short circuit accident.

Summary of the invention

The object of the present invention is to provide a kind ofly can overcome noise jamming, be used for the three-phase fully-controlled scr rectification circuit, accurately carry out the method that the three phase mains zero crossing detects.When detecting above-mentioned three phase mains zero crossing, carry out computation of Period and the judging phase order of three phase mains, and carry out reliable phase shifting control.

For achieving the above object, the technical scheme taked of the present invention is:

Three phase mains R, S, T can produce 6 interruptions through the zero passage comparison circuit in one-period: R phase rising edge, trailing edge; S phase rising edge, trailing edge; T phase rising edge, trailing edge.In the inner moment of adopting counter to record respectively their interrupt of little processing be:

t _rup，t _rdown，t _sup，t _sdown，t _tup，t _tdown，

Simultaneously in software take 10us as the cycle, the continuous level state of poll RST three-phase synchronous signal, continuous to detect level state 50 times identical, thinks that then burr does not occur disturbs the misoperation that causes.

When having occured, R phase rising edge interrupts, and the level state the when level state of the three-phase synchronous signal that this detects interrupts with last R phase rising edge is consistent, think that then the new cycle begins, detect new zero crossing, one order inertia filter below using this moment calculates power cycle, and calculates phase difference.

$\left.\begin{array}{c}{T}_{\mathrm{temp}}+=T_{i-1}*K_1+(32768-K_1)*(t_{\mathrm{rup}\left(i\right)}-t_{\mathrm{rup}(i-1)});\\ T_i=T_{\mathrm{temp}}>>15;\\ T_{\mathrm{temp}}-=T_i<<15;\end{array}\right\}......\left(1\right)$

T _rs＝t _sup-t _rup；T _rt＝t _tup-t _rup；

When Trs＞Trt is judged as the RST phase sequence, otherwise be RTS.

Be time reference according to the R phase zero crossing that finds, backward every 60 degree, obtain other 5 natural commutation point of one-period, the Trigger Angle according to given triggers thyristor.

The beneficial effect that the present invention is compared with the prior art is: the present invention utilizes the saltus step of three-phase synchronous signal level to detect zero cross signal, has guaranteed the real-time of synchronous detection; Simultaneously by detecting the level state of synchronizing signal, effectively filtering the issuable misoperation of noise burr, guaranteed the accuracy of synchronous detection, avoided disturbing the thyristor false triggering that causes; Calculate power cycle by above-mentioned filter on the other hand, filtering interference and the measure error minimum fluctuation that arrives, the accuracy of the power cycle that has calculated.

Description of drawings

The present invention is described further below in conjunction with the drawings and specific embodiments.

Fig. 1 is three-phase fully-controlled scr rectification circuit schematic diagram.

Fig. 2 is that the synchronizing signal that burr causes is disturbed schematic diagram.

Fig. 3 is three-phase synchronous testing circuit schematic diagram.

Fig. 4 is that schematic diagram is divided in three phase mains signal level and sector.

Fig. 5 is that three-phase synchronous signal interrupts schematic diagram.

Embodiment

The invention provides a kind of simple to operate, strong interference immunity, and the three phase mains sychronizing signal detecting method that can be used widely in engineering.In Fig. 1, the inventive method is a kind of sychronizing signal detecting method that is used in interchange and the direct current Thyristor DC Speed Regulation System.The method connects and level shifting circuit based on the circuit among Fig. 3, and wherein R, S, T are respectively three-phase alternating-current supply.

The present invention need to detect the level state of three-phase synchronous signal, in Fig. 3, adopts synchrotrans with the step-down of three-phase forceful electric power and isolation, uses analog circuit to carry out zero balancing, output three-phase synchronous square-wave signal.In Fig. 4, according to the time interval of 60 degree, the three-phase synchronous level signal is divided into 6 sectors, the level state of each sector is determined, as follows: S0 (101), S1 (100), S2 (110), S3 (010), S4 (011), S5 (001), wherein 1 represent high level, 0 represents low level.In Fig. 2, in the process of thyristor Push And Release, the three phase mains distorted then can produce burr at three phase mains, produces disturbing pulse at three-phase synchronous signal.In Fig. 2, it is a high-frequency signal that burr disturbs, and sees that by oscilloscope the pulse duration that is caused by burr is 10～100 microseconds in practice, the longest in 300 microseconds.In Fig. 4, in each sector of three phase mains, the level state of signal is constant, when interference has occured, is disturbing the moment that occurs so, and the level state of this sector just changes, and has become S2 (010) by S1 (001).But the duration of S2 lacks very much, and in the scope of sector 1, most times of the state of level are S1, in software, and the state of a level of each 10us poll, continuous to detect level state 50 times identical, thinks that then this sector location is correct.In Fig. 5, each cycle, 6 level saltus step schematic diagrames that three-phase synchronous signal produces:

t _rup，t _rdown，t _sup，t _sdown，t _tup，t _tdown，

Respectively R phase rising edge, R phase trailing edge, S phase rising edge, S phase trailing edge, T phase rising edge, T phase trailing edge.Edge with these level saltus steps interrupts as interrupt signal triggering microprocessor, and the moment of record interruption generation, as the time reference of computing cycle and phase shift triggering.

Based on above-mentioned principle, the detection of synchronizing signal comprises computation of Period, judging phase order, is to carry out according to following steps:

Rising edge occurs and interrupts in the first step: R mutually, records current level state, and the state when current level state with last R the rising edge interruption occurs mutually is identical, then turns second step, otherwise turns for the 3rd step;

Second step: calculate the three phase mains cycle according to formula (1).Wherein Ti represents the current power cycle that calculates.Formula 1 is an one order inertia filter, and K1 is filter factor, selects K1=1000.Then carried out synchronously fault and judged, judged whether power cycle is 20ms (50HZ), and going beyond the scope then reports an error, otherwise, calculate the power cycle difference of twice calculating, when continuous 10 cycles, the computation of Period error then arranges synchronous complement mark in 3us;

$\left.\begin{array}{c}{T}_{\mathrm{temp}}+=T_{i-1}*K_1+(32768-K_1)*(t_{\mathrm{rup}\left(i\right)}-t_{\mathrm{rup}(i-1)});\\ T_i=T_{\mathrm{temp}}>>15;\\ T_{\mathrm{temp}}-=T_i<<15;\end{array}\right\}......\left(1\right)$

T wherein _TempThe intermediate variable that calculates the digital filter algorithm of electrical network cycle use, T _Temp+=and T _TempThe literary style of-=be C language, expression adds deduct K with the result of calculation of previous step is tired ₁Be filter factor, value 1000 in the use, t _{Rup (i)}The R phase rising edge moment that obtains in the current sampling period, t _{Rup (i-1)}The R phase rising edge moment that obtained in a upper sampling period, (t _{Rup (i)}-t _{Rup (i-1)}) be that two rising edges subtract each other constantly, be the instant electrical network cycle that current sampling obtains, T _I-1The filtered electrical network cycle that previous step calculates, T _iIt is the current filtered electrical network cycle that calculates.

The 3rd step: the continuous level state of poll synchronizing signal, when the level state that obtains for continuous 50 times is identical, then upgrade current sector level state;

Rising edge occurs and interrupts in the 4th step: S mutually, then calculates the RS phase difference according to formula (2);

T _rs＝t _sup-t _rup......(2)

Rising edge occurs and interrupts in the 5th step: T mutually, then calculates the RT phase difference according to formula (3);

T _rt＝t _tup-t _rup......(3)

The 6th step: the RS that calculates according to formula (2) (3) and the phase difference of RT carry out judging phase order, work as T _Rs＞T _RtCan be judged as the RST phase sequence, otherwise be RTS, wherein T _RsPhase difference between the expression RS phase, T _RtPhase difference between the expression RT phase;

The 7th step: when finishing synchronously, then calculate the Trigger Angle α that current step needs carry out thyristor control according to the DC speed regulator control algolithm.According to the cycle that calculates, and interrupt constantly can obtaining the moment t of all the other 5 natural commutation point as time reference with R phase rising edge _i=t ₀+ (T _Period/ 6) * i (i=1,2,3,4,5), T _PeriodThe expression power cycle.According to circuit shown in the figure one, thyristor is triggered.

Claims (3)

1. a detecting synchronous signal of direct current speed regulator is characterized in that, comprises following content:

1) with the zero balancing of three-phase synchronous voltage process, obtains the three-phase synchronous square-wave signal, these square-wave signals are input to processor, and detect the rising edge interruption;

2) according to the interval of 60 degree, the three-phase synchronous level signal is divided into 6 sectors, the level state of each sector is determined;

3) state of a level of each 10us poll, identical when detecting level state continuous 50 times, think that then this sector location is correct;

4) calculate power cycle according to the one order inertia Filtering Formula, and judge phase sequence, obtain natural commutation point, carry out phase shift and trigger.

2. detecting synchronous signal of direct current speed regulator according to claim 1, it is characterized in that, the three-phase synchronous level signal is divided into 6 sectors, the level state of each sector is determined, shown below: S0 (101), S1 (100), S2 (110), S3 (010), S4 (011), S5 (001), wherein 1 represent high level, 0 represents low level.

3. detecting synchronous signal of direct current speed regulator according to claim 1 is characterized in that, uses following one order inertia filter:

$\left.\begin{array}{c}{T}_{\mathrm{temp}}+=T_{i-1}*K_1+(32768-K_1)*(t_{\mathrm{rup}\left(i\right)}-t_{\mathrm{rup}(i-1)});\\ T_i=T_{\mathrm{temp}}>>15;\\ T_{\mathrm{temp}}-=T_i<<15;\end{array}\right\}......\left(1\right)$

T wherein _TempThe intermediate variable that calculates the digital filter algorithm of electrical network cycle use, T _Temp+=and T _TempThe literary style of-=be C language, expression adds deduct K with the result of calculation of previous step is tired ₁Be filter factor, value 1000 in the use, t _{Rup (i)}The R phase rising edge moment that obtains in the current sampling period, t _{Rup (i-1)}The R phase rising edge moment that obtained in a upper sampling period, (t _{Rup (i)}-t _{Rup (i-1)}) be that two rising edges subtract each other constantly, be the instant electrical network cycle that current sampling obtains, T _I-1The filtered electrical network cycle that previous step calculates, T _iIt is the current filtered electrical network cycle that calculates.

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