CN102110713B - Transistor - Google Patents
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- CN102110713B CN102110713B CN 200910265488 CN200910265488A CN102110713B CN 102110713 B CN102110713 B CN 102110713B CN 200910265488 CN200910265488 CN 200910265488 CN 200910265488 A CN200910265488 A CN 200910265488A CN 102110713 B CN102110713 B CN 102110713B
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Abstract
The invention discloses a transistor, which comprises a substrate, a gate, a semiconductor layer, an insulating stack layer, a source electrode and a drain electrode. The drain electrode is arranged on the substrate. The semiconductor layer is arranged on the substrate, and the first type carrier is used as the main carrier. The insulating stack layer is arranged between the semiconductor layer and the gate and comprises a first insulating layer and a second insulating layer, wherein the first insulting layer comprises a first group capable of attracting the first type carrier, the second insulating layer comprises a second group capable of attracting the second type carrier, and the first insulating layer is arranged between the semiconductor layer and the second insulating layer. The source electrode and the drain electrode are arranged on the substrate, and are positioned on the two sides of the semiconductor layer.
Description
Technical field
The invention relates to a kind of semiconductor element, and particularly relevant for a kind of transistor.
Background technology
Transistor can be played the part of the role who drives display medium in display, and in the process that drives display medium, the stability of transistorized electrical characteristics will influence the image comparison that display medium presents.Therefore, have better display quality in order to make display, transistor array need be kept stable threshold voltage (threshold voltage) and operating current.
In general, under the situation of dark and anhydrous oxygen, transistor can have stable threshold voltage and operating current.Yet, transistor has high sensitive to light, that is to say, when transistor is penetrated in illumination, transistorized electrical characteristics can be affected at once, and threshold voltage shift takes place, subthreshold slope (sub-threshold swing) becomes electrically drift phenomenon such as big and operating current change, and above-mentioned electrical property change can't be replied in millisecond.Thus, can have a strong impact on display frame and the display quality of display.
Therefore, this area is needed a kind of high electrically transistor of stability that has badly, to keep good electrical characteristics in operating process.
Summary of the invention
The invention provides a kind of transistor, it has high electrically stability and low lightsensitivity.
The present invention proposes a kind of transistor, comprises substrate, grid, semiconductor layer, insulation stack of layers and source electrode and drain electrode.Gate configuration is on substrate.Semiconductor layer is disposed on the substrate, with the first kenel charge carrier as main charge carrier.The insulation stack of layers is disposed between semiconductor layer and the grid, comprises first insulating barrier and second insulating barrier.Wherein, first insulating barrier comprises first group that can attract the first kenel charge carrier, and second insulating barrier comprises second group that can attract the second kenel charge carrier, and first insulating barrier is disposed between semiconductor layer and second insulating barrier.Source electrode and drain configuration and are positioned at the both sides of semiconductor layer on substrate.
In one embodiment of the invention, above-mentioned insulation stack of layers further comprises the 3rd insulating barrier, and the 3rd insulating barrier comprises the 3rd group that can attract the first kenel charge carrier, and the 3rd insulating barrier is disposed between second insulating barrier and the grid.
Based on foregoing, transistor of the present invention has the insulation stack of layers, it is stacked mutually by the insulating barrier that different charge carriers is had binding force and forms, and to promote transistorized electrical stability and to reduce transistorized lightsensitivity, makes transistor have good electrical characteristics.
For feature of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is a kind of transistorized generalized section according to the first embodiment of the present invention.
Fig. 2 is a kind of transistorized generalized section according to a second embodiment of the present invention.
Fig. 3 is a kind of transistorized generalized section of a third embodiment in accordance with the invention.
Fig. 4 is a kind of transistorized generalized section of a fourth embodiment in accordance with the invention.
Fig. 5 is a kind of transistorized generalized section according to a fifth embodiment of the invention.
The main element symbol description
100,100a, 200,200a, 300: transistor
110,210,310: substrate
120,220,320: semiconductor layer
130S, 230S, 330S: source electrode
130D, 230D, 330D: drain electrode
140,140a, 240,240a, 340: insulation stack of layers
142,144,146,242,244,246,342,344,346: insulating barrier
150,250,350: grid
Embodiment
[first embodiment]
Fig. 1 is a kind of transistorized generalized section according to the first embodiment of the present invention.
Please refer to Fig. 1, transistor 100 comprises substrate 110, semiconductor layer 120, source electrode 130S and drain electrode 130D, insulation stack of layers 140 and grid 150.Semiconductor layer 120 is disposed on the substrate 110, with the first kenel charge carrier as main charge carrier.Source electrode 130S and drain electrode 130D are disposed on the substrate 110, and are positioned at the both sides of semiconductor layer 120.In detail, in the present embodiment, the first kenel charge carrier is the hole, that is to say that semiconductor layer 120 for example is the p type semiconductor layer that has than multi-hole.The material of semiconductor layer 120 can be inorganic semiconductor or organic semiconductor, wherein inorganic semiconductor comprises amorphous silicon, polysilicon or oxide semiconductor series, and organic semiconductor comprises organic molecule, organic polymer or organic molecule and organic macromolecule mixture.Moreover substrate 110 can be rigid substrate or bendable musical form substrate, and wherein the material of rigid substrate for example is glass, quartz or Silicon Wafer, and the material of bendable musical form substrate for example is for example acryl, metal forming (metal foil) or paper of plastic cement.Source electrode 130S for example is the alloy of gold, silver, aluminium, copper, chromium, titanium or previous materials with the material of drain electrode 130D, and its formation method for example is the physical vapour deposition (PVD) manufacture method.
In the present embodiment, first insulating barrier 142 and second insulating barrier 144 can be inorganic insulating material or organic insulating material, and it for example is that dielectric constant is lower than 4 advanced low-k materials.Moreover the formation method of first insulating barrier 142 and second insulating barrier 144 for example is rubbing method, and the gross thickness of insulation stack of layers 140 for example is 220nm～800nm, and wherein preferred situation is 230nm～300nm.Wherein, the material of first insulating barrier 142 for example is vinylpyrrolidone (poly (vinyl pyrrolidone), PVP), polyethylene phenol (poly (vinyl phenol), PVP), polyphenylene sulfide (polyphenylene sulfide, PPS), phenol resin (phenol resin) or other comprise the insulating material of the group with electronics releasability.The material of second insulating barrier 144 for example is that polytetrafluoro (polyethylene tetrafluoride) comprises the insulating material of the group with electronics capacitation with polyarylate (polyarylate) or other.In addition, second insulating barrier 144 with attraction electronic capability for example is to comprise such as metallics such as gold, silver or platinum, and the content of metallic in second insulating barrier 144 is less than 0.1wt% (being that the percentage by weight of metallic in second insulating barrier is less than 0.1%).For instance, the material of second insulating barrier 144 can be golden nanometer particle be entrained in the organic memory material of formed bistable state in the polymer (polymerstabilized gold-nanoparticles, Au-PCm).
Special one carry be, insulation stack of layers 140 may further include the 3rd insulating barrier (not illustrating), the 3rd insulating barrier is disposed between grid 150 and second insulating barrier 144, and the 3rd insulating barrier can be the insulating material that comprises the group that can attract the hole, the insulating material that comprises the group that can attract electronics or general insulating material.Moreover the formation method of grid 150 for example is to form one deck gate material layers earlier, and the little shadow of recycling and etching manufacture method are with the gate material layers patterning.The material of gate material layers comprises metal, doped polycrystalline silicon or transparent conductive oxide etc., and its formation method for example is physical vapour deposition (PVD) manufacture method or chemical vapour deposition (CVD) manufacture method.
In the present embodiment, on the semiconductor layer 120 that has than multi-hole, stack second insulating barrier 144 that has first insulating barrier 142 that attracts the hole ability and have the attraction electronic capability in regular turn.Thus, different charge carriers had first insulating barrier 142 of binding force and second insulating barrier 144 after stacking coupling, can offset the number of effective defective, and the electronics that produces trace fetters defective, this micro-electronics constraint defective can fetter the electronic carrier in the semiconductor layer 120, and these electronic carriers can suppress the accumulation in hole at semiconductor layer/insulating barrier interface place.Therefore, when transistorized semiconductor layer is penetrated in illumination, because the electron recombination (recombination) that produces when most holoe carrier can be with illumination in the semiconductor layer, so can keep the electrical stability of transistor 100 and the lightsensitivity that reduces transistor 100, make transistor 100 have good electrical characteristics.
Therefore, when transistor application in display (comprising soft electronic display unit such as Electronic Paper, flexible display) during as driving transistors, when even light source shines the transistor surface by display medium, transistor still can be kept electrical characteristics such as stable threshold voltage and operating current, makes display have better display quality.Special one carry be, stop that with metal cover light enters transistorized method than existing, transistor of the present invention need not use extra material layer, just can reduce because of illumination and penetrate the electrical drift amount that causes, so transistorized manufacturing of the present invention is compatible with existing manufacture method and can not increase transistorized cost of manufacture.Moreover, because the defective number of organic insulator is than next many of inorganic insulation layer, make existing organic transistor that electrical problem of unstable be arranged easily, therefore insulation stack of layers of the present invention can be applicable in the organic transistor, to promote the electrical stability of organic transistor.
[second embodiment]
Fig. 2 is a kind of transistorized generalized section according to a second embodiment of the present invention.The structural similarity of the structure of the transistor 100a of present embodiment and the transistor 100 of Fig. 1, its main difference are in transistor 100a and further comprise the 3rd insulating barrier 146, below only describe at its main difference place.
Please refer to Fig. 2, transistor 100a comprises substrate 110, semiconductor layer 120, source electrode 130S and drain electrode 130D, insulation stack of layers 140a and grid 150.Insulation stack of layers 140a comprises first insulating barrier 142, second insulating barrier 144 and the 3rd insulating barrier 146 that stacks in regular turn on semiconductor layer 120.In the present embodiment, semiconductor layer 120 is to be main charge carrier with the hole, and it for example is p type semiconductor layer.First insulating barrier 142 for example is to comprise first group that can attract the hole, and second insulating barrier 144 for example is to comprise second group that can attract electronics, and the 3rd insulating barrier 146 for example is to comprise the 3rd group that can attract the hole.Wherein, the 3rd group comprises that alkyl, alcohol radical, amino and other have the group of electronics releasability.
In the present embodiment, first insulating barrier 142, second insulating barrier 144 and the 3rd insulating barrier 146 can be inorganic insulating material or organic insulating material, and it for example is that dielectric constant is lower than 4 advanced low-k materials.Moreover the formation method of first insulating barrier 142, second insulating barrier 144 and the 3rd insulating barrier 146 for example is rubbing method, and the gross thickness of insulation stack of layers 140a for example is 220nm～800nm, and wherein preferred situation is 230nm～300nm.Wherein, the material of first insulating barrier 142 and second insulating barrier 144 can be with reference to described in first embodiment, and the material of the 3rd insulating barrier 146 for example is vinylpyrrolidone (poly (vinyl pyrrolidone), PVP), polyethylene phenol (poly (vinyl phenol), PVP), polyphenylene sulfide (polyphenylenesulfide, PPS), phenol resin (phenol resin) or other comprise the insulating material of the group with electronics releasability.Special one carry be, insulation stack of layers 140a can more comprise the 4th insulating barrier (not illustrating), the 4th insulating barrier is disposed between grid 150 and the 3rd insulating barrier 146, and the 4th insulating barrier can be the insulating material that comprises the group that can attract the hole, the insulating material that comprises the group that can attract electronics or general insulating material.In other words, though in the present embodiment be with by three-layer insulated layer 142,144,146 to be stacked the insulation stack of layers 140a that forms be example, but the invention is not restricted to this, the user can form multiple insulation stack of layers according to the mode of stacking of insulating barrier of the present invention.
From the above, in the present embodiment, on the semiconductor layer 120 that has than multi-hole, stack in regular turn and have first insulating barrier 142 that attracts the hole ability, have and attract the of electronic capability, insulating barrier 144 and have the 3rd insulating barrier 146 that attracts the hole ability.That is to say, main charge carrier kenel according to semiconductor layer, on semiconductor layer in regular turn and staggered stacking have the insulating barrier that attracts the hole ability and have the insulating barrier that attracts electronic capability, thus, different charge carriers had the insulating barrier of binding force after stacking coupling, can offset the number of effective defective, and the electronics that produces trace fetters defective, this micro-electronics constraint defective can fetter the electronic carrier in the semiconductor layer, and these electronic carriers can suppress the accumulation in hole at semiconductor layer/insulating barrier interface place.
Therefore, when transistorized semiconductor layer is penetrated in illumination, because the electron recombination (recombination) that produces when most holoe carrier can be with illumination in the semiconductor layer, so can keep transistorized electrical stability and reduce transistorized lightsensitivity, make transistor have good electrical characteristics.Thus, when transistor application in display (comprising soft electronic display unit such as Electronic Paper, flexible display) during as driving transistors, even light irradiation transistor is arranged, transistor still can be kept electrical characteristics such as stable threshold voltage and operating current, makes display have better display quality.
[the 3rd embodiment]
Fig. 3 is a kind of transistorized generalized section of a third embodiment in accordance with the invention.The structural similarity of the structure of the transistor 200 of present embodiment and the transistor 100 of Fig. 1, its main difference be in the semiconductor layer 220 of the transistor 200 of present embodiment be with electronics as main charge carrier, below will describe at its main difference place.
Please refer to Fig. 3, transistor 200 comprises substrate 210, semiconductor layer 220, source electrode 230S and drain electrode 230D, insulation stack of layers 240 and grid 250.Semiconductor layer 220 is disposed on the substrate 210, with electronics as main charge carrier.Grid 250 is disposed on the substrate 210.Insulation stack of layers 240 is disposed between semiconductor layer 220 and the grid 250, comprises first insulating barrier 242 and second insulating barrier 244.Wherein, first insulating barrier 242 comprises the group that can attract electronics, and second insulating barrier 244 comprises the group that can attract the hole, and first insulating barrier 242 is disposed between semiconductor layer 220 and second insulating barrier 244.Source electrode 230S and drain electrode 230D are disposed on the substrate 210, and are positioned at the both sides of semiconductor layer 220.Wherein, substrate 210, grid 250 and source electrode 230S can be persons described in the known materials and methods in affiliated field or first embodiment with material and the formation method of drain electrode 230D, so do not describe in detail in this.
In the present embodiment, semiconductor layer 220 is for having the n type semiconductor layer than polyelectron.The material of semiconductor layer 220 can be inorganic semiconductor or organic semiconductor, wherein inorganic semiconductor for example is amorphous silicon, polysilicon or oxide semiconductor series, and organic semiconductor comprises organic molecule, organic polymer or organic molecule and organic macromolecule mixture.First insulating barrier 242 comprises the group that can attract electronics, comprises that halogen (halogen group), itrile group (nitrile group), carbonyl (carbonyl group), nitro (nitro group) and other have the group of electronics capacitation.Second insulating barrier 244 comprises the group that can attract the hole, comprises that alkyl (alkyl group), alcohol radical (alcohol group), amino (amino group) and other have the group of electronics releasability.
Moreover first insulating barrier 242 and second insulating barrier 244 can be inorganic insulating material or organic insulating material, and it for example is that dielectric constant is lower than 4 advanced low-k materials.Moreover the formation method of first insulating barrier 242 and second insulating barrier 244 for example is rubbing method, and the gross thickness of insulation stack of layers 240 for example is 220nm～800nm, and wherein preferred situation is 230nm～300nm.Wherein, the material of first insulating barrier 242 for example is that polytetrafluoro (polyethylenetetrafluoride) comprises the insulating material of the group with electronics capacitation with polyarylate (polyarylate) or other.The material of second insulating barrier 244 for example is vinylpyrrolidone (poly (vinylpyrrolidone), PVP), polyethylene phenol (poly (vinyl phenol), PVP), polyphenylene sulfide (polyphenylene sulfide, PPS), phenol resin (phenol resin) or other comprise the insulating material of the group with electronics releasability.In addition, first insulating barrier 242 with attraction electronic capability for example is to comprise such as metallics such as gold, silver or platinum, and the content of metallic in insulating barrier 242 is less than 0.1wt%.For instance, the material of first insulating barrier 242 can be golden nanometer particle be entrained in the organic memory material of formed bistable state in the polymer (polymerstabilized gold-nanoparticles, Au-PCm).Moreover, insulation stack of layers 240 may further include the 3rd insulating barrier (not illustrating), it is disposed between grid 250 and second insulating barrier 244, and the 3rd insulating barrier can be the insulating material that comprises the group that can attract electronics, the insulating material that comprises the group that can attract the hole or general insulating material.
In the present embodiment, on the semiconductor layer 220 that has than polyelectron, stack second insulating barrier 244 that has first insulating barrier 242 that attracts electronic capability and have attraction hole ability in regular turn.Thus, different charge carriers had first insulating barrier 242 of binding force and second insulating barrier 244 after stacking coupling, can offset the number of effective defective, and the hole that produces trace fetters defective, this micro-hole constraint defective can fetter the holoe carrier in the semiconductor layer 220, and these holoe carriers can suppress the accumulation of electronics at semiconductor layer/insulating barrier interface place.
Therefore, when transistorized semiconductor layer is penetrated in illumination, because the hole-recombination (recombination) that produces when most electronic carrier can be with illumination in the semiconductor layer, so can keep transistorized electrical stability and reduce transistorized lightsensitivity, make transistor have good electrical characteristics.Therefore, when transistor application in display (comprising soft electronic display unit such as Electronic Paper, flexible display) during as driving transistors, even light irradiation transistor is arranged, transistor still can be kept electrical characteristics such as stable threshold voltage and operating current, makes display have better display quality.
[the 4th embodiment]
Fig. 4 is a kind of transistorized generalized section of a fourth embodiment in accordance with the invention.The structural similarity of the structure of the transistor 200a of present embodiment and the transistor 200 of Fig. 3, its main difference are in transistor 200a and further comprise the 3rd insulating barrier 246, below only describe at its main difference place.
Please refer to Fig. 4, transistor 200a comprises substrate 210, semiconductor layer 220, source electrode 230S and drain electrode 230D, insulation stack of layers 240a and grid 250.Insulation stack of layers 240a comprises first insulating barrier 242, second insulating barrier 244 and the 3rd insulating barrier 246 that stacks in regular turn on semiconductor layer 220.In the present embodiment, semiconductor layer 220 is to be main charge carrier with electronics, and it for example is n type semiconductor layer.First insulating barrier 242 for example is to comprise the group that can attract electronics, and second insulating barrier 244 for example is to comprise the group that can attract the hole, and the 3rd insulating barrier 246 for example is to comprise the group that can attract electronics.Wherein, the 3rd insulating barrier 246 contained groups comprise that halogen, itrile group, carbonyl, nitro and other have the group of electronics capacitation.
In the present embodiment, first insulating barrier 242, second insulating barrier 244 and the 3rd insulating barrier 246 can be inorganic insulating material or organic insulating material, and it for example is that dielectric constant is lower than 4 advanced low-k materials.Moreover the formation method of first insulating barrier 242, second insulating barrier 244 and the 3rd insulating barrier 246 for example is rubbing method, and the gross thickness of insulation stack of layers 240a for example is 220nm～800nm, and wherein preferred situation is 230nm～300nm.Wherein, the material of first insulating barrier 242 and second insulating barrier 244 can be with reference to described in the 3rd embodiment, comprise the insulating material of the group with electronics capacitation and the material of the 3rd insulating barrier 246 for example is polytetrafluoro (polyethylene tetrafluoride) with polyarylate (polyarylate) or other, its formation method for example is rubbing method.Special one carry be, insulation stack of layers 240a may further include the 4th insulating barrier (not illustrating), the 4th insulating barrier is disposed between grid 250 and the 3rd insulating barrier 246, and the 4th insulating barrier can be the insulating material that comprises the group that can attract the hole, the insulating material that comprises the group that can attract electronics or general insulating material.In other words, though in the present embodiment be with by three-layer insulated layer 242,244,246 to be stacked the insulation stack of layers 240a that forms be example, but the invention is not restricted to this, the user can form multiple insulation stack of layers according to the mode of stacking of insulating barrier of the present invention.
Hold above-mentionedly, in the present embodiment, on the semiconductor layer 220 that has than polyelectron, stack in regular turn and have first insulating barrier 242 that attracts electronic capability, have second insulating barrier 244 that attracts the hole ability and have the 3rd insulating barrier 246 that attracts electronic capability.That is to say, on having than the semiconductor layer of polyelectron in regular turn and staggered stacking have the insulating barrier that attracts electronic capability and have the insulating barrier that attracts the hole ability, thus, different charge carriers had the insulating barrier of binding force after stacking coupling, can offset the number of effective defective, and the hole that produces trace fetters defective, this micro-hole constraint defective can fetter the holoe carrier in the semiconductor layer, and these holoe carriers can suppress the accumulation of electronics at semiconductor layer/insulating barrier interface place.
Therefore, when transistorized semiconductor layer is penetrated in illumination, because the hole-recombination (recombination) that produces when most electronic carrier can be with illumination in the semiconductor layer, so can keep transistorized electrical stability and reduce transistorized lightsensitivity, make transistor have good electrical characteristics.Thus, when transistor application in display (comprising soft electronic display unit such as Electronic Paper, flexible display) during as driving transistors, even light irradiation transistor is arranged, transistor still can be kept electrical characteristics such as stable threshold voltage and operating current, makes display have better display quality.
[the 5th embodiment]
In the above-described embodiment, all be transistor 100,100a, 200, the 200a with last grid (top gate) structure be example, but transistor of the present invention also can be applied to have the transistor of following grid (bottom gate) structure.
Fig. 5 is a kind of transistorized generalized section according to a fifth embodiment of the invention.
As shown in Figure 5, the member of transistor 300 is similar to the member of the transistor of Fig. 2 100, but transistor 300 has following grid structure.Transistor 300 comprises substrate 310, semiconductor layer 320, source electrode 330S and drain electrode 330D, insulation stack of layers 340 and grid 350.Wherein, semiconductor layer 320 is disposed on the substrate 310 and is positioned at grid 350 tops, with the first kenel charge carrier as main charge carrier.Source electrode 330S and drain electrode 330D are positioned at the both sides of semiconductor layer 320 and are positioned at grid 350 tops.Insulation stack of layers 340 is disposed between semiconductor layer 320 and the grid 350, comprises first insulating barrier 342, second insulating barrier 344 and the 3rd insulating barrier 346.First insulating barrier, 342 adjacent semiconductor layers 320, the 3rd insulating barrier 346 adjoins gate 350, and second insulating barrier 344 is between first insulating barrier 342 and the 3rd insulating barrier 346.Wherein, first insulating barrier 342 comprises first group that can attract the first kenel charge carrier, and second insulating barrier 344 comprises second group that can attract the second kenel charge carrier, and the 3rd insulating barrier 346 comprises the 3rd group that can attract the first kenel charge carrier.
In other words, when semiconductor layer 320 with the first kenel charge carrier during as main charge carrier, the insulating barrier 342 that will comprise the group that can attract first charge carrier is configured to and semiconductor layer 320 adjacency, the more interconnected insulating barrier 344 and the insulating barrier 346 that comprises the group that can attract first charge carrier that comprises the group that can attract second charge carrier.That is to say, as shown in Figure 5, with 310 the direction from semiconductor layer 320 to substrate, form first insulating barrier 342, second insulating barrier 344 and the 3rd insulating barriers 346 at semiconductor layer 320 in regular turn.When the first kenel charge carrier in the semiconductor layer 320 is the hole, semiconductor layer 320, first insulating barrier 342, second insulating barrier 344 and the 3rd insulating barrier 346 can be corresponding with reference to semiconductor layer 120, first insulating barrier 142, second insulating barrier 144 and the 3rd insulating barrier 146 described in second embodiment, so do not give unnecessary details in this.On the other hand, when the first kenel charge carrier is electronics in the semiconductor layer 320, semiconductor layer 320, first insulating barrier 342, second insulating barrier 344 and the 3rd insulating barrier 346 can be corresponding with reference to semiconductor layer 220, insulating barrier 242, insulating barrier 244 and the insulating barrier 246 described in the 4th embodiment, so do not give unnecessary details in this.Moreover, though be that the stack of layers 340 that insulate comprises that three-layer insulated layer 342,344,346 is example in the present embodiment, but the transistor with following grid structure also can have the insulation stack of layers that stacked with dielectric layers (only comprising first insulating barrier 342 and second insulating barrier 344 such as insulation stack of layers 340), or by other number insulating barriers according to the formed insulation stack of layers of mode that stacks of the present invention.
In the present embodiment, the stack of layers that will insulate in the above described manner is disposed in the transistor 300 with following grid structure, different charge carriers had the insulating barrier of binding force after stacking coupling, can promote the electrical stability of transistor 300 and the lightsensitivity that reduces transistor 300, make transistor have good electrical characteristics.Thus, be under dark or light-struck environment, to operate no matter have the transistor of following grid structure, can both keep electrical characteristics such as stable threshold voltage and operating current.
In sum, transistor of the present invention has the insulation stack of layers, it is stacked mutually by the insulating barrier that different charge carriers is had binding force and forms, these insulating barriers are after stacking coupling, can promote transistorized electrical stability and reduce transistorized lightsensitivity, make transistor have good electrical characteristics.That is to say that transistor of the present invention is operated under light-struck environment, still can keep electrical characteristics such as stable threshold voltage and operating current.
Therefore, when transistor application was in display, even light source shines transistor when surface by display medium, transistor still can be kept stable electric characteristics, makes display have better display quality.In addition, stop that with metal cover light enters transistorized method than existing, transistor of the present invention need not use extra material layer, just can reduce because of illumination and penetrate the electrical drift amount that causes, so transistorized manufacturing of the present invention is compatible with existing manufacture method and can not increase transistorized cost of manufacture.Moreover transistorized structure of the present invention can be applicable in the organic transistor, to promote the electrical stability of organic transistor.
Though the present invention discloses as above with embodiment; so it is not in order to limit the present invention; those of ordinary skill under any in the technical field; without departing from the spirit and scope of the present invention; when making suitable change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining who applies for a patent.
Claims (21)
1. transistor comprises:
One substrate;
One grid is disposed on this substrate;
Semi-conductor layer is disposed on this substrate, with one first kenel charge carrier as main charge carrier;
One insulation stack of layers is disposed between this semiconductor layer and this grid, comprising:
One first insulating barrier comprises one first group that can attract this first kenel charge carrier;
One second insulating barrier comprises one second group that can attract one second kenel charge carrier, and wherein this first insulating barrier is disposed between this semiconductor layer and this second insulating barrier; And
One the 3rd insulating barrier, the 3rd insulating barrier comprise one the 3rd group that can attract this first kenel charge carrier, and the 3rd insulating barrier is disposed between this second insulating barrier and this grid; And
One source pole and a drain electrode are disposed on this substrate, and are positioned at the both sides of this semiconductor layer.
2. transistor according to claim 1, wherein this first kenel charge carrier is the hole, and this second kenel charge carrier is electronics.
3. transistor according to claim 2, wherein this semiconductor layer is p type semiconductor layer.
4. transistor according to claim 2, wherein this first group comprise alkyl, alcohol radical and amino one of them.
5. transistor according to claim 2, wherein this second group comprise halogen, itrile group, carbonyl and nitro one of them.
6. transistor according to claim 1, wherein the 3rd group comprise alkyl, alcohol radical and amino one of them.
7. transistor according to claim 2, wherein this second insulating barrier comprises metallic.
8. transistor according to claim 7, wherein the percentage by weight of this metallic in this second insulating barrier is less than 0.1%.
9. transistor according to claim 7, wherein this metallic comprises gold, silver or platinum.
10. transistor according to claim 1, wherein this first kenel charge carrier is electronics, and this second kenel charge carrier is the hole.
11. transistor according to claim 10, wherein this semiconductor layer is n type semiconductor layer.
12. transistor according to claim 10, wherein this first group comprise halogen, itrile group, carbonyl and nitro one of them.
13. transistor according to claim 10, wherein this second group comprise alkyl, alcohol radical and amino one of them.
14. transistor according to claim 10, wherein this first insulating barrier comprises metallic.
15. transistor according to claim 14, wherein the percentage by weight of this metallic in this first insulating barrier is less than 0.1%.
16. transistor according to claim 14, wherein this metallic comprises gold, silver or platinum.
17. transistor according to claim 1, wherein the 3rd group comprise halogen, itrile group, carbonyl and nitro one of them.
18. transistor according to claim 1, wherein the 3rd insulating barrier comprises metallic.
19. transistor according to claim 18, wherein the percentage by weight of this metallic in the 3rd insulating barrier is less than 0.1%.
20. transistor according to claim 18, wherein this metallic comprises gold, silver or platinum.
21. transistor according to claim 1, wherein the gross thickness of this insulation stack of layers is 220nm～800nm.
Priority Applications (1)
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| CN 200910265488 CN102110713B (en) | 2009-12-29 | 2009-12-29 | Transistor |
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| CN 200910265488 CN102110713B (en) | 2009-12-29 | 2009-12-29 | Transistor |
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| CN102110713B true CN102110713B (en) | 2013-08-07 |
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| KR100995451B1 (en) * | 2003-07-03 | 2010-11-18 | 삼성전자주식회사 | Organic Thin Film Transistor comprising Gate Insulator having Multi-layered Structure |
| US20060214154A1 (en) * | 2005-03-24 | 2006-09-28 | Eastman Kodak Company | Polymeric gate dielectrics for organic thin film transistors and methods of making the same |
| JPWO2007099690A1 (en) * | 2006-02-28 | 2009-07-16 | パイオニア株式会社 | Organic transistor and manufacturing method thereof |
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