CN102110613A - Method for regulating threshold voltage of semiconductor device - Google Patents
Method for regulating threshold voltage of semiconductor device Download PDFInfo
- Publication number
- CN102110613A CN102110613A CN2009102441351A CN200910244135A CN102110613A CN 102110613 A CN102110613 A CN 102110613A CN 2009102441351 A CN2009102441351 A CN 2009102441351A CN 200910244135 A CN200910244135 A CN 200910244135A CN 102110613 A CN102110613 A CN 102110613A
- Authority
- CN
- China
- Prior art keywords
- threshold voltage
- dielectric layer
- semiconductor device
- carry out
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method for regulating the threshold voltage of a semiconductor device, and the method comprises the following steps: (a) forming a source region, a drain region, a gate stack arranged on a substrate positioned between the source region and the drain region, a side wall formed on the side wall of the gate stack, and an inner layer dielectric layer covering the source region and the drain region, wherein the gate stack comprises a dummy gate dielectric layer and a dummy gate; (b) removing the dummy gate, and exposing the dummy gate dielectric layer to form an opening; (c) performing ion implantation to the substrate from the opening to form a doped region for regulating the threshold voltage of the semiconductor device, wherein the depth of the formed doped region is less than 10 nm; (d) removing the dummy gate dielectric layer; (e) performing thermal annealing to activate the dopes in the doped region; and (f) depositing a gate dielectric layer and a metal gate in the opening, wherein the gate dielectric layer covers the inner wall of the side wall.
Description
Technical field
The present invention relates generally to semiconductor device art.More specifically, relate to a kind of method of adjusting the semiconductor device threshold voltage of injecting by mixing.
Background technology
In semiconductor technology, the threshold voltage vt of metal-oxide semiconductor (MOS) pipe equals that grid pile up the bottom and source electrode forms the bias voltage of the grid of raceway groove needs to source electrode together the time.If grid less than threshold voltage, does not just have raceway groove to source bias voltage.A specific transistorized threshold voltage is relevant with several factors, comprises that grid pile up the doping of bottom, dielectric thickness, excess charges in grid material and the dielectric or the like.
The doping that grid pile up the bottom is the principal element of decision threshold voltage, mixes to inject by the ion a little under the grid stack surface and adjust in the bottom of metal-oxide-semiconductor.This ion injects and is called threshold value adjustment injection, or Vt adjusts injection.
At present traditional Vt adjusts method for implanting and for example can inject by mixing and to finish, and promptly by forming suitable doped region in the substrate below grid pile up, thereby realizes the adjustment to the semiconductor threshold voltage.But the existing mode of mixing and injecting; in substrate, form doped region and dopant can be introduced source area and drain region undeservedly usually; doped region distributes overlapping with the doping of source/drain region; cause that metal oxide semiconductor field effect answers band-band leakage current in transistor (MOSFET) device and source-drain junction electric capacity to increase, thereby cause the decline of device performance.
Therefore, in order when adjusting the semiconductor device threshold voltage, to provide high-performance semiconductor device, need a kind of method of adjustment of semiconductor device threshold voltage and device thereof source and drain areas to be introduced improper doping when trivial to avoid in substrate, forming mixing.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention proposes a kind of method of adjusting the semiconductor device threshold voltage, can when adjusting the semiconductor device threshold voltage, can provide high performance semiconductor device as required thereby provide.
According to an aspect of the present invention, the method of the adjustment semiconductor device threshold voltage of the embodiment of the invention, described method comprises: a) forming source area, drain region on the substrate, be arranged on that the grid between described source area and drain region pile up on the described substrate, piling up side wall that sidewall forms and the inner layer dielectric layer that covers described source area and drain region at described grid, described grid pile up and comprise dummy grid dielectric layer and dummy grid; B) remove described dummy grid, expose described dummy grid dielectric layer to form opening; C) from described opening substrate is carried out ion and inject, with the doped region of the threshold voltage that is formed for adjusting semiconductor device, the formation degree of depth of described doped region is less than 10 nanometers; D) remove described dummy grid dielectric layer; E) carry out thermal annealing, to activate the doping of described doped region; And f) deposition gate dielectric layer and metal gates in described opening, described gate dielectric layer covers the inwall of described side wall.
For the N type semiconductor device, use P type dopant to carry out ion and inject to improve the threshold voltage of device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.Described N type dopant comprises V group element; Described P type dopant comprises III family element.Described ion implantation dosage is 5e11-5e12.
The further embodiment according to the present invention, described doped region are not overlapping with described source area and drain region.
According to another aspect of the present invention, the method of the adjustment semiconductor device threshold voltage of the embodiment of the invention may further comprise the steps: a) forming source area, drain region on the substrate, be arranged on that the grid between described source area and drain region pile up on the described substrate, piling up side wall that sidewall forms and the inner layer dielectric layer that covers described source area and drain region at described grid, described grid pile up and comprise dummy grid; B) remove described dummy grid, expose described substrate to form opening; C) from described opening substrate is carried out ion and inject, with the doped region of the threshold voltage that is formed for adjusting semiconductor device, the formation degree of depth of described doped region is less than 10 nanometers; D) carry out thermal annealing, to activate the doping of described doped region; And e) plated metal grid in described opening, described metal gates covers the inwall of described side wall.
The further embodiment according to the present invention, described doped region are not overlapping with described source area and drain region.
The present invention utilizes the opening of removing dummy grid formation to carry out the dopant ion injection, can avoid the trivial dopant that mixes is introduced source area and drain region undeservedly, and then make doped region be formed in the substrate under the dummy grid, and make that the distribution of doped region is not overlapping with the doping of source/drain region.Like this, when the present invention adjusts the semiconductor device threshold voltage by the mode of above-mentioned doping injection, can reduce, improve the performance of device because of introducing the increase of doped region to band-band leakage current in the MOSFET device and source-drain junction electric capacity.Therefore, the present invention can provide high performance semiconductor device when adjusting the semiconductor device threshold voltage.
Description of drawings
Fig. 1 shows the flow chart according to the manufacture method of the semiconductor device of the first embodiment of the present invention;
Fig. 2-10 shows the schematic diagram according to each fabrication stage of semiconductor device of the first embodiment of the present invention;
Figure 11 shows the flow chart of the manufacture method of semiconductor device according to a second embodiment of the present invention.
Figure 12-13 shows the schematic diagram of each fabrication stage of semiconductor device according to a second embodiment of the present invention;
Embodiment
The present invention relates generally to a kind of method of adjusting the semiconductor device threshold voltage, relate in particular to a kind of ion that utilizes and inject the method for adjusting the semiconductor device threshold voltage.Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
First embodiment
Fig. 1 shows the flow chart according to the formation method of the semiconductor device of the first embodiment of the present invention.
In step 101, at first provide a Semiconductor substrate 202.With reference to figure 2, in the present embodiment, substrate 202 comprises the silicon substrate (for example wafer) that is arranged in crystal structure.According to the known designing requirement of prior art (for example p type substrate or n type substrate), substrate 202 can comprise various doping configurations.The substrate 202 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Perhaps, substrate 202 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 202 can comprise epitaxial loayer alternatively, can be by stress changes strengthening the property, and can comprise silicon-on-insulator (SOI) structure.
In step 102, be formed with source area 204, drain region 206 on the substrate 202, be arranged on the substrate 202 and the grid between source area 204 and drain region 206 pile up 30, and piling up the side wall 214 that 30 two side forms at grid.Wherein, grid pile up 30 and comprise dummy grid dielectric layer 212 and dummy grid 208.
Dummy grid dielectric layer 212 can be thermal oxide layer, comprises silica, silicon nitride, for example silicon dioxide.Dummy grid 208 is a sacrifice layer.Dummy grid 208 can for example be a polysilicon.In one embodiment, dummy grid 208 comprises amorphous silicon.Dummy grid dielectric layer 212 and dummy grid 208 can be by the MOS technical matters, and for example deposition, photoetching, etching and/or other suitable methods form.
Source/drain region 204,206 can be injected p type or n type alloy or impurity and form to substrate 202 by the transistor arrangement according to expectation.Source/drain region 204,206 can be by comprising that photoetching, ion inject, spread and/or the method for other appropriate process forms.Source electrode and drain electrode 204,206 can form in dummy grid dielectric layer 212 later on, utilize common semiconducter process and step, described device is carried out thermal annealing, to activate the doping in source electrode and the drain electrode 204,206, thermal annealing can adopt the technologies that those skilled in the art knew such as comprising rapid thermal annealing, spike annealing to carry out.
Covering gate piles up 30 and forms side wall 214.Side wall 214 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof, and/or other suitable materials form.Side wall 214 can have sandwich construction.Side wall 214 can form by the method that comprises the dielectric substance that deposition is suitable.Side wall 214 has one section to cover grid and pile up on 30, and this structure can obtain with the technology that those skilled in the art knew.In other embodiments, side wall 214 also can not cover grid and piles up on 30.
Then, as shown in Figure 2, cover source area 204, drain region 206 and side wall 214 on substrate 202, deposition forms inner layer dielectric layer (ILD) 216.Inner layer dielectric layer 216 can be but the silica (as Pyrex, boron-phosphorosilicate glass etc.) and the silicon nitride (Si3N4) that are not limited to for example unadulterated silica (SiO2), mix.Inner layer dielectric layer 216 for example can use, and chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD) and/or other suitable methods such as technology form.Inner layer dielectric layer 216 can have sandwich construction.In one embodiment, the thickness range of inner layer dielectric layer 216 is about 30 to 90 nanometers.
Then, as shown in Figure 3, interlayer dielectric layer 216 and side wall 214 are carried out planarization, and handle the upper surface that stops at side wall 214.For example can remove interlayer dielectric layer 216, until the upper surface that exposes side wall 214 by chemico-mechanical polishing (CMP) method.
As shown in Figure 4, utilize chemico-mechanical polishing or reactive ion etching (RIE) again, side wall 214 is handled,, and expose dummy grid 208 until the upper surface of removing side wall 214.
Then method proceeds to step 103, and as shown in Figure 5, dummy grid 208 is removed, and exposes dummy grid dielectric layer 212 to form opening 220.For example, etching polysilicon and stop at and remove dummy grid 208 on the dummy grid dielectric layer 212 and form opening 220 optionally.Dummy grid 208 can use wet etching and/or dry ecthing to remove.In one embodiment, wet etching process comprises Tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) or other suitable etch agent solutions.
Step proceeds to 104 then, with reference to figure 6, from opening 220 substrate 202 is carried out ion and injects, and forming doped region 222, thereby adjusts the threshold voltage of semiconductor device according to the doped region 222 that forms.Preferably, described ion is injected to vertical substantially ion injection.
The dopant ion type that forms doped region 222 as required can be that p type or n type mix, with to being applied to NMOS or PMOS.
For the N type semiconductor device, use P type dopant to carry out ion and inject to improve the threshold voltage of device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.Described N type dopant comprises V group element; Described P type dopant comprises III family element.Described V group element comprises phosphorus and arsenic; Described III family element comprises boron, boron difluoride or indium.Described ion implantation dosage is 5e11-5e12, and forming the degree of depth is less than 10 nanometers, and the formation degree of depth of described doped region is meant the degree of depth of the doping peak value after ion injects.
In step 105, as shown in Figure 7, dummy grid dielectric layer 212 is removed, for example can use wet etching and/or dry ecthing to remove.In one embodiment, wet etching process comprises hydrofluoric acid (HF) or other suitable etch agent solutions.Keep dummy grid dielectric layer 212 owing in ion implantation process, only removing pseudo electrode 208, so the performance of dummy grid dielectric layer 212 may deterioration.At this moment, need to remove dummy grid dielectric layer 212, in post-order process, form new gate dielectric layer again.As shown in Figure 7, dummy grid dielectric layer 212 is removed, and then carries out thermal annealing, to activate the doping in the doped region 222.Perhaps, earlier doped region 222 is carried out thermal annealing,, and then remove dummy grid dielectric layer 212 with the doping in the activation doped region 222.
In the present embodiment, dummy grid dielectric layer 212 injects the back removal at ion.In other embodiments, dummy grid dielectric layer 212 can be removed before ion injects, and next step execution ion injects and carries out carrying out thermal annealing again behind the doped region 222, hereinafter will provide detailed description.
Subsequently,, device is carried out thermal annealing,, for example can adopt laser annealing or flash anneal, in other embodiment, can adopt other thermal anneal process to activate the doping in the doped region 222 in step 106.In this step, also need to consider to the activation needs of source/drain region 204/206 and source/leakages expansion area doping (impurity) and extend influence.If mix and activated by thermal annealing in source/drain region 204/206 and source/leakage expansion area, the thermal annealing that adopts in this step needs spike, mixes with minimizing source/drain region and source/leakage expansion area and spreads.According to embodiments of the invention, adopt spike technology that device is carried out thermal annealing usually, for example carry out delicate level laser annealing in about temperature more than 1300 ℃.
In step 107, in opening 220, form new gate dielectric layer 224, wherein gate dielectric layer 224 covers the inwall of substrate 202 and side wall 214.As shown in Figure 8.
Deposition gate dielectric layer 224 in the surface of interlayer dielectric layer 216 and opening 220, gate dielectric layer 224 for example is high-k (high k) material.In one embodiment, high k material comprises hafnium oxide (HfO
2).The high k material of other examples comprises HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and combination thereof, and/or other suitable materials.Gate dielectric layer 224 can comprise that about 12 dusts are to the thickness between the 35 dust scopes.Gate dielectric layer 224 can form by the technology of for example chemical vapor deposition (CVD) or ald (ALD).Gate dielectric layer 224 can also have sandwich construction, comprises the more than one layer with above-mentioned material.
Preferably, after forming gate dielectric layer 224, can deposit workfunction metal grid layer thereon.Workfunction metal grid layer can be included in about 10 dusts to the thickness between about 100 dust scopes.The material that is used for workfunction metal grid layer can comprise TiN, TiAlN, TaN and TaAlN.
In other embodiments, after new gate dielectric layer 224 forms, can increase by a step thermal anneal process, to improve gate dielectric layer 224 quality, the temperature range of thermal annealing is 600 to 800 degree.
On gate dielectric layer 224, form metal gates 226 afterwards, as shown in Figure 9.Metal gate material can comprise one or more material layers, and lining for example provides material, gate material and/or other suitable materials of appropriate work function number to grid.Can from the group that comprises following column element, select one or more elements deposit for n N-type semiconductor N device: TiN, TiAlN, TaAlN, TaN, and the combination of these materials; Can from the group that comprises following column element, select one or more elements deposit for p N-type semiconductor N device: TiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and the combination of these materials.
Carry out chemico-mechanical polishing (CMP) technology at last and carry out planarization, to form metal gates 226, as shown in figure 10.At this moment, semiconductor device has the doped region 222 that is arranged in the substrate under the opening 220, and injects type and inject energy according to the dopant ion of doped region 222, can adjust the threshold voltage of semiconductor device.
Second embodiment
The aspect that below will be only be different from first embodiment with regard to second embodiment is set forth.The part of Miao Shuing not will be understood that with first embodiment and has adopted identical step, method or technology to carry out, and therefore repeats no more once more.
Shown in Figure 11, in described step 203, dummy grid dielectric layer 212 and dummy grid 208 can be removed in the lump, thereby be exposed described substrate 202, to form opening 220, as shown in figure 12.In one embodiment, can use wet etching and/or dry ecthing to remove dummy grid 208 and dummy grid dielectric layer 212.
Then the step with first embodiment is identical, more described device is carried out ion and injects, to be formed for regulating the doped region 222 of threshold voltage, as shown in figure 13.For the N type semiconductor device, use P type dopant to carry out ion and inject to improve the threshold voltage of device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.Described N type dopant comprises V group element; Described P type dopant comprises III family element.Described V group element comprises phosphorus and arsenic; Described III family element comprises boron, boron difluoride or indium.Described ion implantation dosage is 5e11-5e12, and forming the degree of depth is less than 10 nanometers.The formation degree of depth of described doped region is meant the degree of depth of the doping peak value after ion injects.
Because dummy grid dielectric layer 212 has been removed in step 203, therefore directly enter step 206, carry out the dopant ion injection technology again after, can directly carry out thermal annealing, to activate the doping impurity in the doped region 222 to device.For example can adopt laser annealing or flash anneal, in other embodiment, can adopt other thermal anneal process.In this step, also need to consider the activation needs that mixed in source/drain region and source/leakage expansion area and extend influence.Be annealed activation if mix in source/drain region and source/leakage expansion area, the thermal annealing that adopts in this step needs spike, mixes with minimizing source/drain region and source/leakage expansion area and spreads.According to embodiments of the invention, adopt spike technology that device is carried out thermal annealing usually, for example carry out delicate level laser annealing in about temperature more than 1300 ℃.
And, in step 207, in opening 220, forming new gate dielectric layer 224 and metal gates 226 subsequently, described gate dielectric layer 224 covers the inwall of described substrate 202 and side wall 214.Thereby compare with first embodiment, second embodiment has obtained to have the semiconductor device of the doped region 222 in the substrate under opening, and the dopant ion according to doped region 222 injects type and injects energy and dosage, can adjust the threshold voltage of semiconductor device.
Described according to the first and second aspects of the present invention above by in substrate, forming doped region, thereby adjusted the method for the threshold voltage of semiconductor device.
The embodiments of the invention utilization is removed opening that dummy grid forms and is carried out ion and inject, and makes doped region be formed in the substrate under the dummy grid, and makes that the distribution of doped region is not overlapping with the doping of source/drain region.And,, use P type dopant to carry out ion and inject to improve the threshold voltage of device for the N type semiconductor device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.Like this, can adjust the semiconductor device threshold voltage by the mode that doped region injects, can reduce simultaneously, improve the performance of device because of introducing the increase of doped region to band-band leakage current in the MOSFET device and source-drain junction electric capacity in the present invention.Therefore, the present invention provides high performance semiconductor device when adjusting the semiconductor device threshold voltage.
In addition, in the prior art because the heat budget of source area and drain region thermal annealing is too big, this thermal annealing forms the required temperature and time of atom diffusion to be needed greater than the annealing of the doping in the channel region.Therefore cause the foreign atom diffusion in the channel region excessive unfriendly, thereby destroyed dopant profiles.Flow process of the present invention can select to carry out earlier source/drain region thermal annealing, then form doped region in the raceway groove, carry out the mode of doped region thermal annealing again, so just avoided of the influence of source/drain region thermal annealing, can advantageously avoid destroying the distribution of precipitous doped region doped region.
Moreover, after forming, gate dielectric carries out usually owing in substrate, form the ion injection of doped region, and ion injects may make the gate dielectric deterioration, also can reduce the performance of device unfriendly.And the injection of doped region ion is carried out in the present invention's employing earlier, forms the mode of gate dielectric and metal gates again, can avoid the problem of above-mentioned gate dielectric deterioration, thereby the performance that has correspondingly guaranteed semiconductor device does not worsen.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, claims of the present invention are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (17)
1. method of adjusting the semiconductor device threshold voltage, described method comprises:
A) forming source area, drain region on the substrate, be arranged on that the grid between described source area and drain region pile up on the described substrate, piling up side wall that sidewall forms and the inner layer dielectric layer that covers described source area and drain region at described grid, described grid pile up and comprise dummy grid dielectric layer and dummy grid;
B) remove described dummy grid, expose described dummy grid dielectric layer to form opening;
C) from described opening substrate is carried out ion and inject, with the doped region of the threshold voltage that is formed for adjusting semiconductor device, the formation degree of depth of described doped region is less than 10 nanometers;
D) remove described dummy grid dielectric layer;
E) carry out thermal annealing, to activate the doping of described doped region; And
F) deposition gate dielectric layer and metal gates in described opening, described gate dielectric layer covers the inwall of described side wall.
2. method according to claim 1, wherein said steps d are carried out after step e.
3. method according to claim 1 and 2 wherein before described step c, is also carried out thermal annealing to activate the doping of described source area and described drain region.
4. method according to claim 1, wherein,
For the N type semiconductor device, use P type dopant to carry out ion and inject to improve the threshold voltage of device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.
5. method according to claim 1, wherein,
For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.
6. according to claim 4 or 5 described methods, wherein, described N type dopant comprises V group element; Described P type dopant comprises III family element.
7. method according to claim 6, wherein said V group element comprises phosphorus and arsenic; Described III family element comprises boron, boron difluoride or indium.
8. method according to claim 7, described ion implantation dosage are 5e11-5e12.
9. method according to claim 1 and 2 is to carry out vertical substantially ion to inject from described opening to the step that substrate carries out the ion injection wherein.
10. method of adjusting the semiconductor device threshold voltage, described method comprises:
A) forming source area, drain region on the substrate, be arranged on that the grid between described source area and drain region pile up on the described substrate, piling up side wall that sidewall forms and the inner layer dielectric layer that covers described source area and drain region at described grid, described grid pile up and comprise dummy grid;
B) remove described dummy grid, expose described substrate to form opening;
C) from described opening substrate is carried out ion and inject, with the doped region of the threshold voltage that is formed for adjusting semiconductor device, the formation degree of depth of described doped region is less than 10 nanometers;
D) carry out thermal annealing, to activate the doping of described doped region; And
E) plated metal grid in described opening, described metal gates covers the inwall of described side wall.
11. method according to claim 10 wherein before described step c, is also carried out thermal annealing to activate the doping of described source area and described drain region.
12. method according to claim 10, wherein said doped region are not overlapping with described source area and drain region.
13. method according to claim 10, wherein,
For the N type semiconductor device, use P type dopant to carry out ion and inject to improve the threshold voltage of device; Using N type dopant to carry out ion injects to reduce the threshold voltage of device.
14. method according to claim 10, wherein,
For the P type semiconductor device, use N type dopant to carry out ion and inject to improve the threshold voltage of device; Using P type dopant to carry out ion injects to reduce the threshold voltage of device.
15. according to claim 13 or 14 described methods, wherein said N type dopant comprises V group element; Described P type dopant comprises III family element.
16. method according to claim 15, wherein said V group element comprises phosphorus and arsenic; Described III family element comprises boron, boron difluoride or indium.
17. method according to claim 16, described ion implantation dosage are 5e11-5e12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102441351A CN102110613A (en) | 2009-12-29 | 2009-12-29 | Method for regulating threshold voltage of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102441351A CN102110613A (en) | 2009-12-29 | 2009-12-29 | Method for regulating threshold voltage of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102110613A true CN102110613A (en) | 2011-06-29 |
Family
ID=44174732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102441351A Pending CN102110613A (en) | 2009-12-29 | 2009-12-29 | Method for regulating threshold voltage of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102110613A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891076A (en) * | 2011-07-22 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Structure of MOS (metal oxide semiconductor) transistor and formation method thereof |
| CN110970495A (en) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | Notched gate for medium voltage devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010014495A1 (en) * | 1999-01-27 | 2001-08-16 | Bin Yu | Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget |
| US6403426B1 (en) * | 1999-03-17 | 2002-06-11 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
-
2009
- 2009-12-29 CN CN2009102441351A patent/CN102110613A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010014495A1 (en) * | 1999-01-27 | 2001-08-16 | Bin Yu | Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget |
| US6403426B1 (en) * | 1999-03-17 | 2002-06-11 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891076A (en) * | 2011-07-22 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Structure of MOS (metal oxide semiconductor) transistor and formation method thereof |
| CN102891076B (en) * | 2011-07-22 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | Structure of MOS transistor and forming method thereof |
| CN110970495A (en) * | 2018-09-28 | 2020-04-07 | 台湾积体电路制造股份有限公司 | Notched gate for medium voltage devices |
| CN110970495B (en) * | 2018-09-28 | 2023-05-16 | 台湾积体电路制造股份有限公司 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220262951A1 (en) | Semiconductor Structure and Methods of Forming Same | |
| CN102087980A (en) | High-performance semiconductor device and forming method thereof | |
| CN101840862B (en) | Forming method of high-performance semiconductor device | |
| CN100353525C (en) | Strained channel cmos device with fully silicided gate electrode and its forming method | |
| CN102087979A (en) | High-performance semiconductor device and method for forming same | |
| US8685814B2 (en) | Transistor device and method of manufacture thereof | |
| CN101728273B (en) | Semiconductor device and method of fabricating the same | |
| US20090166752A1 (en) | Semiconductor Devices and Methods of Manufacture Thereof | |
| CN102110612B (en) | Semiconductor device and manufacturing method thereof | |
| CN102339752A (en) | Method for manufacturing semiconductor device based on gate replacement technique | |
| CN102110609B (en) | High-performance semiconductor device and forming method thereof | |
| CN102157379B (en) | High-performance semiconductor device and manufacturing method thereof | |
| CN102237277B (en) | Semiconductor device and method for forming same | |
| CN103094214B (en) | Manufacturing method for semiconductor device | |
| CN102254824B (en) | Semiconductor device and forming method thereof | |
| US8395221B2 (en) | Depletion-free MOS using atomic-layer doping | |
| CN100405581C (en) | Method for forming non-amorphous, ultra-thin semiconductor devices using sacrificial implantation layer | |
| CN102110613A (en) | Method for regulating threshold voltage of semiconductor device | |
| US7892909B2 (en) | Polysilicon gate formation by in-situ doping | |
| CN103325826A (en) | Semiconductor structure and manufacturing method thereof | |
| CN102157553A (en) | Structure of asymmetrical semi-conductor and forming method thereof | |
| US20080160710A1 (en) | Method of fabricating mosfet device | |
| US11705455B2 (en) | High voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) | |
| US20080194072A1 (en) | Polysilicon gate formation by in-situ doping | |
| EP3291291B1 (en) | Semiconductor device and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110629 |