CN102107852B - Semiconductor nano structure and manufacturing method and application thereof - Google Patents
Semiconductor nano structure and manufacturing method and application thereof Download PDFInfo
- Publication number
- CN102107852B CN102107852B CN 200910312160 CN200910312160A CN102107852B CN 102107852 B CN102107852 B CN 102107852B CN 200910312160 CN200910312160 CN 200910312160 CN 200910312160 A CN200910312160 A CN 200910312160A CN 102107852 B CN102107852 B CN 102107852B
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- cushion
- nanometer
- seed crystal
- crystal material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 209
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000002086 nanomaterial Substances 0.000 title abstract 5
- 239000000463 material Substances 0.000 claims abstract description 69
- 239000013078 crystal Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 55
- 208000012868 Overgrowth Diseases 0.000 claims description 18
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 13
- 239000000956 alloy Substances 0.000 claims description 13
- 230000003287 optical effect Effects 0.000 claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 230000007797 corrosion Effects 0.000 claims description 8
- 238000005260 corrosion Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 229910017083 AlN Inorganic materials 0.000 claims description 7
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910002601 GaN Inorganic materials 0.000 claims description 7
- 229910005540 GaP Inorganic materials 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 7
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 7
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 claims description 7
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 7
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000003362 semiconductor superlattice Substances 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000000835 fiber Substances 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 19
- 229910052710 silicon Inorganic materials 0.000 abstract description 19
- 239000010703 silicon Substances 0.000 abstract description 19
- 230000010354 integration Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- 239000012670 alkaline solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 241000446313 Lamella Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
The invention relates to a semiconductor nano structure, a manufacturing method and application thereof, belonging to the technical field of semiconductor material preparation. The semiconductor nano structure comprises a monocrystalline silicon substrate, a dielectric film, a first buffer layer, a semiconductor seed crystal material, a second buffer layer and a semiconductor nano functional region; the dielectric film is formed on the monocrystalline silicon substrate; the monocrystalline silicon substrate is provided with a patterned window, the first buffer layer is formed on the monocrystalline silicon substrate in the patterned window, and the semiconductor seed crystal material layer is formed on the first buffer layer; the second buffer layer and the semiconductor nanometer functional region are formed on the medium film. When the semiconductor nano structure is integrated and grown on a silicon substrate, the carrier mobility, the geometric characteristics and the heterostructure of the semiconductor nano structure can meet the requirements of high-performance CMOS technology and silicon-based photoelectric integration.
Description
Technical field
The present invention relates to semiconductor applications, relate in particular to a kind of nanometer semiconductor structure and manufacture method and application thereof.
Background technology
In the past in four more than ten years, the silicon base CMOS technology improves performance by down feature sizes, yet when semiconductor technology evolves after nanoscale, the silicon integrated circuit technology is approached its technological limit day by day, and the performance that adopts new material and new construction to promote CMOS has become an important directions of continuity Moore's Law.
Aspect new material, adopting the high mobility channel material is the effective ways that improve the transistor saturation drive current, shorten the grid delay time, and can extend the service life of integrated circuit production line.The room temperature electron mobility of III-V family semi-conducting material is approximately 6-60 times of silicon, has very excellent electron transport performance; And the III-V family semiconductor that has direct band gap is fit to make photoelectric device very much.For the semi-conductive good characteristic of industrial advantage and III-V family in conjunction with si-substrate integrated circuit, integrated growth III-V family semi-conducting material will be the integrated ideal chose of high-performance III-V family's semiconductor CMOS technology and silicon based opto-electronics on silicon substrate.Yet, there are lattice constant mismatch, coefficient of thermal expansion mismatch and crystal structure mismatch between silicon substrate and III-V family semi-conducting material, be difficult to the III-V family semiconductor epitaxial layers of growing high-quality on silicon substrate.Lattice constant mismatch will be introduced a large amount of dislocations and defective in the hetero-epitaxy process; Thermal expansion coefficient difference will cause thermal mismatching, produce thermal stress in the temperature-fall period after high growth temperature, thereby the defect concentration increase of epitaxial layer is even cracked; The crystal structure mismatch often causes reverse farmland problem.The work of heteroepitaxial growth III-V family semi-conducting material mainly launches around solving these three kinds of mismatch problems on silicon substrate.At present method relatively more commonly used is to utilize epitaxy technology certain flexible intermediate layer of growing, and the defective that lattice mismatch is produced is confined in flexible layer, and then the extension graded buffer layer, thereby obtains high-quality III-V family semiconductor epitaxial layers.This method needs that the thicker flexible layers of general several micron and cushion obtain fabricating low-defect-density III-V family semiconductor lamella, thus cause the extension cost high, and also incompatible with the traditional cmos planar technology.a kind of new technology that developed recently gets up at patterned silicon substrate surface heteroepitaxial growth III-V family semi-conducting material, limit dislocation by the depth-width ratio (54.7 ° of h/w＞tan) of selecting figure medium window and expand to the semi-conductive upper surface of III-V family, yet as shown in Figure 1, Fig. 1 is prior art III-V family semi-conducting material 104 dislocation expansion and the structural representation that stops during selective area epitaxial growth on (100) silicon substrate 101 of patterned media 102, its surface always is not parallel to the surface of substrate when selective area epitaxial growth, near [001] crystal orientation that produces because of surface undulation during the crystal growth dislocation 105 can not effectively be eliminated.In case these dislocations expand to the active area of device, will significantly reduce the mobility of carrier and the yield rate of integrated circuit.
Aspect new device structure, adopt the on-plane surface multi-grid structure can effectively suppress transistorized short channel effect.When being contracted to 20 nanometer along with transistorized grid length, the channel thickness of conventional planar MOS device requires to be reduced to 6 nanometers (grid long 1/3rd) and improves the Sub-Threshold Characteristic of device and the on-off ratio of electric current, yet, adopt existing integrated circuit fabrication process to realize that the following ultra-thin raceway groove of 10 nanometers is very difficult.Although adopt the device architecture of novel bigrid (FinFET) or three grids (Tri-Gate) channel thickness can be increased to 2 times of left and right of single gated device, the Fin type structure of these devices is very difficult to make.For example, for the bigrid MOS device (FinFET) that a grid length is 16 nanometers, the width of Fin is only 10 nanometers, and requires depth-width ratio greater than 5 geometric properties, and this has challenge concerning existing photoetching technique and plasma etching technology.And, as shown in Figure 2, Fig. 2 is the structural representation of the prior art III-V semiconductor FinFET of family element manufacturing on the lattice mismatch cushion, the raceway groove 205 of the traditional III-V semiconductor FinFET of family device all is positioned at the top of hetero-epitaxy cushion 206, in the high-temperature process of follow-up semiconductor technology, dislocation easily extends to channel region, and transistor performance is degenerated.
Summary of the invention
The present invention is directed to the active area that dislocation that prior art III-V family semi-conducting material produces during selective area epitaxial growth can expand to device on the patterned silicon substrate, and significantly reduce the mobility of carrier and the yield rate of integrated circuit, and by the device of its manufacturing in the high-temperature process of follow-up semiconductor technology, dislocation easily extends to channel region, make the deficiency of device performance degeneration, a kind of semiconductor III-V family's nanometer semiconductor structure and manufacture method and application thereof are provided.
The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of nanometer semiconductor structure comprises monocrystalline substrate, dielectric film, the first cushion, semiconductor seed material layer, the second cushion and semiconductor nano functional areas; Described dielectric film is formed on described monocrystalline substrate; Have graphical window on described monocrystalline substrate, described the first cushion is formed on monocrystalline substrate in described graphical window, and described semiconductor seed material layer is formed on described the first cushion; Described the second cushion and semiconductor nano functional areas are formed on described dielectric film.
Further, described semiconductor seed crystal material, the second cushion and semiconductor sacrificial layer are commaterial, and comprise following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
Further, described dielectric film layer comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.
Further, the thickness of described dielectric film is greater than 1.41 times of the graphical window width on described monocrystalline substrate.
Further, the lattice paprmeter of described the first cushion is between described monocrystalline silicon and semiconductor seed crystal material, and it comprises following any one material: SiGe alloy, Ge semiconductor, III-V family's semiconductor and their multicomponent alloy.
Further, described nanometer semiconductor structure, it is characterized in that, described semiconductor nano functional areas comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy perhaps comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above as follows: a kind of manufacture method of nanometer semiconductor structure comprises the following steps:
Step 10: form the dielectric film layer on monocrystalline substrate;
Step 20: by the patterned media thin layer, form graphical window on monocrystalline substrate;
Step 30: form the first cushion in the graphical window on described monocrystalline substrate;
Step 40: growing semiconductor seed crystal material on described the first cushion, and form epitaxial lateral overgrowth outgrowth district;
Step 50: the described epitaxial lateral overgrowth outgrowth of etching district, thus form semiconductor seed crystal material side direction crystal face with described dielectric film layer Surface Vertical;
Step 60: epitaxial growth the second cushion on described semiconductor seed crystal material side direction crystal face;
Step 70: selective epitaxial semiconductor nano functional areas and semiconductor sacrificial layer successively on described the second cushion;
Step 80: the top of the described semiconductor seed crystal material of planarization, semiconductor nano functional areas and semiconductor sacrificial layer keeps the epitaxial lateral overgrowth part perpendicular to dielectric film;
Step 90: the described semiconductor seed crystal material of wet method selective corrosion, the second cushion and semiconductor sacrificial layer form nanometer semiconductor structure on dielectric film.
Further, the chemical attack characteristic of described semiconductor nano functional areas is all not identical with semiconductor seed crystal material, the second cushion, semiconductor sacrificial layer, by wet method selective corrosion method, semiconductor seed crystal material, the second cushion and semiconductor sacrificial layer are removed, and do not damaged semiconductor nano functional areas.
Further, described in described step 30, step 40, step 60 and step 70, the method for selective epitaxial comprises: metal organic chemical vapor deposition, high vacuum chemical vapour deposition and other chemical vapour deposition techniques.
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above as follows: a kind of device of being made by nanometer semiconductor structure, described nanometer semiconductor structure is applied to the functional part of following device: field-effect transistor, bipolar transistor, resonance tunnel-through diode, Schottky diode, light emitting devices, photo-detector, fiber waveguide, optical modulator, optical coupler and optical switch.
The invention has the beneficial effects as follows: nanometer semiconductor structure of the present invention makes its carrier mobility, geometric properties and heterojunction structure can satisfy high-performance CMOS technology and the integrated requirement of silicon based opto-electronics on silicon substrate during integrated growth.
Description of drawings
Fig. 1 is the dislocation expansion and the structural representation that stops during selective area epitaxial growth on the patterned silicon substrate of prior art III-V family semi-conducting material;
Fig. 2 is the structural representation of the prior art III-V semiconductor FinFET of family element manufacturing on the lattice mismatch cushion;
The schematic flow sheet of the manufacture method of the nanometer semiconductor structure that Fig. 3 provides for the embodiment of the present invention;
The structural representation of step 20 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 4 provides for the embodiment of the present invention;
The structural representation of step 40 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 5 provides for the embodiment of the present invention;
The structural representation of step 50 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 6 provides for the embodiment of the present invention;
The structural representation of step 70 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 7 provides for the embodiment of the present invention;
The structural representation of step 80 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 8 provides for the embodiment of the present invention;
The structural representation of step 90 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 9 provides for the embodiment of the present invention;
The nanometer semiconductor structure that Figure 10 provides for the embodiment of the present invention is applied to the structural representation of FinFET device;
The nanometer semiconductor structure that Figure 11 provides for the embodiment of the present invention is applied to the structural representation of RTD device.
The specific embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example only is used for explaining the present invention, is not be used to limiting scope of the present invention.
The schematic flow sheet of the manufacture method of the nanometer semiconductor structure that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, manufacture method comprises the following steps:
Step 10: form dielectric film layer 402 on monocrystalline substrate 401.
The crystalline orientation of monocrystalline substrate can be (100), and crystal plane direction can be＜100 〉.The dielectric film layer comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.At the present embodiment, the dielectric film layer is the silicon nitride of high growth temperature.
Step 20: by patterned media thin layer 402, form graphical window 403 on monocrystalline substrate 401.
The structural representation of step 20 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, can adopt dry etching technology to form graphical window on monocrystalline substrate 401, the thickness of dielectric film 402 so just can be limited in misfit dislocation in graphical window 403 greater than 1.41 times of graphical window 403 width on monocrystalline substrate 401.
After this step is completed, then before carrying out next step, adopt and form the V-type groove in the graphical window 403 of anisotropic wet technique on monocrystalline substrate 401.
Step 30: selective epitaxial the first cushion in the graphical window 403 on monocrystalline substrate 401.
The lattice paprmeter of the first cushion is between monocrystalline silicon 401 and semiconductor seed crystal material 405, and it comprises following any one material: SiGe alloy, Ge semiconductor, III-V family's semiconductor and their multicomponent alloy.
Step 40: selective epitaxial semiconductor seed crystal material 405 on the first cushion, and the formation epitaxial lateral overgrowth is given birth to long district 404.
The method of the selective epitaxial of semiconductor seed crystal material 405 comprises: metal organic chemical vapor deposition (MOCVD), high vacuum chemical vapour deposition (UHVCVD) and other chemical vapour deposition techniques (CVD).Semiconductor seed crystal material 405 is proceeded the epitaxial lateral overgrowth outgrowth after filling up graphical window, thereby forms epitaxial lateral overgrowth outgrowth district 404.The top of semiconductor seed crystal material requires to exceed the upper surface of dielectric film layer 402.The dislocation that produces in the misfit dislocation that produces due to monocrystalline substrate and epitaxial process all is limited in graphical window 403 and the upper area of window, thereby the dislocation density in epitaxial lateral overgrowth outgrowth district 404 is extremely low, even without any dislocation.
The structural representation of step 40 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 5 provides for the embodiment of the present invention.As shown in Figure 5, semiconductor seed crystal material 405 comprises following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
Step 50: etching epitaxial lateral overgrowth outgrowth district 404, thus form lateral semiconductor crystal face 406 with dielectric film layer Surface Vertical.
The structural representation of step 50 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 6 provides for the embodiment of the present invention.As shown in Figure 6, the surface light at semiconductor seed crystal material 405 carves needed figure.The method of etching can adopt dry etching, also can adopt wet etching.After the lateral semiconductor crystal face 406 of formation and dielectric film layer Surface Vertical, adopt wet chemical process to carry out polishing etch to its side direction crystal face 406.
Step 60: epitaxial growth the second cushion 407 on lateral semiconductor crystal face 406.
The second cushion 407 is commaterial with semiconductor seed crystal material 405, and the function of the second cushion 407 is to filter dislocation.
Step 70: selective epitaxial the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 successively on the second cushion 407.
The structural representation of step 70 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 7 provides for the embodiment of the present invention.As shown in Figure 7, can extension during at least one semiconductor nano functional areas, the material of semiconductor nano functional areas can be germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.When at least two of extensions semiconductor nano functional areas, the material of each semiconductor nano functional areas can be identical, also can be not identical.When one of extension semiconductor nano functional areas, semiconductor nano functional areas can also comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.In the present embodiment, the first semiconductor nano functional areas 408 and the second semiconductor nano functional areas 410 comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.Semiconductor sacrificial layer 409 is commaterial with semiconductor seed crystal material 405, and the function of semiconductor sacrificial layer 409 is isolation each semiconductor III-V family's semiconductor nano functional areas.The semiconductor nano functional areas can be that the high mobility channel material is made the high-performance CMOS device, also can be hetero-junctions or quantum well structure is made opto-electronic device.The thickness of the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 is accurately controlled by growth time.
Step 80: the top of planarization semiconductor seed crystal material 405, the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 and semiconductor sacrificial layer 409 keeps the epitaxial lateral overgrowth part perpendicular to dielectric film layer 402.
The method of planarization comprises chemical mechanical polishing method, can realize the planarization on surface, and this planarized surface has determined the thickness of the first semiconductor nano functional areas 408 and the second semiconductor nano functional areas 410 to the distance of the upper surface of dielectric film layer 402.
The structural representation of step 80 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 8 provides for the embodiment of the present invention.As shown in Figure 8,
Step 90: wet method selective corrosion semiconductor seed crystal material 405, the second cushion 407 and semiconductor sacrificial layer 409 form nanometer semiconductor structure on the dielectric film layer.
The structural representation of step 90 correspondence in the manufacture method of the nanometer semiconductor structure that Fig. 9 provides for the embodiment of the present invention.As shown in Figure 9, because the first semiconductor nano functional areas 408, the second semiconductor nano functional areas 410 have different chemical attack characteristics from semiconductor seed crystal material 405, the second cushion 407, semiconductor sacrificial layer 409, so semiconductor seed crystal material 405, the second cushion 407 and semiconductor sacrificial layer 409 can optionally be removed by chemical etching technology, corrosion selectively requires greater than 5.
Semiconductor nano functional areas, the second cushion, semiconductor sacrificial layer and semiconductor seed crystal material are the Lattice Matching relation, perhaps have certain lattice mismatch, the lattice mismatch of the lattice mismatch of the lattice mismatch of semiconductor nano functional areas and semiconductor seed crystal material, the second cushion and semiconductor seed crystal material, semiconductor sacrificial layer and semiconductor seed crystal material is all lower than ± 5%.
The manufacture method of nanometer semiconductor structure of the present invention adopts the wrong filtration methods of two steps, i.e. the technology that combines with selective epitaxial of graph substrate, the semiconductor seed crystal material of integrated growth utmost point low-dislocation-density on monocrystalline substrate; Then utilize advanced epitaxy technology can accurately control the characteristics of semiconductor film layer thickness, selective epitaxial semiconductor nano functional areas on the side direction crystal face of semiconductor seed crystal material; Then use flatening process and semiconductor sacrificial layer technology to form nanometer semiconductor structure.Be that the present invention utilizes graph substrate constituency epitaxy technology to be terminated in by the dislocation that lattice mismatch causes on the side wall of graphical window, use simultaneously constituency epitaxial lateral overgrowth technology further to filter dislocation, form utmost point low-dislocation-density (＜10
3cm
-2) the lateral semiconductor crystal face, by in conjunction with epitaxial lateral overgrowth means, flatening process and sacrificial layer technology, the final nanometer semiconductor structure of realizing utmost point low-dislocation-density, high mobility, high integration on silicon substrate, thus satisfy high-performance semiconductor electronic device and the integrated material requirements of silica-based photoelectric foreign substance.
The nanometer semiconductor structure that Figure 10 provides for the embodiment of the present invention is applied to the structural representation of FinFET device.As shown in figure 10, the manufacturing process of FinFET device is: at first adopt low-pressure chemical vapor deposition method (LPCVD) at the SiNx medium 502 of Si (100) 501 surface high-temp growth one deck 200 nanometers, litho pattern also uses RIE etching SiNx to form the wide window of 100 nanometers, adopts alkaline solution to corrode the V-type groove in window; Put into mocvd growth chamber constituency extension InP seed crystal material (selecting GaAs the first cushion) after RCA cleans, then outgrowth realizes the epitaxial lateral overgrowth outgrowth; Litho pattern also adopts RIE etching epitaxial lateral overgrowth outgrowth district to form vertical side direction crystal face, then carries out polishing etch; Put into mocvd growth chamber after thoroughly cleaning and carry out the constituency extension, successively extension 100 nanometer InP the second cushions, 20 nanometer N-type In
0.7Ga
0.3As raceway groove 503,100 nanometer InP sacrifice layers, 20 nanometer P type GaAs
0.3Sb
0.7Raceway groove 504 and 100 nanometer InP sacrifice layers; Use cmp method (CMP) planarized surface, the height of controlling channel material is about 120 nanometers, then uses hydrochloric acid solution selective corrosion InP sacrifice layer, forms symmetrical In
0.7Ga
0.3As and GaAs
0.3Sb
0.7Channel array; Adopt at last conventional CMOS manufacturing process to complete ALD LaAl0
3Gate medium 506, TaN/W grid metal 505, medium side wall, source are leaked and are injected and metallization process.Compare with traditional silicon CMOS technology, silica-based high mobility III-V family its speed of semiconductor CMOS technology that adopts that the present invention makes improves more than 2 times, order of magnitude of power-dissipation-reduced, be after the ideal chose of 15 nanometers (post-15nm) CMOS technology.
The nanometer semiconductor structure that Figure 11 provides for the embodiment of the present invention is applied to the structural representation of RTD device.As shown in figure 11, the manufacturing process of RTD device is: at first adopt low-pressure chemical vapor deposition method (LPCVD) at the SiNx medium 602 of Si (100) 601 surface high-temp growth one deck 200 nanometers, litho pattern also uses RIE etching SiNx to form the wide window of 100 nanometers, adopts alkaline solution to corrode the V-type groove in window; Put into mocvd growth chamber selective epitaxial InP seed crystal material (selecting GaAs the first cushion) after RCA cleans, then outgrowth realizes epitaxial lateral overgrowth; Litho pattern also adopts RIE etching epitaxial lateral overgrowth outgrowth district to form vertical side direction crystal face, then carries out polishing etch; Put into mocvd growth chamber after thoroughly cleaning and carry out the constituency extension, successively extension InP the second cushion, semiconductor nano functional areas 603 (being AlAs/InGaAs/AlAs double potential barrier RTD heterojunction structure in this example), InGaAs ohmic contact layer 604 and InP sacrifice layer; Use cmp method (CMP) planarized surface, then use hydrochloric acid solution selective corrosion InP sacrifice layer, form the RTD epitaxial structure of horizontal direction; Adopt at last conventional semiconductor technology to make Ohmic contact 605, mesa etch, dielectric passivation layer 606.By implementing the present invention, can realize high performance AlAs/InGaAs/AlAs double potential barrier RTD on silicon substrate, by in conjunction with RTD and CMOS technology, will provide a new technology platform for high integration MULTI-VALUED LOGIC CIRCUIT, ultrahigh-speed and low-power-consumption circuit.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a nanometer semiconductor structure, is characterized in that, comprises monocrystalline substrate, dielectric film, the first cushion, semiconductor seed crystal material, the second cushion, semiconductor nano functional areas and semiconductor sacrificial layer; Described dielectric film is formed on described monocrystalline substrate; Have graphical window on described monocrystalline substrate, described the first cushion is formed on monocrystalline substrate in described graphical window, and described semiconductor seed material layer is formed on described the first cushion; Described the second cushion and semiconductor nano functional areas are formed on described dielectric film, by selective epitaxial, semiconductor nano functional areas and semiconductor sacrificial layer are arranged on the second cushion.
2. nanometer semiconductor structure according to claim 1, it is characterized in that, described semiconductor seed crystal material, the second cushion and semiconductor sacrificial layer are commaterial, and comprise following any one material: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy.
3. nanometer semiconductor structure according to claim 1, is characterized in that, described dielectric film comprises following any one or a few material: silica, silicon nitride, carborundum, metal oxide and metal nitride.
4. nanometer semiconductor structure according to claim 1, is characterized in that, the thickness of described dielectric film is greater than 1.41 times of the graphical window width on described monocrystalline substrate.
5. nanometer semiconductor structure according to claim 1, it is characterized in that, the lattice paprmeter of described the first cushion is between described monocrystalline silicon and semiconductor seed crystal material, and it comprises following any one material: SiGe alloy, III-V family's semiconductor and their multicomponent alloy.
6. nanometer semiconductor structure according to claim 1, it is characterized in that, described semiconductor nano functional areas comprise following any one material or different materials: germanium, gallium phosphide, GaAs, indium phosphide, indium arsenide, gallium antimonide, indium antimonide, gallium nitride, aluminium nitride, indium nitride and their multicomponent alloy perhaps comprise the function combination of following any one or a few structure: semiconductor P-N knot, heterojunction semiconductor, semiconductor quantum well, semiconductor superlattice, semiconductor optical waveguide and optical semiconductor reflector.
7. the manufacture method of a nanometer semiconductor structure, is characterized in that, described manufacture method comprises the following steps:
Step 10: form the dielectric film layer on monocrystalline substrate;
Step 20: by the patterned media thin layer, form graphical window on monocrystalline substrate;
Step 30: selective epitaxial the first cushion in the graphical window on described monocrystalline substrate;
Step 40: selective epitaxial semiconductor seed crystal material on described the first cushion, and form epitaxial lateral overgrowth outgrowth district;
Step 50: the described epitaxial lateral overgrowth outgrowth of etching district, thus form semiconductor seed crystal material side direction crystal face with described dielectric film layer Surface Vertical;
Step 60: selective epitaxial the second cushion on described semiconductor seed crystal material side direction crystal face;
Step 70: selective epitaxial semiconductor nano functional areas and semiconductor sacrificial layer successively on described the second cushion;
Step 80: the top of the described semiconductor seed crystal material of planarization, semiconductor nano functional areas and semiconductor sacrificial layer keeps the epitaxial lateral overgrowth part perpendicular to the dielectric film surface;
Step 90: the described semiconductor seed crystal material of wet method selective corrosion, the second cushion and semiconductor sacrificial layer form nanometer semiconductor structure on dielectric film.
8. the manufacture method of nanometer semiconductor structure according to claim 7, it is characterized in that, the chemical attack characteristic of described semiconductor nano functional areas is all not identical with semiconductor seed crystal material, the second cushion, semiconductor sacrificial layer, by wet method selective corrosion method, semiconductor seed crystal material, the second cushion and semiconductor sacrificial layer are removed, and do not damaged semiconductor nano functional areas.
9. the manufacture method of nanometer semiconductor structure according to claim 7, it is characterized in that, described in described step 30, step 40, step 60 and step 70, the method for selective epitaxial comprises: metal organic chemical vapor deposition or high vacuum chemical vapour deposition.
10. device of being made by described nanometer semiconductor structure as arbitrary in claim 1 to 6, it is characterized in that, described nanometer semiconductor structure is applied to the functional part of following device: field-effect transistor, bipolar transistor, resonance tunnel-through diode, Schottky diode, light emitting devices, photo-detector, fiber waveguide, optical modulator, optical coupler or optical switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910312160 CN102107852B (en) | 2009-12-24 | 2009-12-24 | Semiconductor nano structure and manufacturing method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910312160 CN102107852B (en) | 2009-12-24 | 2009-12-24 | Semiconductor nano structure and manufacturing method and application thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102107852A CN102107852A (en) | 2011-06-29 |
| CN102107852B true CN102107852B (en) | 2013-05-22 |
Family
ID=44172150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910312160 Active CN102107852B (en) | 2009-12-24 | 2009-12-24 | Semiconductor nano structure and manufacturing method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102107852B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102383192B (en) * | 2011-07-29 | 2014-06-18 | 上海新傲科技股份有限公司 | Growth method of germanium substrate and germanium substrate |
| CN102969360A (en) * | 2012-12-14 | 2013-03-13 | 中国科学院微电子研究所 | III-V group semiconductor nanowire array field effect transistor |
| CN103022135B (en) * | 2012-12-14 | 2015-08-26 | 中国科学院微电子研究所 | III-V semiconductor nanowire transistor device and manufacturing method thereof |
| EP3428957B1 (en) * | 2013-12-20 | 2021-12-08 | Huawei Technologies Co., Ltd. | Method for producing semiconductor device |
| CN112201722B (en) * | 2019-07-08 | 2022-01-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | Multi-band detection structure and manufacturing method thereof |
| CN114024210B (en) * | 2021-11-05 | 2023-05-16 | 电子科技大学中山学院 | Silicon-based vertical cavity surface emitting laser |
| CN114141911B (en) * | 2021-11-10 | 2023-05-16 | 重庆康佳光电技术研究院有限公司 | Epitaxial structure, manufacturing method thereof and light-emitting device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996613A (en) * | 2000-08-22 | 2007-07-11 | 哈佛学院董事会 | Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices |
| CN101038943A (en) * | 2006-12-27 | 2007-09-19 | 电子科技大学 | Method for preparation of a-b orientated ZnO nanometer linear array |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7670908B2 (en) * | 2007-01-22 | 2010-03-02 | Alpha & Omega Semiconductor, Ltd. | Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling |
| WO2009118979A1 (en) * | 2008-03-28 | 2009-10-01 | パナソニック株式会社 | Nitride semiconductor light-emitting device |
-
2009
- 2009-12-24 CN CN 200910312160 patent/CN102107852B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996613A (en) * | 2000-08-22 | 2007-07-11 | 哈佛学院董事会 | Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices |
| CN101038943A (en) * | 2006-12-27 | 2007-09-19 | 电子科技大学 | Method for preparation of a-b orientated ZnO nanometer linear array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102107852A (en) | 2011-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102107852B (en) | Semiconductor nano structure and manufacturing method and application thereof | |
| US9934967B2 (en) | Formation of devices by epitaxial layer overgrowth | |
| US10074536B2 (en) | Lattice-mismatched semiconductor structures and related methods for device fabrication | |
| US20080006862A1 (en) | Compounds semiconductor-on-silicon wafer with a silicon nanowire buffer layer | |
| CN101378017A (en) | Growth method for epitaxial layer on silicon-based graphical substrate | |
| EP2846353B1 (en) | Method of manufacturing a complementary metal oxide semiconductor device | |
| CN106480498B (en) | A kind of nano graph substrate side epitaxial silicon based quantum dot laser equipment material and preparation method thereof | |
| CN105074872A (en) | Lattice mismatched heterojunction structures and devices made therefrom | |
| JP6525554B2 (en) | CMOS device including substrate structure | |
| US8680510B2 (en) | Method of forming compound semiconductor | |
| US8168517B2 (en) | Method for epitaxial growth and epitaxial layer structure using the method | |
| US9558943B1 (en) | Stress relaxed buffer layer on textured silicon surface | |
| CN102280469B (en) | Epitaxial growth of III-V compound semiconductors on silicon surfaces | |
| US10636882B2 (en) | Method for forming a semiconductor structure and a semiconductor structure manufactured thereof | |
| US8846503B1 (en) | Self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane | |
| CN108461535B (en) | Micro-nano transistor and micro-nano transistor manufacturing method | |
| KR101547535B1 (en) | manufacturing method of multi semiconductor epi-layer on SOI(001) substrate | |
| KR101556089B1 (en) | manufacturing method of semiconductor epi-layer on SOI(001) substrate | |
| Caymax et al. | Epitaxy of III–V based channels on Si and transistor integration for 12-10nm node CMOS | |
| TW201403866A (en) | Semiconductor apparatus and a method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240408 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Country or region after: China Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences Country or region before: China |