CN102104376B - Phase generation device and phase generation method - Google Patents

Abstract

The invention discloses a phase generation device and a phase generation method, and is capable of reducing the power consumption of a circuit during operation substantially, and improving the glitch phenomenon, generated during an operation process, of the circuit. The phase generation device disclosed by the invention comprises a phase selection unit and a phase generation unit. The phase selection unit is used for selecting one of a plurality of input frequencies according to a part of bits of a digital signal in order to generate a reference frequency, wherein the input frequencies have different phases respectively. The phase generation unit is used for eliminating the frequency of the reference frequency, and selectively carrying out delay treatment on the frequency-eliminated reference frequency according to the other part of bits of the digital signal in order to generate an output frequency.

Description

Phase generating device and phase generating method

Technical Field

The present invention relates to a phase generator and related method, and more particularly, to a digital phase generator and related method.

Background

Please refer to fig. 1. Fig. 1 is a schematic diagram of a conventional phase generator 10. For example, Phase generator 10 may be a Phase digital-to-analog converter (Phase DAC). Conventionally, the phase generator 10 generates a phase in an analog manner. More specifically, the phase generator 10 is used to interpolate two differential input frequencies (CLK0+, CLK0-, CLK1+, CLK1-) with different phases to an output frequency CLK2 with a new phase. The phase generator 10 includes a first differential pair transistor M1, M2, a second differential pair transistor M3, M4, a first load 12, a second load 14, a first reference current source 16 and a second reference current source 18, wherein the gates Na, Nb of the first differential pair transistor M1, M2 respectively receive a first positive input frequency CLK0+ and a first negative input frequency CLK0+ of the first differential input frequency, and the gates Nc, Nd of the second differential pair transistor M3, M4 respectively receive a second positive input frequency CLK1+ and a second negative input frequency CLK1 of the second differential input frequency. The first reference current source 16 and the second reference current source 18 respectively provide a first current I1 and a second current I2 to the first differential pair transistors M1 and M2 and the second differential pair transistors M3 and M4. Please note that, the coupling relationship between each component in the phase generator 10 is shown in fig. 1 and is not described herein.

The phase generator 10 interpolates the output clock CLK2 with a new phase according to the magnitude relationship between the first current I1 and the second current I2, as shown in fig. 2. FIG. 2 is a timing diagram of the differential input frequency (CLK0+, CLK0-, CLK1+, CLK1-) and the output frequency (CLK2+, CLK2-) of the phase generator 10. The gate terminals Na and Nb are inputted at time ta with the first positive input clock CLK0+ and the first negative input clock CLK0-, respectively, and the gate terminals Nc and Nd are inputted at time td with the second positive input clock CLK1+ and the second negative input clock CLK1-, respectively. If the first current I1 and the second current I2 are both divided into ten equal parts, when the ratio between the first current I1 and the second current I2 is 5: 5, the phase of the output frequency (CLK2+, CLK2-) is just between the first differential input frequency (CLK0+, CLK0-) and the second differential input frequency (CLK1+, CLK1-), i.e. the transition of the output frequency (CLK2+, CLK2-) occurs at the time point tc. When the ratio between the first current I1 and the second current I2 is 9: 1, a transition of the output frequency (CLK2+, CLK2-) occurs at time tb. In other words, the phase of the output frequency (CLK2+, CLK2-) is closer to the first differential input frequency (CLK0+, CLK0-) as the first current I1 is larger. Conversely, the larger the second current I2, the closer the phase of the output frequency (CLK2+, CLK2-) is to the second differential input frequency (CLKI +, CLK1-), and so on. Thus, when the first current I1 and the second current I2 are divided into ten equal parts, the phase generator 10 can generate ten different phases between the time points ta-td according to the distribution of the first current I1 and the second current I2. However, since the phase generator 10 generates different phases by current driving (current driving), the phase generator 10 has a relatively high power consumption. Therefore, how to improve the power consumption of a phase generator has become a problem to be solved in the mixed signal field.

Disclosure of Invention

The present invention provides a phase generating apparatus and a phase generating method, which can greatly reduce the power consumption of the circuit during operation and improve the Glitch (Glitch) phenomenon generated during the operation of the circuit.

In order to solve the technical problems, the invention provides the following technical scheme:

the invention provides a phase generating device. The phase generating device comprises a phase selecting unit and a phase generating unit. The phase selection unit is used for selecting one of a plurality of input frequencies according to part of bits of the digital signal to generate a reference frequency, wherein the input frequencies respectively have different phases. The phase generating unit is used for frequency dividing the reference frequency and selectively delaying the frequency-divided reference frequency according to the other part of bits of the digital signal so as to generate the output frequency.

The present invention also provides a phase generating method for generating an output frequency having a desired phase according to a digital signal, the phase generating method comprising the steps of: (a) providing a plurality of input frequencies, and selecting one of the input frequencies according to a part of bits of the digital signal to generate a reference frequency, wherein the input frequencies have different phases; (b) dividing the reference frequency to generate a divided reference frequency: and (c) selectively delaying the divided reference frequency according to another part of bits of the digital signal to generate the output frequency.

The phase generating device and the phase generating method of the present invention can avoid using the conventional current driving (current driving) circuit by implementing the phase converting device in a digital circuit manner, so that the phase generating device 100, 800 can greatly reduce the power consumption of the circuit during operation. On the other hand, through the selection circuit 106 and the related method disclosed by the present invention, the phase generating apparatus 100, 800 can further improve the Glitch (Glitch) phenomenon generated during the operation of the circuit.

Drawings

Fig. 1 is a schematic diagram of a conventional phase generator.

FIG. 2 is a timing diagram of a differential input frequency and an output frequency of the generator converter of FIG. 1.

FIG. 3 is a schematic diagram of a phase generating device according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of an embodiment of a selection circuit of the phase generating device of fig. 3.

FIG. 5 is a timing diagram of a plurality of input frequencies, a first selected input frequency, a first divided frequency, a second frequency, a reference frequency, and a fifth divided frequency of the phase generating apparatus of FIG. 3.

FIG. 6 is a timing diagram of a second frequency, a second frequency-dividing frequency, the first output frequency, the fifth frequency-dividing frequency and a sixth frequency-dividing frequency of the phase generator shown in FIG. 3.

FIG. 7 is a timing diagram of the first output frequency, the second output frequency, an output signal, a selection signal, a control signal and an output frequency of the selection circuit of the phase generating apparatus shown in FIG. 3.

Fig. 8 is a schematic diagram of another embodiment of the phase generating device according to the present invention.

[ description of main reference symbols ]

10 phase generator

12. 14 load

16. 18 reference current source

100. 800 phase generating device

102. 104, 802, 804 frequency generating device

106. 806 selection circuit

108 reference phase generating circuit

1021. 1041, 1082, 8021, 8041, 8082 phase selector

1022. 1024, 1026, 1042, 1044, 1046, 8023, 8043 inverters

1023. 1025, 1043, 1045, 1084, 1086, 8022, 8042, 8084 frequency divider

1062 multiplexer

1064 control signal generating circuit

1064a AND gate

1064b buffer

210. 410 phase selection unit

220. 230, 420, 430, 820, 840 phase generation unit

Detailed Description

Please refer to fig. 3. Fig. 3 is a schematic diagram of an embodiment of the phase generating apparatus 100 according to the present invention. The phase generating apparatus 100 utilizes a plurality of input frequencies Sin to convert a digital signal into an output frequency Sout having a specific output phase, wherein the specific output phase corresponds to the digital signal. The input frequencies Sin have different input phases, wherein the input phase of each input frequency Sin has substantially the same phase difference with the input phase of its neighboring input frequency Sin. For example, if there are 8 input frequencies Sin (i.e., Sin1-Sin8), the 8 input frequencies Sin may be used to represent 8 different input phases. Therefore, for the sake of better clarity of the description of the spirit of the present invention, the following description of the phase generating apparatus 100 is given by taking the input frequency Sin of 8 different input phases and the output frequency Sout with a specific output phase generated according to the digital signal with 6 bits (i.e., (b5, b4, b3, b2, b1, b 0)).

In the embodiment of fig. 3, the phase generating device 100 includes a first and a second frequency generating device 102, 104, a selecting circuit 106 and a reference phase generating circuit 108. The first clock generating device 102 generates a first output clock Sc1 having a first output phase P1 according to the input clock Sin and a first digital signal Sd 1. The second clock generating device 104 generates a second output clock Sc2 having a second output phase according to the input clock Sin and a second digital signal Sd 2. The selection circuit 106 is coupled to the first and second frequency generating devices 102 and 104, and is used for selecting one of the first and second output frequencies Sc1 and Sc2 generated by the first and second frequency generating devices 102 and 104, respectively, as the output frequency Sout according to a selection signal Sup. The reference phase generating circuit 108 is used for providing at least one reference phase to the first and second frequency generating devices 102 and 104 as a reference phase for the first output phase P1 and the second output phase P2. In this embodiment, the second output frequency Sc2 generated by the second frequency generating device 104 is the output frequency Sout currently output by the phase generating device 100, and the first output frequency Sc1 generated by the first frequency generating device 102 is the output frequency Sout to be output by the phase generating device 100. In other words, the selection circuit 106 is used to switch the second output frequency Sc2 currently used as the output frequency Sout to the first output frequency Sc1 according to the selection signal Sup, which is used as the output frequency Sout to be outputted next.

The first frequency generating device 102 includes a first phase selecting unit 210, a first phase generating unit 220, and a second phase generating unit 230. The first phase selection unit 210 selects one of the input frequencies Sin according to a part of bits of the first digital signal Sd1 to generate a reference frequency (i.e., the first frequency Ssc1 in the embodiment of fig. 3). The first phase generating unit 220 divides the reference frequency, and selectively delays the divided reference frequency according to another part of bits of the first digital signal Sd 1. The second phase generating unit 230 further divides the output frequency of the first phase generating unit 220, and selectively delays the divided output frequency of the first phase generating unit 220 according to another part of bits of the first digital signal Sd 1. In the embodiment of fig. 3, the first phase selecting unit 210 includes a first phase selector 1021 and a first inverter 1022. The first phase generating unit 220 includes a first frequency divider 1023 and a second inverter 1024. The second phase generating unit 230 includes a second frequency divider 1025 and a third inverter 1026. Wherein the first inverter 1022, the second inverter 1024 and the third inverter 1026 are used to delay the phase by 180 degrees. The first phase selector 1021 is configured to select a first selected input frequency Ss1 having a first corresponding phase Ps1 among the input frequencies Sin according to the digital signals (b5, b4, b3, b2, b1, b0), and output the first selected input frequency Ss1, wherein b5 is a most Significant Bit (mostsnificant Bit) among the digital signals (b5, b4, b3, b2, b1, b0), and b0 is a Least Significant Bit (Least Significant Bit) among the digital signals (b5, b4, b3, b2, b1, b0), and so on. Further, the first phase selector 1021 selects one of the input frequencies Sin as the first selected input frequency Ss1 according to a first set of bits in the digital signal (b5, b4, b3, b2, b1, b 0). The first inverter 1022 is coupled to the first phase selector 1021, and is configured to selectively invert the first selected input clock Ss1 according to a second bit set of the digital signals (b5, b4, b3, b2, b1, b0) to generate a first clock Ssc 1. In the present invention, the first bit set comprises at least one least significant bit of the digital signals (b5, b4, b3, b2, b1, b0), and the first inverter 1022 selectively inverts according to the at least one least significant bit of the second bit set. More specifically, in the present embodiment, the first bit set coefficient bit signal (b5, b4, b3, b2, b1, b0) includes (b2, b1, b0) bits. Since 8 input frequencies Sin have 8 different input phases, the first phase selector 1021 selects one of the input frequencies Sin according to the (b2, b1, b0) bits. And the second bit set is the b3 bit of the digital signal (b5, b4, b3, b2, b1, b 0). When the b3 bit is high, the first inverter 1021 inverts the first selected input clock Ss1 to generate the first clock Ssc 1. On the other hand, when the b3 bit is a low bit, the first inverter 1021 does not perform the inversion process, and directly outputs the selected input clock Ss1 as the first clock Ssc 1.

The first frequency divider 1023 is coupled to the first inverter 1022 and is used for performing a frequency dividing operation on the first frequency Ssc1 to generate a first frequency Sdc 1. The second inverter 1024 is coupled to the first frequency divider 1023 for selectively inverting the first frequency-dividing frequency Sdc1 according to the bit b4 of the digital signal (b5, b4, b3, b2, b1, b0) to generate a second frequency Ssc2 with a second phase Ps 2. When the second inverter 1024 does not invert the first division frequency Sdc1, the first division frequency Sdc1 is the second frequency Ssc 2. When the second inverter 1024 inverts the first frequency Sdc1, the output of the second inverter 1024 is the second frequency Ssc 2. The second frequency divider 1025 receives the second frequency Ssc2, and performs a frequency dividing operation on the second frequency Ssc2 to generate a second frequency Sdc 2. The third inverter 1026 is coupled to the second frequency divider 1025 and is configured to selectively invert the second divided frequency Sdc2 according to the bit b5 of the digital signal (b5, b4, b3, b2, b1, b0) to generate the first output frequency Sc1 having the first output phase P1. When the third inverter 1026 does not invert the second division frequency Sdc2, the second division frequency Sdc2 is the first output frequency Sc 1. When the third inverter 1026 inverts the second frequency division frequency Sdc2, the output of the third inverter 1026 is the first output frequency Sc 1.

The second frequency generating device 104 includes a second phase selecting unit 410, a third phase generating unit 420, and a fourth phase generating unit 430. The second phase selection unit 410 includes a second phase selector 1041 and a fourth inverter 1042. The third phase generating unit 420 includes a third frequency divider 1043 and a fifth inverter 1044. The fourth phase generating unit 430 includes a fourth frequency divider 1045 and a sixth inverter 1046. The second frequency generating device 104 generates a second output frequency Sc2 according to a digital signal (c5, c4, c3, c2, c1, c0), and the detailed operation principle thereof is the same as that of the first frequency generating device 102, and is not described herein again.

Referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of the selection circuit 106 of the phase generating apparatus 100 of fig. 3. The selection circuit 106 includes a multiplexer 1062 and a control signal generating circuit 1064. The multiplexer 1062 has a first node N1 and a second node N2 coupled to the first and second frequency generating devices 102 and 104, respectively, for selecting one of the first output frequency Sc1 and the second output frequency Sc2 as the output frequency Sout according to a control signal Se. The control signal generating circuit 1064 is used for generating the control signal Se according to the first output frequency Sc1, the second output frequency Sc2 and the selection signal Sup. In this embodiment, the control signal generating circuit 1064 includes an AND gate (ANDGate)1064a and a register 1064 b. The and gate 1064a has two inputs N3 and N4 for receiving the first output clock Sc1 and the second output clock Sc2, respectively, and an output N5 for outputting an output signal Sn 5. The register 1064b has a data input terminal D for receiving the selection signal Sup, a clock control terminal CK coupled to the and gate 1064a for receiving the output signal Sn5, and a data output terminal Q for outputting the control signal Se.

In the present embodiment, since the digital signal input to the phase generating apparatus 100 has 6 bits, the output frequency Sout generated by the phase generating apparatus 100 can have 64 different phase selections. On the other hand, since the phase generating apparatus 100 of the present embodiment generates the output frequency Sout with the frequency of 100MHz from 8 phases of the 8 input frequencies Sin with the frequency of 400MHz, wherein the output frequency Sout can be selected with 64 different phases, the first frequency divider 1023 and the second frequency divider 1025 perform a frequency dividing operation of dividing the first frequency Ssc1 and the second frequency Ssc2 by one. Similarly, the third frequency divider 1043 and the fourth frequency divider 1045 also perform a frequency dividing operation of dividing the third frequency Ssc3 and the fourth frequency Ssc4 by one. The detailed operation and function of the phase generator 100 are further described in the following paragraphs.

Referring to fig. 5, fig. 5 is a timing diagram of the 8 input frequencies Sin, the first selected input frequency Ss1, the first frequency Ssc1, the first frequency Sdc1 and the second frequency Ssc2 of the phase generating apparatus 100 shown in fig. 3. To more clearly describe the spirit of the present invention, the phase generating apparatus 100 of the present embodiment is illustrated by the digital signals (b5, b4, b3, b2, b1, b0) being (0, 0, 0, 0, 0, 0) and (1, 1, 1, 1, 1, 1), respectively, the frequency of each input frequency Sin is 400MHz, and the frequency of the first output frequency Sc1 is 100 MHz. Therefore, when the input frequencies Sin are inputted to the phase generating apparatus 100, there are 8 different phases between the time points t1-t2, i.e., within a half cycle of the first input frequency Sin1 of the input frequencies Sin. When the digital signal (b5, b4, b3, b2, b1, b0) is (0, 0, 0, 0, 0, 0), the first phase selector 1021 selects one of the input frequencies Sin according to the first bit set (b2, b1, b0) (i.e., (0, 0, 0)) in the digital signal (0, 0, 0, 0, 0, 0). Since the first specific bit set (0, 0, 0) corresponds to the first input clock Sin1 of the input clocks Sin, the first phase selector 1021 selects the input clock Sin1 as the first selected input clock Ss 1. Then, the first inverter 1022 is used to selectively invert the first selected input frequency Ss1 according to the second bit set (i.e., b3 equals 0) of the digital signal (0, 0, 0, 0, 0, 0). Since the second bit set b3 is a low-level bit, the first inverter 1021 does not invert the first selected input clock Ss1, and directly outputs (bypass) the first selected input clock Ss1 as the first clock Ssc 1. Thus, the first clock Ssc1 having the first corresponding phase Ps1_ (0, 0, 0, 0, 0, 0) (relative to the time t1) is generated.

On the other hand, when the digital signal (b4, b3, b2, b1, b0) is (1, 1, 1, 1, 1, 1), the first phase selector 1021 selects one of the input frequencies Sin according to the first bit set (b2, b1, b0) (i.e., (1, 1, 1)) in the digital signal (1, 1, 1, 1, 1, 1). Since the first bit set (1, 1, 1) corresponds to the input frequencies Sin8, the first phase selector 1021 selects the input frequency Sin8 as the first selected input frequency Ss 1. Then, the first inverter 1022 is used to selectively invert the first selected input frequency Ss1 according to the second bit set (i.e., b3 equals 1) of the digital signal (1, 1, 1, 1, 1, 1). Since the second bit set b3 is a high bit, the first inverter 1022 inverts the first selected input clock Ss1 and outputs the inverted input clock Sin8 (i.e., Sin8_ bar) as the first clock Ssc 1. As such, the first frequency Ssc1 having the first corresponding phase Ps1_ (1, 1, 1, 1, 1, 1) (the phase at the time point t3 with respect to the time point t1) is generated, as shown in fig. 5. In other words, since each of the input frequencies Sin can generate 8 input frequencies with 8 phases corresponding to the other 8 phases through the inversion process, the output frequency of the first inverter 1022 (i.e., the first frequency Ssc1) can have 16 different phase selections (relative to the time point t 1).

Then, the first frequency Ssc1 is divided by two by the first frequency divider 1023 to generate a first divided frequency Sdc 1. Taking the digital signals (b5, b4, b3, b2, b1, b0) as (0, 0, 0, 0, 0, 0), since the bit b4 in the digital signals (b5, b4, b3, b2, b1, b0) is the low bit, the second inverter 1024 does not invert the first division frequency Sdc1 and directly outputs (bypass) the first division frequency Sdc1 as the second frequency Ssc 2. Thus, the second clock Ssc2 having the second phase Ps2_ (0, 0, 0, 0, 0, 0) (corresponding to the time t1) is generated. On the other hand, taking the digital signals (b5, b4, b3, b2, b1, b0) as (1, 1, 1, 1, 1), since the bit b4 in the digital signals (b5, b4, b3, b2, b1, b0) is high, the second inverter 1024 inverts the first divided frequency Sdc1 to generate an inverted first divided frequency Sdc1 (i.e., Sdc1_ bar), and outputs the inverted first divided frequency Sdc1 as the second frequency Ssc 2. Thus, the second frequency Ssc2 generated by the second inverter 1024 has the second phase Ps2_ (1, 1, 1, 1) (time t4 relative to time t 1). In other words, after the first frequency Ssc1 generated by the first inverter 1022 is divided by the first frequency divider 1023, the frequency of the first divided frequency Sdc1 is 200MHz, and the phase of the first divided frequency Sdc1 can have 16 different phases selected according to the values of the digital signals (b5, b4, b3, b2, b1, b 0). Similarly, since each input frequency can generate 16 frequencies with another 16 different phases through the inversion process of the second inverter 1024, the phase of the second frequency Ssc2 output by the second inverter 1024 can have 32 different phase selections. Note that the frequency of the second frequency Ssc2 having 32 possible phases may also be 200MHz at this time.

Then, the second frequency Ssc2 with the second phase Ps2 and the frequency of 200MHz is transmitted to the second frequency divider 1025 to generate the second frequency division Sdc 2. Please refer to fig. 6. Fig. 6 is a timing diagram of the second clock Ssc2, the second divided clock Sdc2 and the first output clock Sc1 of the phase generating apparatus 100 shown in fig. 3. Similarly, taking the digital signals (b5, b4, b3, b2, b1, b0) as (0, 0, 0, 0, 0, 0), since the bit b5 in the digital signals (b5, b4, b3, b2, b1, b0) is low, the third inverter 1026 does not invert the second division frequency Sdc2 and directly outputs the second division frequency Sdc2 as the first output frequency Sc 1. Thus, the first output frequency Sc1 having the output phase P1_ (0, 0, 0, 0, 0, 0) (relative to the time t1) is generated. On the other hand, taking the digital signals (b5, b4, b3, b2, b1, b0) as (1, 1, 1, 1, 1), since the bit b5 in the digital signals (b5, b4, b3, b2, b1, b0) is high, the third inverter 1026 inverts the second divided frequency Sdc2 to generate an inverted second divided frequency Sdc2 (i.e., Sdc2_ bar), and outputs the inverted second divided frequency Sdc2 as the first output frequency Sc 1. Thus, the first output frequency Sc1 having the output phase P1_ (1, 1, 1, 1, 1, 1) (time point t5 relative to time point t1) can be generated. In other words, after the second clock Ssc2 is divided by the third divider 1026, the clock frequency of the second divided clock Sdc2 is 100MHz, and the phase of the second divided clock Sdc2 can have 32 different phases selected according to the values of the digital signals (b5, b4, b3, b2, b1, b 0). Similarly, since each input frequency can be inverted by the third inverter 1026 to generate 32 frequencies with another 32 different phases, the phase of the first output frequency Sc1 outputted by the third inverter 1026 can have 64 different phase selections. Please note that, the frequency of the first output frequency Sc1 with 64 different phases is also 100 MHz. From the above-described operation process, it can be seen that when a plurality of frequencies respectively having a plurality of different phases pass through a circuit composed of a frequency divider and an inverter, a double-multiple phase selection is generated. Therefore, those skilled in the art should understand that the present invention is not limited to the architecture using only two sets of frequency dividers and inverters (i.e. one set consisting of the first frequency divider 1023 and the second inverter 1024 included in the dashed line 1022a, and the other set consisting of the second frequency divider 1025 and the third inverter 1026 included in the dashed line 1022 b), and that the phase generating apparatus 100 can generate any multiple of the specific number of output phases according to the specific number of phases after being modified appropriately.

In addition, the reference phase generating circuit 108 includes a third phase selector 1082, a fifth frequency divider 1084 and a sixth frequency divider 1086. The third phase selector 1082 selects an input frequency from the input frequencies Sin as a reference frequency Sref. The fifth frequency divider 1084 is coupled to the third phase selector 1082, and is used for performing a frequency dividing operation on the reference frequency Sref to generate a fifth frequency dividing frequency Sdc 5. The sixth frequency divider 1086 is coupled to the fifth frequency divider 1084, and is used for performing a frequency dividing operation on the fifth frequency dividing frequency Sdc5 to generate a sixth frequency dividing frequency Sdc 6. Please note that, in the present embodiment, the fifth frequency divider 1084 and the sixth frequency divider 1086 respectively perform a division operation on the reference frequency Sref and the fifth frequency divider Sdc 5. For convenience, the third phase generator 1082 of the present embodiment selects the first input frequency Sin1 from the input frequencies Sin as the reference frequency Sref, but the invention is not limited thereto.

Please refer to fig. 3, fig. 5 and fig. 6. When the phase generating apparatus 100 receives the input frequencies Sin, since the first input frequency Sin1 is the frequency of the first input frequency Sin inputted to the phase generating apparatus 100, the phase of the first input frequency Sin1 (i.e., the time point t1) is used as the reference point of the phase of the first frequency Ssc1 by the third phase selector 1082. In other words, taking the digital signals (b5, b4, b3, b2, b1, b0) as (0, 0, 0, 0, 0) for example, the first corresponding phase Ps1_ (0, 0, 0, 0, 0, 0) of the first frequency Ssc1 is synchronized with the phase of the reference frequency Sref (i.e., time t 1). Taking the digital signals (b5, b4, b3, b2, b1, b0) as (1, 1, 1, 1, 1), the first corresponding phase Ps1_ (1, 1, 1, 1, 1, 1) of the first specific input frequency Ssc1 (i.e., time t3) has the largest phase difference with the phase of the reference frequency Sref. Then, the fifth frequency divider 1084 divides the reference frequency Sref by two to generate a fifth frequency Sdc5, and the first frequency divider 1023 and the second inverter 1024 generate a second frequency Ssc2 according to the first frequency Ssc 1. Since a divided-frequency output phase of a divided-frequency output frequency generated by a frequency divider may not be synchronized with the input phase of the input frequency (e.g., by 180 °) after an input frequency having an input phase is divided by the frequency divider, in order to make the first divided-frequency Sdc1 generated by the first frequency divider 1023 have a uniform reference phase, the first frequency divider 1023 generates the second frequency Ssc2 according to the phase of the fifth divided-frequency Sdc5 generated by the fifth frequency divider 1084 as a reference point (e.g., time point t1), so that the phase difference between the reference frequency Sref and the first frequency Ssc1 is substantially equal to the phase difference between the fifth divided-frequency Sdc5 and the second frequency Ssc 2. Similarly, in order to make the second frequency-dividing frequency Sdc2 generated by the second frequency divider 1025 have a uniform reference phase, the second frequency divider 1025 generates the first output frequency Sc1 according to the phase of the sixth frequency-dividing frequency Sdc6 generated by the sixth frequency divider 1086 as a reference point (e.g., time t1), so that the phase difference between the fifth frequency-dividing frequency Sdc5 and the second frequency Ssc2 is substantially equal to the phase difference between the sixth frequency-dividing frequency Sdc6 and the first output frequency Sc 1.

On the other hand, the second frequency generating device 104 of the phase generating device 100 of the present embodiment also receives the input frequencies Sin and generates the second output frequency Sc2 having the second output phase according to the digital signals (c5, c4, c3, c2, c1, c0) and the input frequencies Sin. Please note that, since the operation manner of the second frequency generating device 104 is substantially similar to that of the first frequency generating device 102, further description is omitted. However, for the sake of more clearly describing the spirit of the present invention, the present embodiment takes the digital signals (b5, b4, b3, b2, b1, b0) ═ 0, 0, 0, 0, 0, and (c5, c4, c3, c2, c1, c0) ═ 0, 0, 0, 0, 1, 0 as an example to illustrate the operation of the selection circuit 106. Please refer to fig. 7. FIG. 7 is a timing diagram illustrating the first output clock Sc1, the second output clock Sc2, the output signal Sn5, the selection signal Sup, the control signal Se, and the output clock Sout of the selection circuit 106 of the phase generator 100. When the output frequency Sout currently output by the phase generating device 100 corresponds to (c5, c4, c3, c2, c1, c0) being (0, 0, 0, 0, 1, 0) (i.e. generated by the second frequency generating device 104), and the output frequency Sout to be output next corresponds to (b5, b4, b3, b2, b1, b0) being (0, 0, 0, 0) (i.e. generated by the first frequency generating device 102), the selection signal Sup is first switched from the low voltage level to the high voltage level at the time point te. Then, the first output frequency Sc1 corresponding to (b5, b4, b3, b2, b1, b0) — (0, 0, 0, 0, 0) is input to the multiplexer 1062 and the and gate 1064a at the time point tf. Then, the first output frequency Sc1 and the second output frequency Sc2 are at the high voltage level at the time point tg, so that the output signal Sn5 is also switched from the low voltage level to the high voltage level at the time point tg, and at this time, the control signal Se of the register 1064b is also switched from the low voltage level to the high voltage level. Therefore, at the time tg, the output of the multiplexer 1062 is switched from the second output frequency Sc2 corresponding to (c5, c4, c3, c2, c1, c0) ═ 0, 0, 0, 0, 1, 0 to the first output frequency Sc1 corresponding to (b5, b4, b3, b2, b1, b0) ═ 0, 0, 0, 0. Then, at the time th, the output signal Sn5 is switched from the high voltage level to the low voltage level to maintain the control signal Se of the register 1064b at the high voltage level. In this way, after the time tg, the output frequency Sout of the phase generating apparatus 100 can be switched from the second output frequency Sc2 to the first output frequency Sc 1. It should be noted that, between time te and tg, the voltage level at the output terminal N6 of the multiplexer 1062 remains unchanged, i.e., remains at the high voltage level, and does not switch from a high voltage level to a low voltage level or from a low voltage level to a high voltage level, so that the voltage level at the output terminal N6 does not actually change. In other words, when the output frequency Sout of the phase generating apparatus 100 is switched from the second output frequency Sc2 to the first output frequency Sc1 at the time tg, the Glitch (Glitch) phenomenon at the output terminal N6 of the phase generating apparatus 100 can be greatly improved.

It should be noted that, as can be appreciated by those skilled in the art, the phase generating device 100 of the present invention is not limited to generating the output frequency Sout by the first and second frequency generating devices 102 and 104 and the selecting circuit 106. The phase generating apparatus 100 may also generate a plurality of output frequencies Sout by a plurality of sets of first and second frequency generating apparatuses 102, 104 and a selecting circuit 106 through suitable modification. In addition, the phase generating apparatus 100 of the present invention is not limited to the Two-to-one (Two-to-one) multiplexer 1062 combined with the first and second frequency generating devices 102 and 104 to generate the output frequency Sout, and the phase generating apparatus 100 may also be combined with a plurality of frequency generating devices (e.g. three frequency generating devices) to generate the output frequency Sout with one to one (e.g. three to one) multiplexers through suitable modification. On the other hand, although the first phase generator 1021 of the phase generating apparatus 100 is illustrated as generating 16 phases in a Full cycle (Full cycle) with 8 phases in a Half cycle (Half cycle), it should be understood that the invention is not limited thereto. The phase generating apparatus 100 of the present invention can also directly generate the output frequency Sout with the input frequencies Sin having 16 phases in the full cycle, as shown in fig. 8.

Fig. 8 is a schematic diagram of another embodiment of a phase generating device 800 according to the present invention. In the embodiment of fig. 8, the phase generating device 800 includes a first and a second frequency generating device 802, 804, a selecting circuit 806 and a reference phase generating circuit 808. The first clock generation apparatus 802 generates a first output clock Sc1 ' having a first output phase according to the input clocks Sin ' and a first digital signal Sd1 ' (i.e., (d4, d3, d2, d1, d 0)). The second clock generator 804 generates a second output clock Sc2 ' having a second output phase according to the input clocks Sin ' and a second digital signal Sd2 ' (i.e. (e4, e3, e2, e1, e 0)). The selection circuit 806 is coupled to the first and second frequency generating devices 802, 804, and is used for selecting one of the first and second output frequencies Sc1 ', Sc 2' generated by the first and second frequency generating devices 802, 804, respectively, as the output frequency Sout 'according to a selection signal Sup'. The reference phase generating circuit 808 is used to provide at least one reference phase to the first and second frequency generating devices 802, 804 as a reference phase for the first output phase and the second output phase. In addition, the first frequency generating device 802 includes a first phase selector 8021 and a first phase generating unit 820. The first phase selector 8021 is used for selecting a selected input clock Ssc1 ' having a corresponding phase from the input clocks Sin ' according to the first digital signal Sd1 '. The first phase generating unit 820 comprises a first frequency divider 8022 and a first inverter 8023. The first frequency divider 8022 is coupled to the first phase selector 8021, and is configured to perform a frequency dividing operation on the selected input frequency Ssc1 'to generate a first frequency division frequency Sdc 1'. The first inverter 8023 is coupled to the first divider 8022, and is configured to selectively invert the first frequency-dividing frequency Sdc1 'according to a bit (i.e., d4) of the first digital signal Sd 1', so as to generate the first output frequency Sc1 'having the first output phase P1'. Similarly, the second frequency generating device 804 also includes a second phase selector 8041 and a second phase generating unit. The second phase generating unit includes a second frequency divider 8042 and a second inverter 8043. In addition, the reference phase generating circuit 808 comprises: a third phase selector 8082 for selecting an input frequency from the input frequencies Sin 'as a reference frequency Sref'; and a third frequency divider 8084, coupled to the third phase generator 8082, for performing a frequency dividing operation on the reference frequency Sref 'to generate a third frequency dividing frequency Sdc 3'; the first frequency divider 8022 and the second frequency divider 8042 generate the first frequency dividing frequency Sdc1 ' and the second frequency dividing frequency Sdc2 ' respectively by using the phase of the third frequency dividing frequency Sdc3 ' as a reference phase. The selection circuit 806 is used to switch the second output frequency Sc2 ' currently used as the output frequency Sout ' to the first output frequency Sc1 ' according to the selection signal Sup ' to be used as the output frequency Sout ' to be outputted next.

Furthermore, in the present embodiment, the input frequencies Sin 'have 16 frequencies with different phases under the condition of the full cycle, and therefore, the first, second and third phase selectors 8021, 8041 and 8082 of the phase generating apparatus 800 of the present embodiment select a phase from the 16 phases in the full cycle of the input frequencies Sin', so as to omit the corresponding first inverter 1022 and fourth inverter 1042 in the phase generating apparatus 100. Furthermore, for simplicity, the phase generating apparatus 800 generates an output frequency Sout 'having a corresponding phase according to five bits of digital signals (i.e. the first digital signal Sd 1' (d4, d3, d2, d1, d0) and the second digital signal Sd2 '(e 4, e3, e2, e1, e0)), wherein four bits (d3, d2, d1, d0) of the first digital signal Sd 1' are provided to the first phase selector 8021 to select an input frequency having a corresponding phase from the 16 input frequencies Sin, the bit d4 of the first digital signal Sd1 'is provided to the first frequency divider 8022, and four bits (e3, e2, e 2) of the second digital signal Sd 7' are provided to the second phase selector 41 to select a second input frequency 2, a corresponding to the input frequency 16 ', the second frequency divider 2'. Referring to the technical content taught with respect to the phase generating device 100, since the digital signal of the phase generating device 800 has 5 bits, the output frequency Sout ' generated by the phase generating device 800 can have a selection of 32 different phases, and the frequency of the output frequency Sout ' is 100MHz (the frequency of the input frequencies Sin ' is 200 MHz). Please note that, since the operation of the phase generator 800 is similar to that of the phase generator 100, the detailed operation thereof is not repeated herein.

In summary, the embodiments disclosed herein generate a phase conversion device by way of Digital (Digital) circuit. As described above, since the phase conversion device is implemented by a digital circuit, the conventional current driving (current driving) circuit can be avoided, and thus the phase generation device 100, 800 of the present invention can greatly reduce the power consumption of the circuit during operation. On the other hand, through the selection circuit 106 and the related method disclosed by the present invention, the phase generating apparatus 100, 800 can further improve the Glitch (Glitch) phenomenon generated during the operation of the circuit.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims (11)

1. A phase generating apparatus for generating an output frequency having a desired phase according to a digital signal, the phase generating apparatus comprising:

a phase selection unit for selecting one of a plurality of input frequencies to generate a reference frequency according to a portion of bits of the digital signal, wherein the input frequencies have different phases; and

a phase generating unit for dividing the reference frequency and selectively delaying the divided reference frequency according to another part of bits of the digital signal to generate the output frequency;

wherein, this phase place produces the unit and includes:

a frequency divider for dividing the reference frequency; and

a delay unit for selectively delaying the divided reference frequency according to the other part of bits in the digital signal to generate the output frequency, wherein the delay unit is composed of an inverter.

2. The phase generating apparatus of claim 1, wherein the phase selection unit comprises:

a phase selector for selecting one of the input frequencies according to a portion of the portion of bits of the digital signal; and

a delay unit for selectively delaying the selected input frequency according to another part of the part of bits in the digital signal to generate the reference frequency.

3. The phase generating apparatus of claim 1, wherein the phase selection unit comprises a phase selector for selecting one of the input frequencies as the reference frequency according to the portion of the bits of the digital signal.

4. The phase generating apparatus as claimed in claim 3, further comprising:

a reference phase selector for selecting one of the input frequencies as a reference frequency; and

one frequency divider to divide the reference frequency to generate one divided reference frequency;

the frequency divider generates the divided reference frequency based on the phase of the divided reference frequency.

5. The phase generating device of claim 1, further for generating another output frequency having a desired phase according to another digital signal, the phase generating device further comprising:

another phase selection unit for selecting one of the input frequencies according to a portion of bits of the another digital signal to generate another reference frequency;

another phase generating unit for dividing the frequency of the another reference frequency and selectively delaying the divided another reference frequency according to another part of bits of the digital signal to generate the another output frequency; and

a selection circuit for selecting one of the output frequency and the other output frequency according to a selection signal.

6. The phase generating apparatus of claim 5, wherein the selection circuit comprises:

a control signal generating circuit for generating a control signal according to the output frequency, the other output frequency and the selection signal; and

a multiplexer for receiving the output frequency and the other output frequency and selecting one of the output frequency and the other output frequency according to the control signal.

7. A phase generating method for generating an output frequency having a desired phase according to a digital signal, the phase generating method comprising:

(a) providing a plurality of input frequencies, and selecting one of the input frequencies according to a part of bits of the digital signal to generate a reference frequency, wherein the input frequencies have different phases;

(b) dividing the reference frequency to generate a divided reference frequency: and

(c) selectively delaying the divided reference frequency according to another part of bits of the digital signal to generate the output frequency; wherein,

in step (c), an inverter is used to delay the divided reference frequency.

8. The phase generating method of claim 7, wherein the step (a) comprises:

selecting one of the input frequencies based on a portion of the portion of bits of the digital signal; and

selectively delaying the selected input frequency according to another part of the part of bits in the digital signal to generate the reference frequency.

9. The method of claim 7, wherein one of the input frequencies is selected as the reference frequency in step (a) based on the portion of the bits of the digital signal.

10. The phase generation method of claim 7, further comprising:

selecting one of the input frequencies as a reference frequency; and

performing frequency division processing on the reference frequency to generate a divided reference frequency;

wherein the step (b) generates the divided reference frequency based on the phase of the divided reference frequency.

11. The method of claim 7, further comprising generating another output frequency having a desired phase according to another digital signal, the method further comprising:

selecting one of the input frequencies according to a part of bits of the other digital signal to generate another reference frequency;

dividing the other reference frequency, and selectively delaying the divided other reference frequency according to another part of bits of the digital signal to generate the other output frequency; and

selecting one of the output frequency and the other output frequency according to a selection signal.

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