CN102096746B - The layout design method of analog to digital converter high-low coupling capacitor and specific capacitance - Google Patents
The layout design method of analog to digital converter high-low coupling capacitor and specific capacitance Download PDFInfo
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Abstract
The invention discloses the layout design method of a kind of analog to digital converter high-low coupling capacitor and specific capacitance, comprise the following steps: S1, on domain, first design the coupling capacitance (C1) of definite shape as reference capacitance; S2, by multiple for uniform for the reference capacitance of step S1 virtual dividing virtual dividing block, each virtual dividing block is block electric capacity (C3); S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity (C3) that coupling capacitance (C1) numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance (C2).The layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, be suitable for gradual approaching A/D converter, its advantage is: simplicity of design, layout area that is convenient, that take chip layout is little.
Description
Technical field
The present invention relates to IC layout design field, relate to the layout design method of a kind of gradual approaching A/D converter high-low coupling capacitor and specific capacitance concretely.
Background technology
The high-low-position of gradual approaching A/D converter is connected by coupling capacitance.For the gradual approaching A/D converter of a N position, suppose that its high-order electric capacity is M position, bit capacitor is L position.Also be N=M+L, then the coupling capacitance in the middle of is [2
l/ (2
l-1)] C, wherein C is unit capacitance, and namely coupling capacitance is always greater than specific capacitance.Such as 10 gradual approaching A/D converters, are connected by capacitive coupling between high 5 and low 5.The coupling capacitance C10 of 10 gradual approaching A/D converter high-low-positions is the specific capacitance C20 of 32/31.The value of its coupling capacitance C10 is the fractional value of specific capacitance C20, and non-integer.The realization method of layout of coupling capacitance C10 and specific capacitance C20 has two kinds: as shown in Figure 1, the first, for benchmark with specific capacitance C20, a little limit electric capacity C30 is drawn again afterwards at the periphery of specific capacitance C20, employing afterwards trims technique opposite side electric capacity C30 and revises, to reach the fractional value of coupling capacitance C10.The shortcoming of this kind of layout design method is: performing step is complicated, and coupling capacitance C10 is not specification body, makes coupling capacitance C10 be difficult to layout in capacitor array domain.As shown in Figure 2, the second adopts multiple electric capacity C40 connection in series-parallel composition; The shortcoming of this kind of coupling capacitance manufacture method is: the area not only taking chip layout is large, and there is stray capacitance C50 between series-parallel electric capacity C40 and ground, makes the fractional value of coupling capacitance not reach requirement, thus makes the conversion accuracy step-down of analog to digital converter.
Summary of the invention
Technical matters to be solved by this invention is, overcomes above deficiency, provides the layout design method of the little analog to digital converter high-low coupling capacitor of a kind of simplicity of design, layout area that is convenient, that take chip layout and specific capacitance.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: the layout design method of a kind of analog to digital converter high-low coupling capacitor and specific capacitance, comprises the following steps:
S1, computing formula C1=[2 according to analog to digital converter high-low coupling capacitor and specific capacitance
l/ (2
l-1)] C2, wherein L is the figure place of bit capacitor, domain is first designed the coupling capacitance of square or rectangular shape as reference capacitance;
S2, by the reference capacitance of step S1 according to described computing formula C1=[2
l/ (2
l-1)] the uniform virtual dividing of the multiple of the numerator value of C2 is multiple virtual dividing blocks, and each virtual dividing block is block electric capacity;
S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity that coupling capacitance numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance.
Further, the shape of the coupling capacitance of step S1 is square, and the shape of the reference capacitance virtual dividing of step S2 is N
2individual equal-sized virtual dividing block, the shape of described virtual dividing block is square, wherein N be greater than 3 integer.
Further, the shape of the coupling capacitance of step S1 is square, and the shape of the reference capacitance virtual dividing of step S2 is B × D equal-sized virtual dividing block, and the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer.
Further, the shape of the coupling capacitance of step S1 is rectangle, and the shape of the reference capacitance virtual dividing of step S2 is N
2individual equal-sized square, wherein N be greater than 3 integer.
Further, the shape of the coupling capacitance of step S1 is rectangle, and the shape of the reference capacitance virtual dividing of step S2 is B × D equal-sized virtual dividing block, and the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer.
The invention has the beneficial effects as follows: because coupling capacitance is the fractional value being greater than specific capacitance, domain is first designed the coupling capacitance of square shape; Again the order of coupling capacitance according to step S2, step S3 is cut, obtain specific capacitance.Its basic thought is, gets coupling capacitance as reference capacitance.Reference capacitance is carried out virtual dividing, cuts away reference capacitance corner, obtain specific capacitance.Its specific design method has four kinds.
The first, S1, first design the coupling capacitance of square shape as reference capacitance on domain; S2, be N by uniform for the reference capacitance of step S1 virtual dividing
2individual equal-sized square, wherein N be greater than 3 integer, each square virtual dividing block is block electric capacity; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity that coupling capacitance numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance.
The second, S1, first designs the coupling capacitance of square shape as reference capacitance on domain; S2, be B × D equal-sized rectangle by uniform for the reference capacitance of step S1 virtual dividing, wherein B be greater than 2 integer, D be greater than 3 integer, each rectangle virtual dividing block is block electric capacity; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity that coupling capacitance numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance.
The third, S1, first design the coupling capacitance of rectangular shape as reference capacitance on domain; S2, be N by uniform for the reference capacitance of step S1 virtual dividing
2individual equal-sized square, wherein N be greater than 3 integer, each square virtual dividing block is block electric capacity; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity that coupling capacitance numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance.
4th kind, S1, on domain, first design the coupling capacitance of rectangular shape as reference capacitance; S2, be B × D equal-sized rectangle by uniform for the reference capacitance of step S1 virtual dividing, wherein B be greater than 2 integer, D be greater than 3 integer, each rectangle virtual dividing block is block electric capacity; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity that coupling capacitance numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance.
The layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, do not need employing to trim technique and revise coupling capacitance or specific capacitance, therefore, layout design of the present invention is simple.Because specific capacitance cuts on the basis of reference capacitance, its overall specification is similar to reference capacitance, therefore, coupling capacitance and specific capacitance can be evenly distributed on chip layout, namely facilitate coupling capacitance and the layout of specific capacitance on chip layout.Meanwhile, because coupling capacitance is independent parts in domain, can not produce when adopting series-parallel system to manufacture coupling capacitance, after multiple electric capacity connection in series-parallel, the problem that area occupied is large in chip layout.The i.e. layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, coupling capacitance area occupied in chip layout is little.
Accompanying drawing explanation
Fig. 1 is the process schematic of the layout design method of the first coupling capacitance of prior art and specific capacitance;
Fig. 2 is the schematic diagram of the layout design method of prior art the second coupling capacitance and specific capacitance;
Fig. 3 a-3f is the first process schematic to the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance;
Fig. 4 a-4f is the first process schematic to the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance;
Fig. 5 a-5f is the first process schematic to the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance;
Fig. 6 a-6f is the first process schematic to the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail:
The layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, comprises the following steps:
S1, computing formula C1=[2 according to analog to digital converter high-low coupling capacitor C1 and specific capacitance C2
l/ (2
l-1)] C2, wherein L is the figure place of bit capacitor, domain is first designed the coupling capacitance C1 of square or rectangular shape as reference capacitance;
S2, by the reference capacitance of step S1 according to described computing formula C1=[2
l/ (2
l-1)] the uniform virtual dividing of the multiple of the numerator value of C2 is multiple virtual dividing blocks, and each virtual dividing block is block electric capacity C3;
S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
Embodiment 1:
As illustrated in figs. 3 a-f, S1, on domain, first design the coupling capacitance C1 of square shape as reference capacitance; S2, be N by uniform for the reference capacitance of step S1 virtual dividing
2individual equal-sized virtual dividing block, the shape of described virtual dividing block is square, wherein N be greater than 3 integer, each square virtual dividing block is block electric capacity C3; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
Fig. 3 a is the process schematic of the first cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely the block electric capacity C3 at coupling capacitance C1 diagonal angle is cut away.
Fig. 3 b is the process schematic of the second cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of adjacent two corners of coupling capacitance C1 is cut away.
Fig. 3 c is the process schematic of the third cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of coupling capacitance C1 tetra-corners is cut away.
Fig. 3 d is the process schematic of the 4th kind of cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely cut away the half of coupling capacitance C1 diagonal blocks electric capacity C3, the shape cutting away part is right-angle triangle.
Fig. 3 e is the process schematic of the 5th kind of cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of adjacent two corners of coupling capacitance C1, the shape cutting away part is right-angle triangle.
Fig. 3 f is the process schematic of the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 1 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of coupling capacitance C1 tetra-corners, the shape cutting away part is right-angle triangle.
Such as: design 10 gradual approaching A/D converter high-low coupling capacitor C1 and specific capacitance C2, its coupling capacitance C1=32/31C2, wherein C2 is the specific capacitance of high-low-position sample circuit.Capacitance due to coupling capacitance C1 is greater than the capacitance of specific capacitance C2, therefore using coupling capacitance C1 as reference capacitance.In the present embodiment 1, first manufacture foursquare coupling capacitance C1 as reference capacitance, again coupling capacitance C1 is carried out uniform virtual dividing according to the multiple of numerator value 32, the shape of virtual dividing is square, and the numerator value of coupling capacitance C1 is expanded 2 times carries out virtual dividing.Namely coupling capacitance C1 is become the square block electric capacity of 8 × 8=64 by virtual dividing, then coupling capacitance C1=32/31C2=64/62C2, cuts away two block electric capacity of the symmetrical corner of coupling capacitance C1, obtains the specific capacitance C2 of 62 pieces.
Embodiment 2:
As shown in Fig. 4 a-4f, S1, on domain, first design the coupling capacitance C1 of square shape as reference capacitance; S2, be B × D equal-sized virtual dividing block by uniform for the reference capacitance of step S1 virtual dividing, the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer, each rectangle virtual dividing block is block electric capacity C3; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
Fig. 4 a is the process schematic of the first cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely the block electric capacity C3 at coupling capacitance C1 diagonal angle is cut away.
Fig. 4 b is the process schematic of the second cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of adjacent two corners of coupling capacitance C1 is cut away.
Fig. 4 c is the process schematic of the third cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of coupling capacitance C1 tetra-corners is cut away.
Fig. 4 d is the process schematic of the 4th kind of cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely cut away the half of coupling capacitance C1 diagonal blocks electric capacity C3, the shape cutting away part is right-angle triangle.
Fig. 4 e is the process schematic of the 5th kind of cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of adjacent two corners of coupling capacitance C1, the shape cutting away part is right-angle triangle.
Fig. 4 f is the process schematic of the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 2 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of coupling capacitance C1 tetra-corners, the shape cutting away part is right-angle triangle.
Embodiment 3:
As shown in Figure 5, S1, on domain, first design the coupling capacitance C1 of rectangular shape as reference capacitance; S2, be N by uniform for the reference capacitance of step S1 virtual dividing
2individual equal-sized virtual dividing block, the shape of described virtual dividing block is square, wherein N be greater than 3 integer, each square virtual dividing block is block electric capacity C3; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
Fig. 5 a is the process schematic of the first cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely the block electric capacity C3 at coupling capacitance C1 diagonal angle is cut away.
Fig. 5 b is the process schematic of the second cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of adjacent two corners of coupling capacitance C1 is cut away.
Fig. 5 c is the process schematic of the third cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of coupling capacitance C1 tetra-corners is cut away.
Fig. 5 d is the process schematic of the 4th kind of cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely cut away the half of coupling capacitance C1 diagonal blocks electric capacity C3, the shape cutting away part is right-angle triangle.
Fig. 5 e is the process schematic of the 5th kind of cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of adjacent two corners of coupling capacitance C1, the shape cutting away part is right-angle triangle.
Fig. 5 f is the process schematic of the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 3 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of coupling capacitance C1 tetra-corners, the shape cutting away part is right-angle triangle.
Embodiment 4:
As shown in Figure 6, S1, on domain, first design the coupling capacitance C1 of rectangular shape as reference capacitance; S2, be B × D equal-sized virtual dividing block by uniform for the reference capacitance of step S1 virtual dividing, the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer, each rectangle virtual dividing block is block electric capacity C3; S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
Fig. 6 a is the process schematic of the first cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely the block electric capacity C3 at coupling capacitance C1 diagonal angle is cut away.
Fig. 6 b is the process schematic of the second cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of adjacent two corners of coupling capacitance C1 is cut away.
Fig. 6 c is the process schematic of the third cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely the block electric capacity C3 of coupling capacitance C1 tetra-corners is cut away.
Fig. 6 d is the process schematic of the 4th kind of cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely cut away the half of coupling capacitance C1 diagonal blocks electric capacity C3, the shape cutting away part is right-angle triangle.
Fig. 6 e is the process schematic of the 5th kind of cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of adjacent two corners of coupling capacitance C1, the shape cutting away part is right-angle triangle.
Fig. 6 f is the process schematic of the 6th kind of cutting mode of the method for designing of the embodiment of the present invention 4 coupling capacitance and specific capacitance; Namely cut away the half of the block electric capacity C3 of coupling capacitance C1 tetra-corners, the shape cutting away part is right-angle triangle.
The layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, do not need employing to trim technique and revise coupling capacitance C1 or specific capacitance, therefore, layout design of the present invention is simple.Because specific capacitance C2 cuts on the basis of reference capacitance, its overall specification is similar to reference capacitance, therefore, coupling capacitance and specific capacitance C2 can be evenly distributed on chip layout, namely facilitate coupling capacitance C1 and the layout of specific capacitance C1 on chip layout.Meanwhile, because coupling capacitance C1 is independent parts in domain, can not produce when adopting series-parallel system to manufacture coupling capacitance C1, after multiple electric capacity connection in series-parallel, the problem that area occupied is large in chip layout.The i.e. layout design method of analog to digital converter high-low coupling capacitor of the present invention and specific capacitance, coupling capacitance C1 area occupied in chip layout is little.
Adopt the method for traditional layout design method coupling capacitance and specific capacitance, the scope of its differential nonlinearity error DNL is-0.6<DNL<0.02, and the scope of integral non-linear error INL is-0.5<INL<0.5; Adopt layout design method of the present invention, the scope of its differential nonlinearity error DNL is-0.02<DNL<0.02, and the scope of integral non-linear error INL is-0.02<INL<0.
Claims (5)
1. a layout design method for analog to digital converter high-low coupling capacitor and specific capacitance, is characterized in that: comprise the following steps:
S1, computing formula C1=[2 according to analog to digital converter high-low coupling capacitor C1 and specific capacitance C2
l/ (2
l-1)] C2, wherein L is the figure place of bit capacitor, domain is first designed the coupling capacitance C1 of square or rectangular shape as reference capacitance;
S2, by the reference capacitance of step S1 according to described computing formula C1=[2
l/ (2
l-1)] the numerator value 2 of C2
lthe uniform virtual dividing of multiple be multiple virtual dividing blocks, each virtual dividing block is block electric capacity C3;
S3, adopt mode that is symmetrical or dispersion, in step s 2 reference capacitance corner, cut away the block electric capacity C3 that coupling capacitance C1 numerator value deducts the multiple of the quantity of denominator value, obtain specific capacitance C2.
2. the layout design method of analog to digital converter high-low coupling capacitor according to claim 1 and specific capacitance, is characterized in that: the shape of the coupling capacitance C1 of step S1 is square, and the reference capacitance virtual dividing of step S2 is N
2individual equal-sized virtual dividing block, the shape of described virtual dividing block is square, wherein N be greater than 3 integer.
3. the layout design method of analog to digital converter high-low coupling capacitor according to claim 1 and specific capacitance, it is characterized in that: the shape of the coupling capacitance C1 of step S1 is square, the reference capacitance virtual dividing of step S2 is B × D equal-sized virtual dividing block, the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer.
4. the layout design method of analog to digital converter high-low coupling capacitor according to claim 1 and specific capacitance, is characterized in that: the shape of the coupling capacitance C1 of step S1 is rectangle, and the reference capacitance virtual dividing of step S2 is N
2individual equal-sized virtual dividing block, the shape of described virtual dividing block is square, wherein N be greater than 3 integer.
5. the layout design method of analog to digital converter high-low coupling capacitor according to claim 1 and specific capacitance, it is characterized in that: the shape of the coupling capacitance C1 of step S1 is rectangle, the reference capacitance virtual dividing of step S2 is B × D equal-sized virtual dividing block, the shape of described virtual dividing block is rectangle, wherein B be greater than 2 integer, D be greater than 3 integer.
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| CN103023504B (en) * | 2012-12-18 | 2015-09-16 | 中国科学院微电子研究所 | Successive approximation type ADC layout structure |
| CN105808791A (en) * | 2014-12-29 | 2016-07-27 | 北京华大九天软件有限公司 | An acceleration method for resistance calculation mesh division |
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN107612549B (en) * | 2017-09-05 | 2020-08-18 | 成都易源芯辰微电子科技有限公司 | Twisted-pair type shared central capacitor array and layout design method thereof |
| CN114937557B (en) * | 2022-05-26 | 2024-06-11 | 北京奕斯伟计算技术股份有限公司 | Capacitor array module |
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| CN1108791A (en) * | 1993-09-20 | 1995-09-20 | 株式会社鹰山 | Capacitance forming method |
| US5889486A (en) * | 1997-09-18 | 1999-03-30 | National Semiconductor Corporation | Split capacitor array for digital-to-analog signal conversion |
| CN101800551A (en) * | 2010-04-02 | 2010-08-11 | 中国科学院苏州纳米技术与纳米仿生研究所 | Gradually-appoximant analog-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1108791A (en) * | 1993-09-20 | 1995-09-20 | 株式会社鹰山 | Capacitance forming method |
| US5889486A (en) * | 1997-09-18 | 1999-03-30 | National Semiconductor Corporation | Split capacitor array for digital-to-analog signal conversion |
| CN101800551A (en) * | 2010-04-02 | 2010-08-11 | 中国科学院苏州纳米技术与纳米仿生研究所 | Gradually-appoximant analog-digital converter |
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