CN102082542A - VME (Versa Module Eurocard)-bus-based vector control system of three-phase asynchronous motor - Google Patents
VME (Versa Module Eurocard)-bus-based vector control system of three-phase asynchronous motor Download PDFInfo
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- CN102082542A CN102082542A CN2011100330192A CN201110033019A CN102082542A CN 102082542 A CN102082542 A CN 102082542A CN 2011100330192 A CN2011100330192 A CN 2011100330192A CN 201110033019 A CN201110033019 A CN 201110033019A CN 102082542 A CN102082542 A CN 102082542A
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Abstract
The invention discloses a VME (Versa Module Eurocard)-bus-based vector control system of a three-phase asynchronous motor, belonging to the field of control systems of alternating current motors. In the system, a three-level rectifying and three-level voltage inverting type circuit is adopted for a main circuit, and PowerPC+DSP (Power Personal Computer+Digital Signal Processor) digital control structures are respectively adopted for a rectifying link and a inverting link, wherein the PowerPC is used for realizing rectifying and inverting algorithms, the DSP is used for realizing pulse output triggered by a fully-controlled-type power switching device, and the PowerPC and the DSP are communicated through a VME bus. With respect to a hardware system, algorithms with excellent performances, such as an asynchronous motor vector control method, an on-line identification and ant colony optimization and the like, are adopted so as to greatly improve the system performance on speed regulation. The system has great realistic significance to saving energy sources and improving economic benefits. In the system, rectified direct-current voltage is stable, input current and voltage phases on the alternating current side are basically identical, and input power factor is close to 1. By means of the invention, a speed regulation system has the advantages of high response speed, small overshoot, high steady-state precision and strong robustness on revolving speed, as well as small current and voltage harmonic, low pulse torque and stable magnetic flux linkage.
Description
Technical field
The invention belongs to AC Motor Control system field, the threephase asynchronous vector control platform of a kind of PowerPC+DSP based on the VME bus particularly is provided, highly versatile has antijamming capability; Host CPU is finished basic control function, and finishes the collection and the processing of signal; Auxilliary CPU finishes Electric Machine Control, exports 12 road pwm pulses, satisfies the demand of three level rectifyings and inversion.Utilize the VME bus to realize information exchange between the main and auxiliary CPU, core bus is international industrial standard VME bus, and system has certain opening, with user friendly expansion.
Background technology
Modern AC Adjusting Speed Technology is one of major progress of 20 th century later human societies, its development speed is fast, what use coverage rate extensively is unprecedented, it makes this ancient electromechanical energy device of motor obtain new development and uses widely, greatly improve the production efficiency of industrial or agricultural, improved people's quality of life.
For a long time, owing to the scientific technological advance level is limited, compare with alternating current motor in view of DC motor to have superior speed adjusting performance, so high performance governing system generally adopts DC motor.But, there are devices such as mechanical commutator and brush on this body structure of DC motor, this has brought a series of restriction for the capacity and the application scenario of Direct Current Governor System.After the sixties in 20th century, because the requirement of the needs of production development and saving electric energy impels countries in the world to pay attention to the research and development of ac speed control technology.Especially since the vector control technology development seventies in 20th century, made Alternating Current Governor System can compare favourably with Direct Current Governor System on dynamic and static performance, the control thought of vector control has established theoretical foundation for high performance ac speed control technology.But, being subject to the development of power electronic device, the PWM inverter just occurred at that time, and GTR and GTO still are in initial stage of development, and the inverter that vector control system adopts constitutes by thyristor.Not only volume is big for this inverter, quality heavy, and can't adapt to rapid acceleration and load impact, has limited the range of application of vector controller greatly.
Along with the function of the continuous appearance of the development of power electronic device, new-type circuit converter and microprocessor is powerful day by day, make ac speed control technology forward high frequencyization, digitlization and intelligentized direction develop, nearly all new control theory, control method can attempt on AC speed regulator and use, and this makes vector control technology be able to its outstanding control performance of performance in the speed governing field.But constantly the improving of control theory also is accompanied by control algolithm to become increasingly complex, and this is just more and more higher to the disposal ability requirement of computer.Fully used in industry in order to make control algolithm some complexity, useful, improve the disposal ability and the operational efficiency of industrial computer, use the processor active task that the aiding CPU system shares the part host CPU, form the parallel processor system parallel processing, thereby improving the real-time and the reliability of system, will be a feasible approach.
Simultaneously, advanced control system is mainly used in the processing complex process, and what follow is the complicated of control algolithm, and then the hardware of system is had higher requirement, particularly the occasion of having relatively high expectations in real-time more needs system's assurance of powerful data-handling capacity.The threephase asynchronous vector control system that the present invention is designed adopts two CPU to participate in computing, and one is used for identification and optimal controller parameter, and another piece is made vector control CPU.
By research, the design based on the parallel multiprocessing system of VME bus mode communication has been proposed between the processor to parallel processing technique and multiprocessing system design principle scheduling theory.The design of system mainly comprises the hardware and the logical design of aid in treatment system.
In sum, control for the threephase asynchronous vector control system that requires wide speed regulating range, high steady speed precision, fast dynamic response and four quadrant running, require designed control system should have opening, extensibility, reliability, more adjustable parameter, bigger use adaptability, not too complex installation and maintenance, should not be subjected to simultaneously the influence of abominable factor such as complex industrial process environment, operating mode, can guarantee under complex environment, to finish the threephase asynchronous vector control.
Summary of the invention
The object of the present invention is to provide a kind of threephase asynchronous vector control system, improve motor vector control precision.It is good that it has a systemic openness, the reliability height, fault-tolerant ability is strong, and antijamming capability is strong, install simple, adaptability is strong, can normal and continuous operation under the complex environment of load variations, and cooperate DSP in the superiority of sending out aspect the pwm pulse simultaneously, introduce the motor vector control method and the advanced control theory of comparative maturity, designed DSP as aiding CPU, PowerPC has guaranteed the stability and the real-time of system's operation as the numerical control system of host CPU.
Threephase asynchronous vector control system provided by the invention adopts Power PC+DSP parallel processing structure, and system design is divided into host processing system and DSP aid in treatment system two parts.Host processing system adopts the general hardware platform, and what choose is the PowerPC8245 single board computer of motorola inc, and host processing system mainly is to carry out the software design exploitation; The complete autonomous Design of DSP auxiliary processor system, the core dsp chip adopts TMS320F2812; Make up the parallel processor framework by the VME bus between the major-minor processor.
Primary processor has standard VME bus, has energy operate as normal under the VME framework of standard, and is supporting multiprocessor.Primary processor PowerPC8245 has low in energy consumption simultaneously, and speed is fast, and can directly detain the IO daughter board on mainboard, finishes the input and output of analog quantity, digital quantity.The DSP auxiliary processor is realized the parallel co-ordination of major-minor processor by the VME interface on the processor.Finish the collection and the processing of signals such as current of electric, voltage, rotating speed, torque by primary processor PowerPC, finish vector control algorithm then, draw the sector number, zonule number at three level SVPWM reference vector places, three basic vectors time span etc. separately, again these data are sent to auxiliary processor DSP, auxiliary processor is by regularly tabling look-up, can draw and respectively export the impulse level signal, send by the auxiliary processor task manager again, finish Motor Control, export 12 road pwm pulses, satisfy the demand of three level rectifyings and inversion.
Hardware designs of the present invention mainly is the design of DSP aiding CPU plate, comprises the fpga logic design, DSP peripheral expansion circuit design, power module design, VME interface circuit design and IGBT design of drive circuit.Communication between the major-minor CPU is to be undertaken by the VME bus, and the aiding CPU intralamellar part adopts XC3S400 to realize VME slave interface, and generates DPRAM in inside, carries out exchanges data with dsp chip, has increased the flexibility and the reliability of system.This system has the bus expansion of 8K * 32 simultaneously, is convenient to expand external interface.
The DSP that uses in the said system is TMS320F2812, and TMS320F2812 is a chip that is primarily aimed at motor and motion control and Power Electronic Circuit of the up-to-date development of American TI Company.It has high cost performance, command system and operating characteristics flexibly, and operational capability and improved parallel organization at a high speed, and meet the JTAG standard testing interface of the standard of IEEE 1149.Especially its CZBxTM kernel CPU, highest frequency can reach 150 MHz, and the ancillary equipment that the most suitable motor and motion control are used is embedded into wherein, comprises two event manager modules (EVA and EVB), 12 A/D converters of 16 passages (ADC).Wherein event manager module can produce the output of PWM, and has a quadrature coding pulse (QEP) circuit.They are respectively applied for switch control of obtaining power device and the position and the velocity information of catching electric rotating machine.
TMS320F2812 adopts improved Harvard structure, and the one, allow procedure stores in high-speed cache (Cache), improve the reading speed of instruction; The 2nd, allow storage in program storage, and directly used by arithmetic instruction, strengthen the flexibility of chip; In addition, the dual port RAM among the DSP (SARAM) comprises a random port and a sequential port, and independently reads and writes bus and improved data access speed.DSP extensively adopts pipelining (Pipeline), has strengthened the disposal ability of processor, and the degree of depth of F2812 streamline can reach 8 grades, that is to say, but in 8 instructions of an instruction cycle parallel processing;
Its maximum is supported 96 external interrupt simultaneously.
Above-mentioned VME bus adopts the electrical layer of VME standard and the definition of logical layer, and the arrangement of drawing pin has taken into full account the integration and the power supply supply of holding wire.Only use the P1 connector, support 16 position datawires, the double altitudes plate of 24 bit address lines.Asynchronous control mode is all adopted in all transmission of VME bus, and address and data are all with non-multiplexed parallel mode transmission.Excellent Interrupt Process mechanism has real-time response ability at a high speed, and is highly reliable, the anti-vibration impact capacity.
Fpga chip in the above-mentioned auxilliary processor is the XC3S400 of Xilinx company, and this chip cooperates with DSP, constitutes the control core of whole auxilliary cpu system.DSP directly and between the FPGA carries out transfer of data by the addressing of I/O mouth.When system moved, the TMS320F2812 processor chips read the AC asynchronous motor feedback signal that FPGA gathers, and rotating speed of motor and position signalling are carried out relevant control algolithm computing, and produced the PWM drive signal by the SPWM algorithm.Drive signal sends to the drive end of power model after light-coupled isolation, produce three-phase inversion voltage, realizes the control to ac three-phase asynchronous motor.
An embodiment adopts the parallel organization of major-minor processor that threephase asynchronous is realized rectification, inversion algorithm, finally motor is carried out vector control.Be buckled in I/O daughter card on the host CPU and finish input and output analog quantity, digital quantity, host CPU is finished the collection and the processing of data simultaneously, and finish optimization to the parameter of electric machine by on-line identification and ant group optimization scheduling algorithm, finish vector control algorithm, draw the required data of three level SVPWM reference vectors.Again these data are exported to DSP, DSP draws by computing and respectively exports the impulse level signal, and is sent by task manager, realizes the vector control to threephase asynchronous.
The major-minor processor structure that relates among the present invention can be selected according to concrete application scenario, and a complete numerical control system can constitute with two PowerPC and two DSP.Hardware system is mixed well behaved Vector Control for Asynchronous Motor method and on-line identification and ant group optimization scheduling algorithm, can be so that system's speed adjusting performance improves greatly.
Description of drawings
Fig. 1 is the numerical control system block diagram according to example of the present invention.
Fig. 2 is the auxiliary processor system block diagram according to example of the present invention.
Fig. 3 is FPGA (XC3S400) the part connecting circuit figure according to example of the present invention.
Fig. 4 is the part interface circuit figure of the DSP (TMS320F2812) according to example of the present invention.
Fig. 5 is the VME bus configuration interface circuit figure according to example of the present invention.
Fig. 6 is the VME bus isolation circuit figure according to example of the present invention.
Fig. 7 is the flow chart according to the control system of example of the present invention.
The number of pins of the equal presentation graphs chips of Arabic numerals among Fig. 3, Fig. 4, Fig. 5, Fig. 6 wherein, in relevant integrated circuit textbook, the pin of chip is arranged in sequence, the number of pins of different chips is all since 1, therefore identical Arabic numerals can appear in same figure, just because of the existence of number of pins, can the with the aid of pictures and use of more convenient relevant technical staff.All have operation instructions for concrete chip when buying, number of pins wherein is consistent with the label in the accompanying drawing.
Embodiment
A specific embodiment of the present invention adopts the parallel organization of major-minor processor that threephase asynchronous is carried out vector control.Wherein, it mainly finishes the collection and the processing of data primary processor, and vector control algorithm, draws the related parameter that has of three level SVPWM M reference vectors, again these data is sent to auxilliary processor; Auxilliary processor can draw and respectively export the impulse level signal by regularly tabling look-up, and is sent by the DSP task manager again, finishes a vector control circulation.The major-minor processor structure that relates among the present invention can be selected according to concrete application scenario, and whole numerical control system can constitute with two PowerPC and two DSP, finishes rectification and inversion respectively.Two cover even more major-minor processor systems overlap processor system more and all can be installed to simultaneously in the same set of VME framework.
Fig. 1 has described the numerical control system block diagram according to example of the present invention.Wherein the PowerPC on the left side and DSP mainly finish the control of rectification link, and the PowerPC on the right and DSP mainly finish the control of inversion link.PowerPC finishes the collection and the processing of data, basic function control and vector control algorithm, and DSP exports 12 tunnel pulses, realizes the vector control to threephase asynchronous.
Fig. 2 has described the auxiliary processor system block diagram according to example of the present invention.System module mainly comprises with the lower part: power module, dsp chip interface module, FPGA connecting circuit module, IGBT isolation drive module, bus isolation drive module and interface module.
The FPGA circuit part interface that Fig. 3 has described according to example of the present invention connects and external circuits figure.The FPGA internal structure is made of logic gate array, and each gate array parallel processing I/O signal has more advantage than controller (MCU) on the speed of service during operation, can gather signals such as electric current, voltage, rotating speed simultaneously.Fpga chip adopts the XC3S400 of Xilinx company among the design, and this chip cooperates with DSP, constitutes the control core of auxilliary processor.Dsp chip directly and between the FPGA carries out transfer of data by the addressing of I/O mouth, reads the various feedback signals of asynchronous machine.DSP is connected with the IO of FPGA, realizes that the inner DPRAM of generation of FPGA is connected with DSP, and this partial circuit major function is that the FPGA internal storage is mapped to the DSP address space, thereby realizes the direct high-speed data exchange of DSP to FPGA.In addition DSP external interrupt signal and timer signal are inserted FPGA, can realize neatly that FPGA communicates by letter with the control of DSP.
Fig. 4 has described the dsp chip connecting circuit figure according to example of the present invention.F2812 has 176 pins, wherein many with pin GPIO (General Purpose Input/ Output pin) 56, each pin all has two kinds of functions to be provided with: the one, as general digital I/O mouth (Digital I/O), the one, as peripheral functionality pin (Peripheral Function), such as PWM, eCAN, SCI, sPI etc.45 of external interrupt pin XINTF (External Interrupt), power supply (comprises the digital-to-analog power supply, voltage has the branch of 1.9V and 3.3V) and pin (digital-to-analog ground) 38, ground, 23 of the pins relevant, 7 of the pins relevant with jtag interface with analog/digital converter ADC.
Fig. 5 has described the VME bus configuration interface circuit figure according to example of the present invention.Auxilliary CPU observes the VME bus specification, only uses the P1 connector, supports 16 position datawires, the double altitudes plate of 24 bit address lines.Asynchronous control mode is all adopted in all transmission of VME bus, and address and data are all with non-multiplexed parallel mode transmission.Excellent Interrupt Process mechanism has real-time response ability at a high speed, and is highly reliable, the anti-vibration impact capacity.
Fig. 6 has described the VME bus isolation circuit figure according to example of the present invention.XC3S400 IO voltage is 3.3V, and the VME bus adopts the 5V level, so the buffer circuit design is necessary.All VME address data signals adopt SN74ALV16245 to isolate, and have increased the driving force of bus greatly, satisfy the requirement of VME standard to the drive current size.Voltage transitions adopts QS3861Q, and this chip maximum delay is 25PS, therefore satisfies the requirement to sequential fully.
Fig. 7 has described the flow chart according to the control system in the specific embodiment of the present invention.Primary processor PowerPC finishes current of electric, voltage, rotating speed, the collection of signals such as torque and processing, carrying out magnetic linkage calculates, finish vector control algorithm then, draw the sector number at three level SVPWM reference vector places, zonule number, three basic vectors are time span etc. separately, again these data are sent to auxiliary processor DSP, auxiliary processor is by regularly tabling look-up, can draw and respectively export the impulse level signal, send by the auxiliary processor task manager again, export 12 road pwm pulses, satisfy the demand of three level rectifyings and inversion, finish Motor Control; Thereby finish a vector control circulation.
Claims (5)
1. threephase asynchronous vector control system based on the VME bus is characterized in that: comprise the veneer PowerPC device of framework based on the VME bus, VME bus, based on the data acquisition daughter board of PMC bus, the DSP pulse outputting unit of VME bus; The data acquisition daughter board is connected with sensor device, and the DSP pulse outputting unit links to each other with the main circuit power switch pipe;
Adopt VME standard card cage device, ensure the high speed information reliable delivery between many CPU;
Adopt the PMC bus of powerpc board inside to link to each other, improve real time data acquisition with the data acquisition daughter board;
Adopt the data acquisition daughter board assemblies, the analog voltage signal that each transducer sniffer is exported is converted to digital signal;
Adopt the dsp board device, output impulse level signal, the demand of satisfied three level rectifyings and inversion is finished Motor Control.
2. according to the described threephase asynchronous vector control system of claim 1 based on the VME bus, it is characterized in that: adopt two cover PowerPC+DSP equipment, one cover is used for rectification, one cover is used for inversion, each covering device all is made of major-minor CPU, host CPU is that PowerPC finishes basic control function, and finishes the collection and the processing of signal; Auxilliary CPU is that DSP realizes full control type device for power switching trigger impulse output, realizes three phase rectifier and three-phase inversion
,Finish Motor Control, satisfy the demand of three level rectifyings and inversion; Host CPU mainly adopts the veneer CPU based on the VME bus of outsourcing, and intralamellar part has the PMC interface, and auxilliary CPU is the DSP aiding CPU plate of independent development, comprise the fpga logic circuit design, DSP peripheral expansion circuit design, power module design, VME interface circuit design and IGBT design of drive circuit; Communication between the major-minor CPU is undertaken by the VME bus, and the aiding CPU intralamellar part adopts FPGA to realize VME slave interface, and generates DPRAM in inside, carries out the exchange of data with dsp chip, has increased the flexibility and the reliability of system; This system has the bus expansion of 8K * 32 simultaneously, is convenient to expand external interface.
3. according to the described threephase asynchronous vector control system of claim 1 based on the VME bus, it is characterized in that: information exchange is by the VME bus between the major-minor CPU, the various information that auxilliary CPU handles directly sends host CPU to by the VME bus, does not influence the visit of host CPU to other CPU board or I/O in the framework like this.
4. according to the described threephase asynchronous vector control system based on the VME bus of claim 1, it is characterized in that: the signals collecting daughter board is buckled on the host CPU plate by PMC, improves real time data acquisition; The analog-signal transitions that signal pickup assembly is used for detecting is that digital signal is input to signal processing apparatus and handles; Signal processing device is changed to host CPU, and signal is finished vector control algorithm, obtains the sector number, zonule number at three level SVPWM reference vector places, three basic vectors time span separately; Send these data-signals to DSP, finish the motor vector control.
5. according to the described threephase asynchronous vector control system of claim 1 based on the VME bus, it is characterized in that: host CPU is finished current of electric, voltage, rotating speed, the collection of dtc signal and processing, finish vector control algorithm then, obtain the sector number at three level SVPWM reference vector places, zonule number, three basic vectors are time span separately, again these data are sent to auxilliary CPU plate DSP, DSP is by regularly tabling look-up, draw and respectively export the impulse level signal, send by the DSP task manager again, finish Motor Control, export 12 road pwm pulses, satisfy the demand of three level rectifyings and inversion.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112865639A (en) * | 2021-02-23 | 2021-05-28 | 浙江大学 | Electric automobile permanent magnet synchronous motor control system with road condition reproduction function |
| CN113075895A (en) * | 2021-03-26 | 2021-07-06 | 江苏城乡建设职业学院 | High-speed centrifuge interrupt program instruction distribution method |
| CN115442178A (en) * | 2022-08-31 | 2022-12-06 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
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2011
- 2011-01-30 CN CN2011100330192A patent/CN102082542A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112865639A (en) * | 2021-02-23 | 2021-05-28 | 浙江大学 | Electric automobile permanent magnet synchronous motor control system with road condition reproduction function |
| CN112865639B (en) * | 2021-02-23 | 2022-06-21 | 浙江大学 | Electric automobile permanent magnet synchronous motor control system with road condition reproduction function |
| CN113075895A (en) * | 2021-03-26 | 2021-07-06 | 江苏城乡建设职业学院 | High-speed centrifuge interrupt program instruction distribution method |
| CN115442178A (en) * | 2022-08-31 | 2022-12-06 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
| CN115442178B (en) * | 2022-08-31 | 2023-12-15 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
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Application publication date: 20110601 |