CN102074574A - Method for forming stack gate of CMOS (Complementary Metal-Oxide-Semiconductor) device and stack gate sturcture - Google Patents
Method for forming stack gate of CMOS (Complementary Metal-Oxide-Semiconductor) device and stack gate sturcture Download PDFInfo
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- CN102074574A CN102074574A CN2009102378004A CN200910237800A CN102074574A CN 102074574 A CN102074574 A CN 102074574A CN 2009102378004 A CN2009102378004 A CN 2009102378004A CN 200910237800 A CN200910237800 A CN 200910237800A CN 102074574 A CN102074574 A CN 102074574A
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Abstract
The invention provides a gate medium structure of an MOS ( Metal-Oxide-Semiconductor) device, which comprises a boundary layer film formed on the surface of a semiconductor substrate and at least two layers of insulating films formed on the surface of the boundary layer film, wherein each of the at least two layers of insulating films has element components and concentrations, which are different from that of other adjacent insulating films, the boundary layer film and the at least two layers of insulating films are processed by an optimized annealing process, and the optimized annealing process is related to the element components and the concentrations of the boundary layer film and the at least two layers of insulating films so as to realize ideal distribution of the element components and the concentrations. In the invention, the gate medium structure of the MOS device is formed by depositing multiple layers of different material components or different concentrations of films in a certain order, and then, the ideal distribution of all element components and the concentrations in the gate medium structure is realized by the optimized annealing process.
Description
Technical field
The present invention relates to a kind of semiconductor device formation method and structure, particularly a kind of formation method and structure thereof of cmos device laminated gate medium.
Background technology
In the microelectric technique development in decades, logic chip manufacturer adopts SiO always when making the MOS device
2As gate medium, adopt heavily doped polysilicon as gate material.But, along with constantly dwindling of characteristic size, the SiO in the MOS transistor
2Gate dielectric has closed on the limit.For example, in 65 nanometer technologies, SiO
2The thickness of grid has been reduced to 1.2 nanometers, is about 5 silicon atom layer thickness, if continue to dwindle, leakage current and power consumption will sharply increase again.What simultaneously, the doped with boron atom diffusion that is caused by polygate electrodes, depletion of polysilicon effect and too high problems such as gate resistance also will become is more and more serious.For 32 nanometers and following each technology generation, sharply problems such as leakage current that increases and power consumption with anxious treat new material, new technology, and the exploitation of new device structure solve.
For reducing leakage current and power consumption, it is to adopt " high k/ metal gate " structure that a kind of improvement technology is arranged.At present, each the main semiconductor company in the international coverage has all taken up towards the exploitation of " high k/ metal gate " technology of 32 nanometers and following technology generation.Intel discloses out after adopting high-k gate dielectric material, and it is original 1/10th that the leakage current of device is reduced to, and still, also brought the threshold voltage control problem of MOS device simultaneously.Because the MOS arts demand possesses nMOS and pMOS device simultaneously, therefore be optimized device performance to greatest extent, the threshold voltage that just requires nMOS and pMOS device also will reduce the numerical value of threshold voltage as much as possible under maintenance absolute value prerequisite about equally.Therefore, how reducing threshold voltage is problem demanding prompt solution.
At present, for reducing device threshold voltage, utilizing suitable material to regulate effective work function is the most direct, feasible and effective method.Discover, some elements are after mixing high k film or metal gate film, can play the effect that makes the flat band voltage skew, regulates threshold voltage, for example rare earth element and Al, Mg etc. such as La, Yb, Dy, and the distributing position of these elements on whole gate medium vertical direction can influence the regulating power of threshold voltage.Also have some elements after mixing high k film, can play the effect that improves film heat stability, for example N, Si etc.In addition, have some elements can form the electric charge or the defective of some at this place near the MOS device channel time, this can produce very big scattering to channel carrier, and then causes carrier mobility to reduce, and causes device performance degeneration, for example N, Al, La etc.
Therefore, in high-k gate dielectric/metal gate technique of new generation, need introduce the element that some need, thereby improve the performance of device in desirable position.
Summary of the invention
For overcoming the defective that exists in the above-mentioned prior art, particularly MOS device stack gate dielectric structure that proposes by the present invention and forming method thereof improves the performance of MOS device.
To achieve these goals, the present invention proposes a kind of gate dielectric structure of metal-oxide semiconductor (MOS) MOS device, comprising: the boundary layer film that on semiconductor substrate surface, forms; With the two-layer at least insulation film that on described boundary layer film surface, forms, every layer of insulation film comprises at least two kinds of elements, wherein, in the described two-layer at least insulation film each all has different elemental constituent of adjacent insulation film with other and/or different concentration, and described boundary layer film and the annealing process of described two-layer at least insulation film through optimizing, the annealing process of described optimization is relevant with the elemental constituent and/or the concentration of described boundary layer film and described two-layer at least insulation film, with the described element that reaches hope and/or the distribution of concentration.
According to a further aspect in the invention, the invention allows for a kind of cmos device, comprise above-mentioned gate dielectric structure.
In accordance with a further aspect of the present invention, the invention allows for a kind of method that forms the gate dielectric structure of above-mentioned MOS device, comprise the steps: on semiconductor substrate surface, to form the boundary layer film; On described boundary layer film surface, form two-layer at least insulation film, every layer of insulation film comprises at least two kinds of elements, wherein, each in the described two-layer at least insulation film all has different elemental constituent of adjacent insulation film with other and/or different concentration; The annealing process that described boundary layer film and described two-layer at least insulation film is optimized according to the elemental constituent of described boundary layer film and described two-layer at least insulation film and/or concentration is with the described element that reaches hope and/or the distribution of concentration.
The present invention forms the laminated gate medium structure of MOS device by the film according to certain sequential deposit multiple layers of different materials component or variable concentrations, reaches desirable distribution by the annealing process of optimizing to impel various elemental constituents and concentration in this laminated gate medium structure then.By control to the distribution of various elemental constituents in the laminated gate medium structure and concentration, can control EOT (equivalent oxide thickness), adjusting threshold voltage, the raising channel mobility of MOS device, and reduce grid leakage current etc., thereby can promote MOS device overall performance comprehensively.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the gate dielectric structure schematic diagram of the MOS device of embodiment of the invention proposition;
Fig. 2-5 is the schematic diagram of the formation rhythmic structure of the fence of the present invention of the embodiment of the invention one;
Fig. 6-11 is the schematic diagram of the formation rhythmic structure of the fence of the present invention of the embodiment of the invention two;
Figure 12-15 is the schematic diagram of the formation rhythmic structure of the fence of the present invention of the embodiment of the invention three;
Figure 16-18 is the schematic diagram of the formation rhythmic structure of the fence of the present invention of the embodiment of the invention four.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
The laminated gate medium structure of the MOS device that the present invention proposes is by forming according to multilayer (2-5 layer) the different materials component of certain sequential deposit or the film of variable concentrations, and the annealing process that cooperates the optimization of the present invention's proposition, this annealing process of optimizing is relevant with the material component and/or the concentration of above-mentioned material layer, with the element that obtains wishing and/or the distribution of concentration, thereby the EOT of control MOS device, adjusting threshold voltage, raising channel mobility, and reduce grid leakage current etc., with comprehensive lifting MOS device overall performance.
But need to prove, present invention focuses on to propose a kind of gate dielectric structure, this gate dielectric structure has a plurality of films, and each film all has to be adjacent the different material component of film or to have the identical materials component and but has different concentration, to reach the distribution of hope.The performance of the MOS device of Ti Shenging as required, each film may have different materials, different thickness or different concentration, this performance that needs to improve as required determines, following examples of the present invention will be introduced some embodiment that improve the MOS device performance, these embodiment make those skilled in the art clearer understanding be arranged to the present invention, are not that the present invention can only realize by following examples.
In addition, can improve the performance of MOS device among the present invention in several ways, these modes can realize separately, also can make up realization.For example, in order to improve the dielectric constant of high K medium layer, can add the La element in dielectric layer, in addition, the distribution in the high K medium layer is controlled to the La element, also can reduce the scattering of La element to channel carrier, thereby improves the mobility of channel carrier.Perhaps, doped with Al unit usually regulates flat band voltage, thereby reaches the purpose of control threshold voltage, simultaneously, controls the Al element by the present invention and can too much not be diffused into SiO
2Or near the raceway groove, and then reduce of the influence of Al element to the channel carrier mobility, or the like.As seen it is a variety of to realize that mode of the present invention has; following embodiment realizes preferred implementation of the present invention; those skilled in the art also can thought according to the present invention make modification, the conversion of a lot of equivalences or substitute, and these all should be included within protection scope of the present invention.
As shown in Figure 1, the gate dielectric structure schematic diagram of the MOS device that proposes for the embodiment of the invention, comprise and be formed on Semiconductor substrate 101 lip-deep boundary layer films 102, with the two-layer at least insulation film 104 (103-1 to 103-n) that on boundary layer film 102 surfaces, forms, wherein, at least each (103-1 to 103-n) in the two-layer insulation film 104 has different elemental constituent of adjacent insulation film with other and/or different concentration, and boundary layer film 102 and the annealing process of two-layer at least insulation film 104 through optimizing, the annealing process of this optimization is relevant with the elemental constituent and/or the concentration of boundary layer film 102 and two-layer at least insulation film 104, with the element that reaches hope and/or the distribution of concentration.
In one embodiment of the invention, boundary layer film 102 and insulation film 103-1 to 103-n can comprise: HfO
2, HfSiO
x, HfON, HfSiON, HfAlO
x, Al
2O
3, ZrO
2, ZrSiO
x, Ta
2O
5, La
2O
3, Y
2O
3, HfLaO
x, LaAlO
x, LaSiO
x, the nitride of above-mentioned material, the nitrogen oxide of above-mentioned material, other rare earth oxides, other rare earth element nitride, SiO
2, SiNx, SiON or above-mentioned material combination, perhaps other material and combinations thereof that are fit to.
The invention allows for a kind of cmos device that comprises above-mentioned gate dielectric structure, this cmos device constituted mode of other parts except that gate dielectric structure is same as the prior art, does not repeat them here.
Just as described above, components different among boundary layer film 102 and the insulation film 103-1 to 103-n are in order to improve a certain or a few performances of MOS device with different concentration, below just set forth in the mode of specific embodiment, these embodiment only are schematically, are not that the present invention only can realize by following examples.
Embodiment one,
Shown in Fig. 2-5, be the schematic diagram of the formation rhythmic structure of the fence of the present invention of the embodiment of the invention one, in this embodiment, multi-layer insulation film is the three-layer thin-film that thickness is identical, atomic percent is different, certainly insulation film also can be inequality in other embodiments, may further comprise the steps:
Step 1: as shown in Figure 2, growth interface layer film 102 on the silicon substrate 101 of carrying out the PROCESS FOR TREATMENT in early stage, its thickness is about 0.5nm, in embodiments of the present invention, boundary layer film 102 is SiO
2The boundary layer film.Boundary layer film 102 is with SiO in the present embodiment
2For example is described, can select above-described other materials in other embodiments as boundary layer film 102.
Step 2: as shown in Figure 3, at SiO
2With ALD technology growth ground floor insulation film 103-1, its thickness is about 1nm on the boundary layer film 102, and in embodiments of the present invention, ground floor insulation film 103-1 is Hf
0.8La
0.2The O film, wherein the La elements atomic percentage is 20%.
Step 3: as shown in Figure 4, at ground floor insulation film 103-1 (Hf
0.8La
0.2The O film) go up with ALD technology generation second layer insulation film 103-2, its thickness is about 1nm, and second layer insulation film 103-2 is Hf
0.5La
0.5The O film, wherein the La elements atomic percentage is 50%.
Step 4: as shown in Figure 5, at second layer insulation film 103-2 (Hf
0.5La
0.5The O film) go up with the three-layer insulated film 103-3 of ALD technology growth, its thickness is about 1nm, and three-layer insulated film 103-3 is Hf
0.2La
0.8The O film, wherein the La elements atomic percentage is 80%.
Step 5: this structure is carried out 500 ℃, the annealing in process of 30s.
This embodiment of the present invention can reach following special beneficial effect:
1, improved the dielectric constant (the La element helps to improve dielectric constant) of whole high K medium layer.
2, make the La element produce gradient in the distribution of whole high K medium layer, near the area L a concentration of element of silicon substrate less than away from silicon substrate area, effectively like this reduced the scattering of La to channel carrier, improved the mobility of channel carrier.
Embodiment two,
Shown in Fig. 6-11, the schematic diagram for the formation rhythmic structure of the fence of the present invention of the embodiment of the invention two may further comprise the steps:
Step 1: the thick boundary layer film 102 of growth 0.5nm on the silicon substrate 101 of carrying out the PROCESS FOR TREATMENT in early stage, as shown in Figure 6, boundary layer film 102 is SiO in this embodiment
2 Boundary layer film 102 is with SiO in the present embodiment
2For example is described, can select above-described other materials in other embodiments as boundary layer film 102.
Step 2: as shown in Figure 6, with ALD technology growth ground floor insulation film 103-1, its thickness is about 1nm on boundary layer film 102, and in this embodiment, ground floor insulation film 103-1 is HfO
2Film.
Step 3: as shown in Figure 7, with ALD technology growth second layer insulation film 103-2, its thickness is about 0.5nm on ground floor insulation film 103-1, and in this embodiment, second layer insulation film 103-2 is Al
2O
3Film.
Step 4: as shown in Figure 8, with the three-layer insulated film 103-3 of ALD technology growth, its thickness is about 0.5nm on second layer insulation film 103-2, and in this embodiment, three-layer insulated film 103-3 is HfO
2Film.
Step 5: in nitrogen atmosphere, the structure that forms by above-mentioned steps is carried out 500 ℃, the annealing in process first time of 30s.
Step 6: as shown in Figure 9, with the 4th layer of insulation film 103-4 of ALD technology growth, its thickness is about 1nm on three-layer insulated film 103-3, and in this embodiment, the 4th layer of insulation film 103-4 is Al
2O
3Film.
Step 7: as shown in figure 10, with ALD technology growth layer 5 insulation film 103-5, its thickness is about 0.5nm on the 4th layer of insulation film 103-4, and in this embodiment, layer 5 insulation film 103-5 is HfO
2Film.
Step 8: the structure that forms by above-mentioned steps is carried out 500 ℃, the annealing in process second time of 15s.
By this embodiment, can reach following special beneficial effect:
1, regulates flat band voltage by mixing of Al element, finally reach the purpose of regulating threshold voltage.
2, pass through Al
2O
3(purpose of the parameter setting of annealing process is to allow to contain the few film annealing temperature of Al element long slightly and the film after annealing time contained more than the Al element of grow is short slightly for the position of film and the setting of annealing process, so both reached the purpose of annealing process minimizing defective itself and interface charge, guaranteed the CONCENTRATION DISTRIBUTION of Al element in the high K medium layer again, as shown in figure 11), make the SiO that is diffused into that the Al element can be not too much
2Or near the raceway groove, and then reduced of the influence of Al element to the channel carrier mobility.
Embodiment three,
Shown in Figure 12-15, the schematic diagram for the formation rhythmic structure of the fence of the present invention of the embodiment of the invention three may further comprise the steps:
Step 1: as shown in figure 12, on the silicon substrate 101 of carrying out the PROCESS FOR TREATMENT in early stage, use the thick HfO of ALD technology growth one deck 0.3nm
2Film 102.
Step 2: in nitrogen atmosphere, this structure is taked 700 ℃, the annealing in process first time of 20s, to form HfSiO
x Boundary layer film 102, shown in Figure 13.
Step 3: as shown in figure 13, at HfSiO
xWith ALD technology growth ground floor insulation film 103-1, its thickness is about 0.5nm on the boundary layer film 102, and in this embodiment, ground floor insulation film 103-1 is the HfLaON film.
Step 4: as shown in figure 14, with ALD technology growth second layer insulation film 103-2, its thickness is about 2nm on ground floor insulation film 103-1, and in this embodiment, second layer insulation film 103-2 is La
2O
3Film.
Step 5: as shown in figure 15, with the three-layer insulated film 103-3 of ALD technology growth, its thickness is about 1nm on second layer insulation film 103-2, and in this embodiment, three-layer insulated film 103-3 is HfO
2Film.
Step 6: the structure that forms by above-mentioned steps is carried out 700 ℃, the annealing in process second time of 30s.
By this embodiment, can reach following special beneficial effect:
1, adopts HfSiO
xThe surface layer film substitutes SiO
2Film, thereby the EOT of reduction gate medium.
2, adopt the HfLaON film, introduced the N element and limited the diffusion of La element in annealing process, reduced the La Elements Diffusion, improved the mobility of channel carrier near the influence that the raceway groove channel carrier is produced scattering.
3, La
2O
3Film has effectively improved whole gate dielectric layer dielectric constant (La
2O
3Dielectric constant very high), reduced the EOT of gate medium.
4, HfO
2Film can prevent La
2O
3Problems such as the moisture absorption that the direct ingress of air of film brought, film go bad.
Embodiment four,
Shown in Figure 16-18, the schematic diagram for the formation rhythmic structure of the fence of the present invention of the embodiment of the invention four may further comprise the steps:
Step 1: as shown in figure 16, the thick SiO of growth 0.5nm on the silicon substrate 101 of carrying out the PROCESS FOR TREATMENT in early stage
2 Boundary layer film 102.
Step 2: at SiO
2With ALD technology growth ground floor insulation film 103-1, its thickness is about 1nm on the boundary layer film 102, and in this embodiment, ground floor insulation film 103-1 is HfO
2Film, as shown in figure 16.
Step 3: with ALD technology growth second layer insulation film 103-2, its thickness is about 1nm on ground floor insulation film 103-1, and in this embodiment, second layer insulation film 103-2 is SiN
xFilm, as shown in figure 16.
Step 4: as shown in figure 17, with the three-layer insulated film 103-3 of ALD technology growth, its thickness is about 1nm on second layer insulation film 103-2, and in this embodiment, three-layer insulated film 103-3 is the HfN film.
Step 5: in nitrogen atmosphere, the structure that above-mentioned steps is formed is carried out 900 ℃, the annealing in process first time of 30s, thereby forms HfSiON (103-2 and 103-3), as shown in figure 18.
Step 6: as shown in figure 18, the HfSiON that forms after annealing (103-2 and 103-3) goes up with the 4th layer of insulation film 103-4 of ALD technology growth, and its thickness is about 1nm, and in this embodiment, the 4th layer of insulation film 103-4 is HfO
2Film.
Step 7: the structure that above-mentioned steps is formed is carried out 700 ℃, the annealing in process second time of 30s.
By this embodiment, can reach following special beneficial effect:
1, in medium, adds the thin layer that contains Si and N element, effectively reduced the leakage current of whole gate dielectric layer, improved thermal stability.
2, the N element has been avoided the scattering of N element to channel carrier at the thin layer away from raceway groove.
3, HfO
2Film has improved the dielectric constant of whole gate dielectric layer, makes the EOT of whole gate medium effectively reduce.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (33)
1. the gate dielectric structure of a metal-oxide semiconductor (MOS) MOS device is characterized in that, comprising:
The boundary layer film that on semiconductor substrate surface, forms; With
The two-layer at least insulation film that on described boundary layer film surface, forms, every layer of insulation film comprises at least two kinds of elements, wherein, in the described two-layer at least insulation film each all has different elemental constituent of adjacent insulation film with other and/or different concentration, and described boundary layer film and the annealing process of described two-layer at least insulation film through optimizing, the annealing process of described optimization is relevant with the elemental constituent and/or the concentration of described boundary layer film and described two-layer at least insulation film, with the described element that reaches hope and/or the distribution of concentration.
2. the gate dielectric structure of MOS device as claimed in claim 1 is characterized in that, described boundary layer film comprises: HfO
2, HfSiO
x, HfON, HfSiON, HfAlO
x, Al
2O
3, ZrO
2, ZrSiO
x, Ta
2O
5, La
2O
3, Y
2O
3, HfLaO
x, LaAlO
x, LaSiO
x, the nitride of above-mentioned material, the nitrogen oxide of above-mentioned material, other rare earth oxides, other rare earth element nitride, SiO
2, SiNx, SiON or above-mentioned material combination.
3. the gate dielectric structure of MOS device as claimed in claim 1 is characterized in that, described insulation film comprises: HfO
2, HfSiO
x, HfON, HfSiON, HfAlO
x, Al
2O
3, ZrO
2, ZrSiO
x, Ta
2O
5, La
2O
3, Y
2O
3, HfLaO
x, LaAlO
x, LaSiO
x, the nitride of above-mentioned material, the nitrogen oxide of above-mentioned material, other rare earth oxides, other rare earth element nitride, SiO
2, SiNx, SiON or above-mentioned material combination.
4. the gate dielectric structure of MOS device as claimed in claim 1 is characterized in that, any thin film in the described two-layer at least insulation film contains the element different with other adjacent films, or contains identical element but elemental constituent is inequality.
5. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, has at least one deck to comprise the Al element in the described insulation film.
6. the gate dielectric structure of MOS device as claimed in claim 5 is characterized in that, also has one deck to comprise Hf element or La element in the described insulation film at least.
7. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, has at least one deck to comprise the Hf element in the described insulation film.
8. the gate dielectric structure of MOS device as claimed in claim 7 is characterized in that, also has one deck to comprise the La element in the described insulation film at least.
9. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, has at least one deck to comprise the Si element in the described insulation film.
10. as the gate dielectric structure of each described MOS device of claim 5-9, it is characterized in that, have at least in the described insulation film one deck contain O element or 14, as the described insulation film of claim 6-12, it is characterized in that having at least one deck to contain the N element in the described insulation film.
11. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, comprises one deck Al in the described insulation film at least
2O
3Film.
12. the gate dielectric structure of MOS device as claimed in claim 11 is characterized in that, at least also comprises one deck HfO in the described insulation film
2Film.
13. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, has at least one deck to comprise the LaAlO film in the described insulation film.
14. the gate dielectric structure of MOS device as claimed in claim 5 is characterized in that, has at least one deck to comprise the HfLaON film in the described insulation film.
15. the gate dielectric structure of MOS device as claimed in claim 14 is characterized in that, also comprises one deck La in the described insulation film
2O
3Film or HfO
2Film.
16. the gate dielectric structure of MOS device as claimed in claim 4 is characterized in that, comprises the HfSiON film in the described insulation film.
17. a cmos device is characterized in that, comprises each described gate dielectric structure of claim 1-16.
18. a method that forms the gate dielectric structure of MOS device is characterized in that, comprises the steps:
On semiconductor substrate surface, form the boundary layer film;
On described boundary layer film surface, form two-layer at least insulation film, every layer of insulation film comprises at least two kinds of elements, wherein, each in the described two-layer at least insulation film all has different elemental constituent of adjacent insulation film with other and/or different concentration;
The annealing process that described boundary layer film and described two-layer at least insulation film is optimized according to the elemental constituent of described boundary layer film and described two-layer at least insulation film and/or concentration is with the described element that reaches hope and/or the distribution of concentration.
19. the method for the gate dielectric structure of formation MOS device as claimed in claim 18 is characterized in that described boundary layer film comprises: HfO
2, HfSiO
x, HfON, HfSiON, HfAlO
x, Al
2O
3, ZrO
2, ZrSiO
x, Ta
2O
5, La
2O
3, Y
2O
3, HfLaO
x, LaAlO
x, LaSiO
x, the nitride of above-mentioned material, the nitrogen oxide of above-mentioned material, other rare earth oxides, other rare earth element nitride, SiO
2, SiNx, SiON or above-mentioned material combination.
20. the method for the gate dielectric structure of formation MOS device as claimed in claim 18 is characterized in that described insulation film comprises: HfO
2, HfSiO
x, HfON, HfSiON, HfAlO
x, Al
2O
3, ZrO
2, ZrSiO
x, Ta
2O
5, La
2O
3, Y
2O
3, HfLaO
x, LaAlO
x, LaSiO
x, the nitride of above-mentioned material, the nitrogen oxide of above-mentioned material, other rare earth oxides, other rare earth element nitride, SiO
2, SiNx, SiON or above-mentioned material combination.
21. the method for the gate dielectric structure of formation MOS device as claimed in claim 18, it is characterized in that, any thin film in the described two-layer at least insulation film contains the element different with other adjacent films, or contains identical element but elemental constituent is inequality.
22. the gate dielectric structure of MOS device as claimed in claim 21 is characterized in that, has at least one deck to comprise the Al element in the described insulation film.
23. the method for the gate dielectric structure of formation MOS device as claimed in claim 22 is characterized in that, also has one deck to comprise Hf element or La element in the described insulation film at least.
24. the method for the gate dielectric structure of formation MOS device as claimed in claim 21 is characterized in that having at least one deck to comprise the Hf element in the described insulation film.
25. the method for the gate dielectric structure of formation MOS device as claimed in claim 24 is characterized in that, also has one deck to comprise the La element in the described insulation film at least.
26. the method for the gate dielectric structure of formation MOS device as claimed in claim 21 is characterized in that having at least one deck to comprise the Si element in the described insulation film.
27., it is characterized in that having at least one deck to contain O element or N element in the described insulation film as each described method that forms the gate dielectric structure of MOS device of claim 22-26.
28. the method for the gate dielectric structure of formation MOS device as claimed in claim 21 is characterized in that, comprises one deck Al in the described insulation film at least
2O
3Film.
29. the method for the gate dielectric structure of formation MOS device as claimed in claim 28 is characterized in that, at least also comprises one deck HfO in the described insulation film
2Film.
30. the method for the gate dielectric structure of formation MOS device as claimed in claim 21 is characterized in that having at least one deck to comprise the LaAlO film in the described insulation film.
31. the method for the gate dielectric structure of formation MOS device as claimed in claim 22 is characterized in that having at least one deck to comprise the HfLaON film in the described insulation film.
32. the method for the gate dielectric structure of formation MOS device as claimed in claim 31 is characterized in that, also comprises one deck La in the described insulation film
2O
3Film or HfO
2Film.
33. the method for the gate dielectric structure of formation MOS device as claimed in claim 21 is characterized in that, comprises the HfSiON film in the described insulation film.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102378004A CN102074574A (en) | 2009-11-19 | 2009-11-19 | Method for forming stack gate of CMOS (Complementary Metal-Oxide-Semiconductor) device and stack gate sturcture |
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|---|---|---|---|
| CN2009102378004A CN102074574A (en) | 2009-11-19 | 2009-11-19 | Method for forming stack gate of CMOS (Complementary Metal-Oxide-Semiconductor) device and stack gate sturcture |
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|---|---|
| CN102074574A true CN102074574A (en) | 2011-05-25 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010884A (en) * | 2016-11-01 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109545846A (en) * | 2017-09-22 | 2019-03-29 | 三星电子株式会社 | Semiconductor devices |
| CN111498793A (en) * | 2020-05-01 | 2020-08-07 | 深迪半导体(上海)有限公司 | MEMS device and processing method thereof |
-
2009
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108010884A (en) * | 2016-11-01 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108010884B (en) * | 2016-11-01 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109545846A (en) * | 2017-09-22 | 2019-03-29 | 三星电子株式会社 | Semiconductor devices |
| CN109545846B (en) * | 2017-09-22 | 2023-10-03 | 三星电子株式会社 | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers |
| CN111498793A (en) * | 2020-05-01 | 2020-08-07 | 深迪半导体(上海)有限公司 | MEMS device and processing method thereof |
| CN111498793B (en) * | 2020-05-01 | 2023-10-27 | 深迪半导体(绍兴)有限公司 | MEMS device and processing method thereof |
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