CN102064797B - Parallel implementation method and device for fractional sampling rate transformation - Google Patents
Parallel implementation method and device for fractional sampling rate transformation Download PDFInfo
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Abstract
The invention discloses a parallel implementation method for fractional sampling rate transformation, which comprises the following steps of: 1, recording a data sequence x(n) to be transformed as x(0), x(1), ..., x(D-1) by taking D paths as a group and inputting the sequence into D filtering channels with channel markers according to frequency fi/D, wherein each filtering channel comprises I subchannels; 2, for each group of data, acquiring I*D paths of data to be operated from the D filtering channels; and 3, extracting I paths of data at fixed positions from the I*D paths of data to be operated according to a first preset rule for executing convolution operation, and acquiring I paths of output data of y(0), y(1), ..., y(I-1) with the frequency of fo/I respectively, wherein fo/fi=I/D refers to the multiple of fractional sampling rate transformation, and I and D are prime numbers. The method can reduce the operating rate of the polyphase filtering-based fractional sampling rate transformation to fi or fo or below and can be applied to multi-channel parallel transmission in a broadband communication system, and serial data is only needed to be subjected to serial/parallel transformation and then is processed.
Description
Technical field
The present invention relates to digital signal transmission technique field, relate in particular to a kind of Parallel Implementation method and device thereof of the fraction time sampling rate conversion based on multiphase filtering.
Background technology
In all-digital receiver during to analog signal sampling, a lot of situation down-sampling rates are not the integral multiple of character rate, and the module General Requirements such as Timing Synchronization of demodulator input data transfer rate is the integral multiple of symbol rate, this need to divide the several times conversion to sample rate, makes sample rate become the integral multiple of character rate.The basic operation of fraction time sampling rate conversion comprises interpolation and extraction.The frequency of supposing the rear sequence x (n) of sampling is f
i, the frequency of the sequences y (n) of the integral multiple character rate of expectation is f
o, f
i/ f
o=I/D (D and I be prime number each other), interpolation multiple and extracting multiple are respectively I and D.After carrying out I times of interpolation, in order to eliminate the high frequency images of baseband frequency spectrum, need to carry out low-pass filtering, the filter passband bandwidth should be not more than π/I.In like manner, carrying out in order to prevent spectral aliasing, correctly recovering original signal, within signal spectrum must being limited in normalized frequency π/D before D doubly extracts.Two filters that are used for interpolation and extraction are cascade filtering, and identical working clock frequency is arranged, and therefore can be merged into a filter, and pass band width is min{ π/I, π/D}.
Be illustrated in figure 1 as the operation principle schematic diagram of existing fraction time sampling rate conversion, wherein f
s=If
i=Df
o, filters H (ejw) is operated in clock f
sUnder.For broadband signal, f
iUp to 100MHz magnitude, f
sUp to the 1GHz magnitude, so high processing speed makes device be difficult to Digital Implementation.Usually adopt polyphase filter technology (for example multiphase filter) that a complete filter is divided into several subfilters and process respectively, can reduce admirably thus the operating frequency of filter.Multiphase filter can combine with extraction process, also can combine processing with interpolation.
Be illustrated in figure 2 as based on the fraction time sampling rate mapped structure schematic diagram that extracts the end multiphase filter.Wherein, the exponent number N of filter (low pass filter often adopts the FIR structure to realize) should be the integral multiple of extracting multiple D.Set N=QD, if the sequence after interpolation is s (n), the sequence after polyphase filtering, before extraction is z (n):
The FIR filter number of phases is D, h
i(n) be i item subfilter, h
i(n) and s
i(n) be all that D to h (n) and s (n) doubly extracts, initial label is i.Like this that each is cumulative mutually, extract at last and obtain y (n), extraction process can adopt construction of switch to realize.According to the network equivalent principle, with multiphase filtering and withdrawal device transposition, that is: will extract before the factor moves on to multiphase filtering, the convolution algorithm speed of filter is by original f like this
sBe reduced to f
oAlthough reduced convolution algorithm speed based on the multiphase filter that extracts end, the work clock of the register group after interpolation and the input data clock of withdrawal device are all f
s, still have the larger difficulty that realizes.In addition, the multiphase filter structure that combines with withdrawal device should carry out interpolation, extract again, although interpolation and extraction operation are fairly simple, and less stable on hardware is realized.
Be illustrated in figure 3 as the mapped structure schematic diagram based on interior spigot multiphase filter, at this moment, the exponent number N=QI of filter, and if only if when n is the multiple of I, s (n)=x (n/I), other situation is 0, can get:
Wherein 0≤v≤I, for each input x (n), have the mutually independent output of I, carries out afterwards D and doubly extract.Extract and still can adopt construction of switch to realize, just here each clock step amount is D.The multiphase filter structure that combines with interpolater no longer needs to carry out extra interpolation operation, but each input data is to there being I position output data h
0(μ), h
1(μ) ... h
I-1(μ), need also that then these I position output data are carried out D and doubly extract, only have the data of 1/D just can be drawn into, more filtering operation result will directly be dropped.It is huge waste to resource that these results that go out by convolution algorithm finally are dropped essence.
As mentioned above, although use multiphase filter to avoid making filter to be operated in clock f
sUnder, but its lowest operating frequency also is at least f
iOr f
oIn wide-band communication system, f
iOr f
oAll can reach hundreds of MHz, so high speed has very high requirement to hardware, makes fraction time sampling rate mapped structure still be difficult to realize.Therefore, along with signal bandwidth further increases, this class scheme of use polyphase filter technology will be no longer applicable.So necessary consideration further reduces work clock, make it no longer be subject to f
iOr f
oConstraint.In addition, the implementation structure of traditional fraction time sampling rate conversion is all for the design of the serial data of single-input single-output.And in wide-band communication system, in order to reduce processing speed, data are all transmitted by the multidiameter delay mode usually, if will carry out the conversion of fraction time sampling rate like this, with regard to first data being carried out parallel-serial conversion, also to go here and there after sampling rate conversion is complete and change and realize parallel transmission.This has not only increased expense, and parallel-serial conversion has also increased the single channel message transmission rate.
Summary of the invention
The technical problem that (one) will solve
The technical problem to be solved in the present invention is how will be reduced to f based on the arithmetic speed of the fraction time sampling rate mapped structure of multiphase filtering
iOr f
oBelow, and its multidiameter delay that is applicable in wide-band communication system is transmitted.
(2) technical scheme
For solving the problems of the technologies described above, technical scheme of the present invention provides the Parallel Implementation method of a kind of fraction time sampling rate conversion, comprises the following steps:
S1: data sequence x to be transformed (n) take the D road as one group, is designated as x (0), x (1) ..., x (D-1) is by frequency f
i/ D input has in D filtering channel of channel tag, and wherein each described filtering channel comprises the I sub-channels;
S2: for every group of data, obtain I * D road by described D filtering channel and treat operational data;
S3: according to the first presetting rule, treat to extract in operational data the I circuit-switched data with fixed position by described I * D road and carry out convolution algorithm, obtain frequency and be respectively f
oThe I road output data y (0) of/I, y (1) ..., y (I-1);
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other.
Wherein, when described data to be transformed were the single channel serial input, step S1 comprised: input data sequence x (n) is gone here and there and conversion process, obtain frequency and be respectively f
iThe D channel parallel data x (0) of/D, x (1) ..., x (D-1).
Wherein, described method also comprises after step S3: when requiring to export data and be the single channel serial, and to described I road output data y (0), y (1) ..., y (I-1) carries out parallel-serial conversion to be processed, and output frequency is f
oSerial data sequence y (n).
Wherein, in step S2, described the first presetting rule comprises: in the I road valid data that extract, with the mark Y (i) of the corresponding subchannel of i circuit-switched data=(i * D+v) %I, and the corresponding operational data highest order label for the treatment of
Wherein, v is the mark of the corresponding subchannel of first via data of extraction.
This provides the Parallel Implementation device of a kind of fraction time sampling rate conversion technical scheme of the present invention, comprising:
Signal input unit, being used for is f with frequency
iData sequence x to be transformed (n) export to described shift register take the D circuit-switched data as one group;
Shift register is used to the data of described signal input unit output that D+Q-1 data bank bit at least is provided; And,
D multiphase filter, each multiphase filter comprises I subfilter, described D poly phase filter concurrent working, extract the D+Q-1 bit data from described shift register at every turn, and I subfilter of each described poly phase filter inputted identical Q bit data, generate I * D road and treat operational data, and according to the second presetting rule, treat in operational data to extract the I road valid data with fixed position and carry out convolution algorithm by described, obtain I road output data y (0), y (1) ..., y (I-1);
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other; Filter order N=QI, wherein Q is the number of the coefficient of each subfilter; The coefficient of subfilter is that the coefficient of N rank filter extracts take I as the interval, and the start bit that different subfilters extracts is different.
Wherein, described signal input unit comprises deserializer, be used for single channel data sequence x (n) is converted to D channel parallel data x (0), and x (1) ..., x (D-1).
Wherein, described device also comprises: parallel-to-serial converter, be used for described I road output data y (0), and y (1) ..., y (I-1) is converted to serial data sequence y (n).
Wherein, described the second presetting rule comprises: in the I road valid data that extract, with the number of phases mark Y (i) of the corresponding subfilter of i circuit-switched data=(i * D+v) %I, and the corresponding operational data highest order label for the treatment of
Wherein, v is the number of phases of the corresponding subfilter of first via data of extraction.
(3) beneficial effect
Technical scheme of the present invention has been optimized the fraction time sampling rate mapped structure based on interior spigot, the multichannel subfilter for the treatment of computing has been carried out the selecting extraction based on presetting rule, the subfilter that is not drawn into need not carried out computing, thereby reduced computational complexity, the work of multiphase filter can be reduced to f all the time
i/ D or f
o/ I; Owing to once extracting as one group of execution take the D circuit-switched data, the position of each valid data that extract is fixed, and need not to arrange extra abstraction module; In addition, traditional sampling rate conversion scheme is as being applied to the multidiameter delay transmission mode, need first data to be converted to serial, also serial data will be reduced into parallel transmission after being disposed, and technical scheme of the present invention can be applied to direct convenience the multidiameter delay transmission mode of wide-band communication system.
Description of drawings
Fig. 1 is the operation principle schematic diagram of traditional fraction time sampling rate conversion;
Fig. 2 is based on the fraction time sampling rate conversion parallel organization schematic diagram that extracts the end multiphase filter;
Fig. 3 is the fraction time sampling rate mapped structure schematic diagram based on interior spigot multiphase filter;
Fig. 4 is the flow chart according to the Parallel Implementation method of fraction time sampling rate of the present invention conversion;
Fig. 5 is the structural representation according to the Parallel Implementation device of fraction time sampling rate of the present invention conversion;
Fig. 6 is the schematic diagram according to an embodiment of the Parallel Implementation method of fraction time sampling rate of the present invention conversion.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for purpose of the present invention is described, but are not used for limiting scope of the present invention.
Core concept of the present invention is, the mapped structure based on interior spigot multiphase filter improved, and be f with the conversion multiple
o/ f
iThe sampling rate conversion process improvement of=I/D is the transfer process between the parallel input in D road and I road parallel output.Specifically, under the single channel transmission mode, the single channel list entries can be converted into the D channel parallel data; Then the multiphase filter that is I by shift register and the number of phases is realized carrying out once optionally convolution algorithm take D group multiphase filter as one group: treat to extract operational data I road valid data from I * D road and carry out computing, obtain I road output data, and do not need again other (I-1) * D road is treated that operational data carries out computing, can make thus the arithmetic speed of multiphase filter be reduced to f
i/ D or f
o/ I; Carry out at last once also going here and there transforming the output signal sequence that can obtain to have desired data rate.And for the parallel transmission pattern in wide-band communication system, only the bit wide of the transmission of data due to what change in its fraction time sampling rate conversion, the data transfer rate of every road transmission does not change, therefore its fraction time sampling rate conversion process can be improved to the change procedure of data bit width, and variation coefficient is D and I.That is: the present invention stands good for the fraction time sampling rate conversion under the multiplexing pattern to technical scheme, and does not need to carry out the string in early stage and the also string conversion in conversion and later stage again.
Need to prove, although still there is extraction operation in technical scheme of the present invention, the position of the data that are drawn in each extraction operation is all fixed.Specifically, in the extraction operation based on the mapped structure of interior spigot poly phase filter, due to I and D relatively prime, for different input data bit, the position of the phase that extracts and mutually number of extracted and inconsistent.But can observe, after D data of every input, effectively the chosen position of phase can repeat once.That is: the extraction situation (for example, extract the position of phase and the number of extract phase) of input data x when (n) is consistent when inputting data x (n-D).According to technical scheme of the present invention, with x (KD) ... x (k (D+1)-1) D bit data altogether inputs as one group of data, be D the multiphase filter of I for the number of phases, to there be I * D road to treat operational data, if from wherein extracting I valid data, that is: after first data pick-up, every one of D bit extraction, the position of these data that extract is fixed.As mentioned above, can arrange multiphase filter neutron filter coefficient, to realize only effective I circuit-switched data in I * D way filter being carried out computing.
Fig. 4 is the flow chart according to the Parallel Implementation method of the fraction time sampling rate conversion of technical solution of the present invention.By in figure as can be known, method of the present invention comprises the following steps:
S1: data sequence x to be transformed (n) take the D road as one group, is designated as x (0), x (1) ..., x (D-1) is by frequency f
i/ D input has in D filtering channel of channel tag, and wherein each described filtering channel comprises the I sub-channels;
S2: for every group of data, obtain I * D road by described D filtering channel and treat operational data;
S3: according to the first presetting rule, treat to extract in operational data the I circuit-switched data with fixed position by described I * D road and carry out convolution algorithm, obtain frequency and be respectively f
oThe I road output data y (0) of/I, y (1) ..., y (I-1);
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other.
Particularly, in step S1, input signal sequence can be converted to the D channel parallel data with same frequency, and described D channel parallel data is deposited in shift register successively, realize thus the grouping input of input signal sequence; The filtering channel of the described I of comprising sub-channels can be the multiphase filter realization of I by the number of phases, and the channel tag of each subchannel is corresponding to the number of phases mark of each subfilter.
Particularly, in step S3, the data that also need to use last time computing due to each convolution algorithm, and the exponent number N of filter should be the integral multiple (N=QI) of extracting multiple I, filter is divided into I subfilter, the coefficient of each subfilter has Q, and the data that participate in convolutional calculation also should be Q, and this shift register will have more Q-1 memory space at least.That is: this shift register will provide D+Q-1 data bank bit at least.
Participate in because each filtering operation needs Q data, after this Q data are inputted in the multiphase filter that the parallel number of phases in D road is I, I * D road output should be arranged at every turn.According to technical scheme of the present invention, extract I from this I * D road output and carry out convolution algorithm: after selecting the number of phases that initial draw operates, extract again one every the D position, just can extract the I bit data from I * D circuit-switched data.Therefore, the first bit data extracts is which in poly phase filter direct relation the extraction of back.First data of supposing extraction are v phase (that is: the initial phase of extraction), and the number of phases of the corresponding subfilter of i circuit-switched data that is drawn into is labeled as Y (i), according to the data pick-up principle, should have:
Y(i)＝(i×D+v)％I (3)
Wherein, " % " expression division remainder.
In other words, carry out in the I road valid data of computing at the need that extract, should be shown in formula (3) with the number of phases mark of the corresponding subfilter of i circuit-switched data (subchannel).Can be determined the coefficient h of each subfilter by Y (i)
Y (i)(n):
h
Y (i)(n)={ h (Y (i)), h (Y (i)+I), h (Y (i)+2I), ..., h ((Y (i)+(Q-1) I) } start bit (highest order) label of input data of the corresponding subfilter of i circuit-switched data that is drawn into of (4) supposition is designated as c (i), by decimation rule as can be known:
In formula
Expression rounds downwards, and c (i) is namely division business's integer part.
In other words, carry out in the I road valid data of computing at selected need, with the input data highest order label of the corresponding subfilter of i circuit-switched data (subchannel) be c (i) (c (i) in fact represent be which in the D channel parallel data be this circuit-switched data come from).Like this, the input data X (i) of i way filter is:
X (i)=x (c (i)-Q+1) ..., x (c (i)-1), x (c (i)) } the output data y (i) of (6) i way filters is:
As mentioned above, determine the conversion multiple f of expectation
i/ f
oAfter=I/D, determine the number of phases of the first via data of extraction; Determine by formula (5) the i circuit-switched data that extracts comes from which group in D group data; Determine the number of phases of i circuit-switched data in its group of extraction by formula (3); Determine the output data by formula (7).
In addition, for the single channel input and output mode, method of the present invention also comprises after step S3: the I channel parallel data to output carries out parallel-serial conversion, obtains to have the output signal of desired data rate.And for the multidiameter delay transmission mode, technical scheme of the present invention is applicable equally, string and the conversion that only need save the parallel-serial conversion in step S1 and transmit for single channel.
Correspondingly, as shown in Figure 5, based on above-mentioned fraction time sampling rate transform method, the Parallel Implementation device of the fraction time sampling rate conversion of technical solution of the present invention should comprise:
Signal input unit, being used for is f with frequency
iData sequence x to be transformed (n) export to described shift register take the D circuit-switched data as one group; For the single channel transmission mode, described signal input unit should comprise deserializer as shown in Figure 5, be used for single channel data sequence x (n) is converted to D channel parallel data x (0), and x (1) ..., x (D-1);
Shift register is used to the data of described signal input unit output that D+Q-1 data bank bit at least is provided; And
D multiphase filter, each multiphase filter comprises I subfilter, the place extracts the D+Q-1 bit data at every turn by described shift register, and to the identical Q bit data of I subfilter input of each described poly phase filter, generates I * D road and treats operational data, and according to the second presetting rule, treat in operational data to extract the I road valid data with fixed position and carry out convolution algorithm by described, obtain I road output data y (0), y (1), ..., y (I-1);
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other; Q is the number of the coefficient of each subfilter; The subfilter coefficient is that the coefficient of N rank filter extracts take I as the interval, and the start bit that different subfilters extracts is different.
In addition, for the single channel input and output mode, this device also should comprise parallel-to-serial converter as shown in Figure 5, be used for described I road output data y (0), and y (1) ..., y (I-1) is converted to serial data sequence y (n).
Preferably, the second presetting rule comprises: carry out in the I road valid data of computing at selected need, with the number of phases mark Y (i) of the corresponding subfilter of i circuit-switched data=(i * D+v) %I, and the corresponding operational data highest order label for the treatment of
Wherein, v is the number of phases of the corresponding subfilter of first via data of extraction.
The below will by specific embodiment, be elaborated to technical scheme of the present invention.
As shown in Figure 6, the transmission rate f that supposes data under the single channel input and output mode is 150M, is divided into 5 road parallel transmissions by going here and there and changing, and namely data transfer rate is 750M.Suppose that the character rate that requires is 300M, need to carry out the conversion of fraction time sampling rate, making data clock is the integral multiple of character rate.If the conversion multiple of expectation is 4 times (1.2G), by the transmission rate of single channel 150M, need altogether 8 circuit-switched data outputs, therefore, need to convert 5 circuit-switched data to 8 circuit-switched data by the conversion of fraction time sampling rate and transmit.
In the present embodiment, the value of I and D is respectively 8 and 5, the number of phases of filter is 8, setting the FIR filter is 32 rank, and filtering operation need to relate to 4 data, therefore the length of input register should be at least 5+4-1=8, each memory space is designated as x (3) successively, x (2) ..., x (4).In 5 tunnel input data that generate after serial to parallel conversion, 5 bit data of each input deposit in five memory spaces that are labeled as x (0)～x (4) of register from front to back successively, and the x (2) of last storage～x (4) moves to x (3)～x (1) x (μ) simultaneously.5 bit data of each input all to 8 bit data outputs should be arranged, are designated as: y (0), and y (1) ... y (7).The start-up phase v that supposes extraction is 1, and by formula (3) formula as can be known, the number of phases mark of these 8 subfilters is respectively: 1,6,3,0,5,2,7,4, simultaneously by formula (5) as can be known the data highest order label of every way filter be respectively: 0,0,1,2,2,3,3,4.8 bit data that needed as can be known to calculate and export by formula (7) are:
y(0)＝y
0(1)＝h(1)x(0)+h(9)x(-1)+h(17)x(-2)+h(25)x(-3)；
y(1)＝y
0(6)＝h(6)x(0)+h(14)x(-1)+h(22)x(-2)+h(30)x(-3)；
y(2)＝y
1(3)＝h(3)x(1)+h(11)x(0)+h(19)x(-1)+h(27)x-2)；
y(3)＝y
2(0)＝h(0)x(2)+h(8)x(1)+h(16)x(0)+h(24)x(-1)；
y(4)＝y
2(5)＝h(5)x(2)+h(13)x(1)+h(21)x(0)+h(29)x(-1)；
y(5)＝y
3(2)＝h(2)x(3)+h(10)x(2)+h(18)x(1)+h(26)x(0)；
y(6)＝y
3(7)＝h(7)x(3)+h(15)x(2)+h(23)x(1)+h(31)x(0)；
y(7)＝y
4(4)＝h(4)x(4)+h(12)x(3)+h(20)x(2)+h(28)x(1) (8)
Like this, by the conversion of fraction time sampling rate, just the data with 5 road 150M have become 8 road 150M data, and making data transmission rate is 4 times of character rate, can be advantageously used in the processing of subsequent module.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (6)
1. the Parallel Implementation method of fraction time sampling rate conversion, is characterized in that, said method comprising the steps of:
S 1: be f with frequency
iData sequence x to be transformed (n) take the D road as one group, be designated as x (0), x (1) ..., x (D-1) is f by frequency
i/ D input has in D filtering channel of channel tag, and wherein each described filtering channel comprises the I sub-channels;
S2: for every group of data, obtain I * D road by described D filtering channel and treat operational data;
S3: according to the first presetting rule, treat to extract in operational data the I circuit-switched data with fixed position by described I * D road and carry out convolution algorithm, obtain frequency and be respectively f
oThe I road output data y (0) of/I, y (1) ..., y (I-1);
Described the first presetting rule comprises: in the I road valid data that extract, with the mark Y (i) of the corresponding subchannel of i circuit-switched data=(i * D+v) %I, and the corresponding operational data highest order label for the treatment of
Wherein, v is the mark of the corresponding subchannel of first via data of extraction;
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other.
2. the Parallel Implementation method of fraction time sampling rate as claimed in claim 1 conversion, it is characterized in that, when described data to be transformed were the single channel serial input, step S1 comprised: input data sequence x (n) is gone here and there and conversion process, obtain frequency and be respectively f
iThe D channel parallel data x (0) of/D, x (1) ..., x (D-1).
3. the Parallel Implementation method of fraction time sampling rate as claimed in claim 2 conversion, it is characterized in that, and described method also comprises after step S3: when requiring to export data and be the single channel serial, to described I road output data y (0), y (1), ..., y (I-1) carries out parallel-serial conversion to be processed, and output frequency is f
oSerial data sequence y (n).
4. the Parallel Implementation device of fraction time sampling rate conversion, is characterized in that, described device comprises:
Signal input unit, being used for is f with frequency
iData sequence x to be transformed (n) export to shift register take the D circuit-switched data as one group;
Shift register is used to the data of described signal input unit output that D+Q-1 data bank bit at least is provided; And,
D multiphase filter, each multiphase filter comprises I subfilter, described D multiphase filter concurrent working, extract the D+Q-1 bit data from described shift register at every turn, and I subfilter of each described multiphase filter inputted identical Q bit data, generate I * D road and treat operational data, and according to the second presetting rule, treat in operational data to extract the I road valid data with fixed position and carry out convolution algorithm by described, obtain I road output data y (0), y (1) ..., y (I-1);
Described the second presetting rule comprises: in the I road valid data that extract, with the number of phases mark Y (i) of the corresponding subfilter of i circuit-switched data=(i * D+v) %I, and the corresponding operational data highest order label for the treatment of
Wherein, v is the number of phases of the corresponding subfilter of first via data of extraction;
Wherein, f
o/ f
i=I/D is fraction time sampling rate conversion multiple, and I and D be prime number each other; Filter order N=QI, wherein Q is the number of the coefficient of each subfilter; The coefficient of subfilter is that the coefficient of N rank filter extracts take I as the interval, and the start bit that different subfilters extracts is different.
5. the Parallel Implementation device of the fraction time sampling rate conversion as shown in claim 4, is characterized in that, described signal input unit comprises deserializer, be used for single channel data sequence x (n) is converted to D channel parallel data x (0), x (1) ..., x (D-1).
6. the Parallel Implementation device of the fraction time sampling rate conversion as shown in claim 5, is characterized in that, described device also comprises: parallel-to-serial converter, be used for described I road output data y (0), y (1) ..., y (I-1) is converted to serial data sequence y (n).
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| US9531343B2 (en) * | 2015-03-20 | 2016-12-27 | Texas Instruments Incorporated | Systems and methods of variable fractional rate digital resampling |
| CN105743508B (en) * | 2016-02-29 | 2019-03-01 | 卡斯柯信号有限公司 | A kind of credible acquisition method of binary channels of different engagement code distance |
| CN109726707B (en) * | 2019-02-27 | 2022-02-01 | 电子科技大学 | Method for selecting sampling rate of signal source in DDWS system |
| CN110212889B (en) * | 2019-05-29 | 2020-11-13 | 北京机电工程研究所 | Digital signal sampling device and method |
| CN110190829B (en) * | 2019-05-30 | 2023-05-23 | 北京星网锐捷网络技术有限公司 | Filter and filtering method |
| CN116132232B (en) * | 2021-11-15 | 2024-04-19 | 西安电子科技大学 | Multipath parallel up-sampling method for high-speed digital communication |
| CN115021768A (en) * | 2022-05-26 | 2022-09-06 | 中国电子科技集团公司第十研究所 | Four-way parallel sampling method, device, equipment and medium based on polyphase filtering |
| CN116910456B (en) * | 2023-09-13 | 2023-12-01 | 北京坤驰科技有限公司 | Filtering method, device, electronic equipment and computer readable storage medium |
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| CN1152820A (en) * | 1995-10-20 | 1997-06-25 | 株式会社鹰山 | Matched filter circuit used for frequency-expansion communication |
| CN1376333A (en) * | 1999-08-27 | 2002-10-23 | 马库尼通信有限公司 | Filter unit comprising a core filter, decimator and inter polator |
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