CN102064129A - Semiconductor process using mask openings of varying widths to form two or more device structures - Google Patents
Semiconductor process using mask openings of varying widths to form two or more device structures Download PDFInfo
- Publication number
- CN102064129A CN102064129A CN2010105541778A CN201010554177A CN102064129A CN 102064129 A CN102064129 A CN 102064129A CN 2010105541778 A CN2010105541778 A CN 2010105541778A CN 201010554177 A CN201010554177 A CN 201010554177A CN 102064129 A CN102064129 A CN 102064129A
- Authority
- CN
- China
- Prior art keywords
- groove
- opening
- layer
- etching
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.
Description
The cross reference of relevant application
The application requires the priority of the U.S. Provisional Patent Application 61/261,043 of submission on November 13rd, 2009, and this application is all quoted at this as a reference.
Summary of the invention
The invention provides a kind of in forming the process of semiconductor device employed method, this method comprises: form mask on the upper surface of a bottom, wherein, described mask comprises and is positioned at first opening among the described mask and is positioned at second opening among the described mask, wherein, first aperture efficiency, second opening is wide; By first and second openings described bottom is carried out etching, have first groove of first width and form second groove with second width in described bottom to form in described bottom, wherein, first groove is wideer than second groove; Forming a conforma layer on the described bottom and within first and second grooves, wherein, described conforma layer does not touch oneself in first groove, but touches own in second groove; Under the situation that conforma layer in first and second grooves exposes, described conforma layer is carried out etching so that described bottom exposes at the first groove place with second etching, wherein, during second etching, described bottom does not expose at the second groove place; And under the situation about exposing of the conforma layer in second groove, described bottom is etched with the degree of depth that increases first groove with the 3rd etching, wherein, after carrying out the 3rd etching, first groove is darker than second groove.
According to an aspect of the present invention, said method also comprises: forming dielectric layer within first groove and on second groove; And make described dielectric layer leveling, wherein, after making described dielectric layer leveling, described dielectric layer is still stayed in first groove.
According to an aspect of the present invention, said method also comprises: form a conductive layer in first groove and on second groove; And make described conductive layer leveling, wherein, after making described conductive layer leveling, described conductive layer is still stayed in first groove.
According to an aspect of the present invention, in said method, first conforma layer in second groove be shallow trench isolation from.
According to an aspect of the present invention, in said method, second conformal dielectric layer in first groove is isolated first and second condenser armatures and described bottom electricity.
According to an aspect of the present invention, in said method, described conforma layer is a conformal dielectric layer, and described method also comprises: in the 3rd etching process, form dielectric spacers from described conformal dielectric layer; And after carrying out the 3rd etching, within first groove, form a conformal conductive layer, wherein, the conformal dielectric layer in second groove prevents to form conformal electrically conductive layers in second groove.
According to an aspect of the present invention, said method also comprises: remove described conformal electrically conductive layers from the upper surface of described bottom, wherein, after the upper surface of described bottom is removed described conformal electrically conductive layers, described conformal dielectric layer is isolated the upper area electricity of conformal electrically conductive layers and described bottom, and wherein, described conformal dielectric layer does not make the lower area electricity of described conformal electrically conductive layers and described bottom isolate.
The present invention also provides a kind of semiconductor device, and it comprises: the semiconductor layer with upper surface; Be positioned at the doping buried layer of the upper surface below of described semiconductor layer; Conduction absorbs the utmost point, and the described conduction absorption utmost point contacts the doping buried layer at first degree of depth place in the described semiconductor layer and exposes at the upper surface place of described semiconductor layer; And at least one area of isolation in described semiconductor layer, described at least one area of isolation comprises first and second portion, described first has first width and extends to described first degree of depth from the upper surface of described semiconductor layer, described second portion has than narrow second width of first width and from described first degree of depth and extends to lateral attitude with respect to described doping buried layer, wherein, at least a portion of the described conduction absorption utmost point and described at least one area of isolation comprises same one deck.
According to an aspect of the present invention, in above-mentioned semiconductor device, described is first conductive layer with one deck, and described at least one area of isolation further comprises: formed second conductive layer below the upper surface of described semiconductor layer, wherein, the described conduction absorption utmost point does not comprise second conductive layer.
According to an aspect of the present invention, above-mentioned semiconductor device also comprises: described semiconductor substrate is included at least two first openings in the described semiconductor substrate; Doping buried layer within semiconductor substrate, wherein, described doping buried layer is directly inserted between described two first second layers in the opening at least, and the dielectric ground floor in described at least one second opening directly overlays above the described doping buried layer.
The present invention also provides a kind of semiconductor device, and it comprises: semiconductor substrate, at least one first opening is arranged in described semiconductor substrate, and wherein, described at least one first opening comprises first width, first degree of depth, upper and lower; Described semiconductor substrate is included at least one second opening in the described semiconductor substrate, and wherein, described at least one second opening comprises second width and second degree of depth, and wherein, first width is wideer than second width, and it is dark that first depth ratio, second degree of depth is wanted; Dielectric layer within described at least one first opening and described at least one second opening, wherein, described dielectric layer is filled described at least one second opening and is not filled described at least one first opening, and described dielectric layer is positioned at the top of described at least one first opening and is not positioned at the bottom of described at least one first opening; And conductive layer, described conductive layer is within described at least one first opening and not within described at least one second opening, wherein, described conductive layer is positioned at the top of described at least one first opening and the bottom of described at least one first opening, and described dielectric layer is isolated the top electricity of the described conductive layer and first opening.
According to an aspect of the present invention, above-mentioned semiconductor device also comprises: described semiconductor substrate is included at least two first openings in the described semiconductor substrate; Doping buried layer within semiconductor substrate, wherein, described doping buried layer is directly inserted between the conductive layer within the bottom of described two first openings at least, and the dielectric layer in described at least one second opening directly overlays above the described doping buried layer.
The present invention also provide a kind of in forming the process of semiconductor device employed method, this method comprises: the mask that forms patterning on a bottom, wherein, the mask of patterning comprises first opening with first width and second opening with second width, and second width is narrower than first width; Carry out first etching, form first groove and described bottom is etched with formation second groove by first opening described bottom is etched with simultaneously by second opening, described first groove has a bottom and its width is approximately identical with first width, and described second groove has a bottom and its width is approximately identical with second width; And before forming the second photoresist mask on the described bottom, etching is carried out in the bottom of first groove but etching is not carried out in the bottom of second groove.
The present invention also provides a kind of electronic system, it comprises: semiconductor device, and this semiconductor device comprises: semiconductor substrate has at least one first opening in described semiconductor substrate, wherein, described at least one first opening comprises first width, first degree of depth, upper and lower; Described semiconductor substrate is included at least one second opening in the described semiconductor substrate, and wherein, described at least one second opening comprises second width and second degree of depth, and wherein, first width is wideer than second width, and it is dark that first depth ratio, second degree of depth is wanted; Ground floor within described at least one first opening and described at least one second opening, wherein, described ground floor is filled described at least one second opening and is not filled described at least one first opening, and described ground floor is positioned at the top of described at least one first opening and is not positioned at the bottom of described at least one first opening; And the second layer, the described second layer is within described at least one first opening and not within described at least one second opening, and wherein, the described second layer is positioned at the top of described at least one first opening and the bottom of described at least one first opening; And power supply, be adapted to described semiconductor device power supply.
According to an aspect of the present invention, in above-mentioned electronic system, described semiconductor device is a processor, and described electronic system further comprises: at least one memory devices that is coupled to described processor by bus; And described power supply is adapted to described semiconductor device power supply.
According to an aspect of the present invention, in above-mentioned electronic system, described semiconductor device is a memory devices, and described electronic system further comprises: at least one processor that is coupled to described memory devices by bus; And described power supply is adapted to described at least one processor power supply.
Description of drawings
The accompanying drawing that comprises in this manual and constitute the part of this specification show embodiments of the present invention and with specifically describe one and be used from and explain principle of the present invention.In the accompanying drawings:
Fig. 1-30 is to use the cross-sectional view of the various intermediate structures of embodiments of the present invention formation; And
Figure 31 is the schematic description that comprises the electronic system of embodiments of the present invention.
Should be noted that, simplified some details in the accompanying drawing, the drafting of accompanying drawing is not really want to keep strict structure accuracy, details and ratio in order to help to understand embodiments of the present invention.
Embodiment
Now will be in detail with reference to embodiments of the present invention (illustrative embodiments), its example shown in the drawings.Under possible situation, label identical in institute's drawings attached will refer to same or analogous parts.
Various execution mode of the present invention comprises: use the single masks, form two or more structures.For example, can use single mask process process to form many structures, these structures comprise area of isolation, the absorption utmost point (sinker) and the dark base stage of lateral bipolar transistor device (such as PNP or NPN device).Hereinafter exemplary description combines a class device (such as the lateral PNP device), but should be appreciated that, also can form the opposite device (such as the NPN device) of conductivity with similar technology.An execution mode is based on the use of narrow opening and wide opening, can use the single masks to make these patterns of openingsization to form the opening of different depth simultaneously, and this depends on initial A/F.In this article, use term " opening ", " groove ", " depression " and " groove " interchangeably, because can comprise in elongated open, circle, ellipse, square, rectangle, the annular etc. one or more when observing the original shape of above-mentioned two or more grooves or opening in plane graph, this depends on the final structure that will form.
In addition, when using term " wide " and " narrow " to describe opening, be meant two or more openings here, wherein wide aperture efficiency narrow opening is wide.Use these terms to simplify description of the invention, but not be used to indicate the size of these openings with respect to any structure different with one or more other openings.
In the described exemplary process of Fig. 1-7, can (such as first oxide layer, its thickness be about 500 with the hard mask 10 of cover layer
To about 10,000
Or thicker, this depends on the degree of depth of groove) be deposited on the bottom 12 (such as semiconductor wafer, wafer substrate assembly (substrate), epitaxial loayer or two-layer or more multi-layered combination), then, press it finer and close.Hard mask layer also can be a sandwich construction, and such as oxide-nitride thing-oxide (ONO) sandwich, this sandwich comprises that thin pad oxide is (such as 50
To 300
Oxide), then be that nitride is (such as 300
To 1,500
), then be that thicker oxide is (such as 1,000
To 10,000
).Can be with the nitride layer that adds as the etching of subsequent treatment process-stop layer.Above-mentioned bottom 12 can comprise various other the layer and structure, doped regions etc., these can find in the device in the course of processing well known by persons skilled in the art.
The mask 14 that can form patterning is to produce structure shown in Figure 1, and mask 14 can be the groove contact mask, has big critical dimension (CD) that is used for wide and dark groove and the narrow CD that is used for narrower and more shallow groove.The mask 14 of patterning comprises wide opening 16 and narrow opening 18.
Next, can carry out etching and patterned process with the hard mask 10 of 14 pairs of above-mentioned cover layers of mask and the bottom 12 of patterning.In the alternative, after hard mask 10 carries out etching and patterned process to cover layer, can remove the mask 14 of patterning, then, be used for bottom 12 is carried out etching.In arbitrary processing procedure, to use first etching that bottom 12 is carried out etching, and remove the structure of the mask 14 of patterning with generation Fig. 2, this structure comprises the hard mask 10 of patterning.Can use standard technique to carry out this etching, optionally silicon is carried out etching and faster than mask material.The above-mentioned bottom of (anisotropically) etching (such as silicon) preferably vertically.Various etching techniques be can use, RIE (MERIE), inductively coupled plasma (ICP), transformer coupled plasma (TCP) or the like strengthened such as plasma etching, reactive ion etching (RIE), magnetic.Fig. 2 has described wide opening 16 and narrow opening 18, and they are openings within the hard mask 10 of patterning and bottom 12, and produces because of above-mentioned first etching.Should be noted that according to employed etching technique, the degree of depth of narrow groove 18 can be more shallow than the degree of depth of wide groove 16, for example, this causes because of dry corrosion effect known in the art.In addition, this point place at process sequence can carry out optional injection, being mixed in zones such as wide trenched side-wall 20, narrow trenched side-wall 22 and/or channel bottom zone 24,26.
Next, deposited conformal dielectric layer 30 and produce the structure of Fig. 3 on the hard mask 10 of patterning and bottom 12, the thickness of this layer 30 is half of width of narrow opening 18 at least, for example, be about 0.7 times of width of narrow opening, and less than half of the width of wide opening 16.Conformal dielectric layer 30 can be made of oxide, and this conformal dielectric layer 30 touches own in narrow opening 18, this conformal dielectric layer 30 does not touch oneself in wide opening 16, and this just causes thick than in the wide opening 16 of layer in the narrow opening 18.That is, conformal dielectric layer 30 remains conformal in first (wide) opening 16, but has filled up this second narrow opening 18 with material basically because of touching oneself in second (narrow) opening 18.It should be appreciated by those skilled in the art that and some material gaps (" keyhole ") when conformal dielectric layer 30 touches oneself, may occur.Conformal dielectric layer 30 can deposit with various technology, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atmospheric pressure CVD (ACVD), sub-atmospheric pressure CVD (SACVD), ald (ALD) or the like.Although specifically mentioned oxide, may be suitable according to other material of above-mentioned application, such as oxynitride, the oxide that is rich in silicon, non-silicon-base oxide or the like.
Next, can on the structure of Fig. 3, carry out vertical orientated anisotropic etching, thereby sidewall 20 places at wide opening 42 produce dielectric spacers 40, and can to the conformal dielectric layer in the narrow opening 18 30 carry out etching and planarizing process but and remove layer 30 by halves, thereby produce dielectric plug 44 shown in Figure 4.Thus, dielectric spacers 40 and dielectric plug 44 are to be made of etched conformal dielectric layer 30.In the position of wide opening 16, dielectric spacers 40 in fact, provides narrower the 3rd opening 42, the three openings 42 to pass the hard mask 10 of patterning and enter into bottom 12.By using plasma etching, RIE, MERIE and other directivity dry etch techniques, can carry out the anisotropic etching of conformal dielectric layer 30, this is selectively to bottom 12 on every side.
After forming the structure of Fig. 4, can pass second etching that the 3rd opening 42 is carried out bottoms 12, thereby the 3rd opening 42 is transferred to 50 places, position in the bottom 12.The silicon etching of the bottom 12 that this etching is carried out before can be in the above-mentioned process, this etching is also carried out etching to the bottom 12 of the position of narrow opening 18, and produced the structure similar to Fig. 5 indistinctively.Thus, the hard mask 10 of formed single patterning when in twice etch processes, having used present embodiment to begin, thus formation has a plurality of openings of at least three different in width (i.e. etched wide opening 16 and narrow opening 18 and the opening 42 at 50 places, etched position for the first time for the second time) and at least two different depths.At this moment, can use material such as boron that the bottom 12 that exposes is carried out optional dopant injects.Dopants such as boron (have or do not have tilt and/or rotation) can be injected in the bottom of exposing and/or sidewall of above-mentioned opening, forming various structures, such as: P type area of isolation (in N doping background area); One or more conductions of (such as P+ buried layer or P trap) absorb the utmost point to the P zone of burying; And/or be used for the dark P doped region (the dark P zone that is used for collector and emitter) of high-performance lateral PNP transistor.The alternate embodiment of above-mentioned opening being mixed with N type dopant is possible, and can randomly carry out annealing after ion injects.
Next, can remove dielectric spacers 40 and dielectric plug 44, thereby produce the structure of Fig. 6.This etching can make hard mask 10 thinnings of patterning, but also not exclusively removes this hard mask 10.If necessary, can carry out optional channel bottom and/or sidewall injects, the conductivity of the bottom 12 that exposes with adjusting to the structure of Fig. 6.By using dry corrosion, such as reactive ion etching (RIE) or chemico-mechanical polishing (CMP), can carry out the thick polysilicon deposition and eat-back (etchback), to remove polysilicon layer from semiconductor substrate upper surface top.This has produced polysilicon structure 70,72, and these structures are stayed in the groove as shown in Figure 7.Can form the polysilicon layer of polysilicon structure 70,72, its thickness can be greater than half of the width of the groove of broad, makes polysilicon layer touch own in each groove and has avoided the center of groove 16,18,42 to occur sinking significantly.In addition, by using in-situ techniques, ion injection etc., polysilicon structure 70,72 can be unadulterated or mix that this depends on above-mentioned application.Next, can carry out oxide etching or CMP, to remove the hard mask 10 of patterning.Subsequently, can carry out processing of wafers, the semiconductor device of finishing with generation.This method is of great use for forming low resistance P+ buried layer (PBL) structure (such as the bipolar device the sort of and shown in Figure 15 shown in Figure 12,13), hereinafter can be described.
Fig. 8 has described another execution mode, and its processing that begins similar to shown in Fig. 1-5.Form to similar structure shown in Figure 5 after, mix conductively or unadulterated polysilicon layer (it can be conformal) can be deposited and being flattened, to produce the structure of Fig. 8, this structure comprises the dielectric spacers 84 at the hard mask 82 of bottom 80, patterning, wide opening 86 places, the dielectric plug 88 and the polysilicon structure 92 (it can conduct electricity) at narrow opening 90 places, and is such just as shown in the figure.Conformal dielectric layer 88 in the narrow opening 90 can prevent to form polysilicon layer 92 in narrow opening 90.The hard mask 82 of patterning be can constitute by first oxide skin(coating), and can dielectric spacers 84 and dielectric plug 88 be constituted by second oxide skin(coating).
This method is of great use for forming a kind of structure, and this structure comprises: the shallow trench isolation that is made of the plug in the shallow and narrow groove 90 88 is from (STI); And the darker polysilicon that formed polysilicon structure 92 constitutes in the groove 86 by broad is isolated.In Figure 16 and describe this structure hereinafter.Dielectric spacers 84 can prevent that polysilicon structure 92 from contacting with the top of semiconductor substrate 80.
Fig. 9 shows and another similar execution mode shown in Figure 8, and this execution mode can comprise: form dielectric medium structure 94, with the polysilicon structure 92 of alternate figures 8.Can constitute dielectric medium structure 94 by the trioxide layer.Thus, the structure of finishing can comprise those elements shown in Figure 8, and difference is that the structure 94 of Fig. 9 can comprise oxide or another kind of dielectric substance (such as silicon nitride etc.).Next, by using the wet etching or the dry etching of CMP or leveling, can the hard mask 82 of patterning be eat-back, this has removed all materials that expose with about identical speed.This method can be used to form shallow trench isolation in narrower groove 90 from (STI) 88 and the darker isolation in wide groove 86 84,94.Figure 17 has described to use the structure of the method for Fig. 9, hereinafter can be described.
Figure 10-12 has described another exemplary execution mode.Present embodiment can start from the structure of Fig. 5 of the execution mode formation of being described according to Fig. 1-5.Form to similar structure shown in Figure 5 after, formed conformal oxide skin(coating) 110 or another dielectric, form conformal polysilicon layer 112 afterwards again.In exemplary execution mode, the width of wide groove 114 can be from being about 5,000
To being about 15,000
, and the width of narrow groove 116 can be from being about 2,000
To being about 10,000
The thickness that can form conformal oxide 110 is from being about 1,200
To being about 7,000
, and the thickness of conformal polysilicon 112 can be from being about 3,000
To being about 15,000
Touch oneself and filled up narrow opening 116 thereby form the enough big conformal oxide skin(coating) 110 of thickness, and conformal oxide skin(coating) 110 and conformal polysilicon layer 112 do not touch own and be conformally formed within wide opening 114.
Can carry out anisotropic (vertical) sept dry corrosion, this dry corrosion etching conformal polysilicon layer 112, and for conformal oxide skin(coating) 110 is optionally, to remove conformal polysilicon layer 112 from the surface of level, thereby produce inter polysilicon parting 118, as shown in Figure 10.Next, immediately following after conformal oxidate, carrying out planarizing process, thereby make oxide plug 120 fill up opening in the wide groove, such as shown in Figure 11.Can proceed planarizing process (perhaps can carry out other method step), with a plurality of parts of the hard mask 10 of removing conformal dielectric 110 and patterning, thereby produce the structure of Figure 12, this is included in the oxide plug 112 in the narrow opening 116.Can be with inter polysilicon parting 118 as two of capacitor parallel plates, oxide plug 120 then provides capacitor dielectric.In the present embodiment, can use plug 122, and conformal oxide skin(coating) 110 make first and second condenser armatures 118 and bottom (being semiconductor substrate 12) electricity isolation mutually as STI.
It will be apparent to those skilled in the art that, can revise the structure of above-mentioned processing and gained, have the various features in semiconductor devices of different pattern, width and/or material thereby use the single masks to form.The exemplary method and the structure of gained have hereinafter been described.
Figure 13 has described substrate 130 (such as silicon wafer) and has been formed at epitaxial loayer 132 on the substrate 130.Should be appreciated that in the alternative, alternatively, substrate 130 and epitaxial loayer 132 can be single semiconductor layers, epitaxial loayer 132 is the doped regions in the substrate.Figure 13 has further described doped P+buried layer (PBL) 134, and for example, thereby this is to use the enough big mask of energy to inject to bury the layer 134 that this injection forms.Also described narrow and shallow polysilicon contact (the absorption utmost point) 136, this contact 136 electrically contacts to PBL 134 and P+ polysilicon isolation structure 138.
According to above-mentioned technology,, can form polysilicon contact 136 and P+ polysilicon isolation structure 138 by using the single mask process.Use the wide opening in mask and the sept to form polysilicon isolation structure 138, and use the narrow opening in the mask to form polysilicon contact 136.In addition, can constitute at least a portion that polysilicon absorbs the utmost point 136 and polysilicon isolation structure 138 by identical polysilicon layer.
Should be noted that the phrase of Shi Yonging " identical layer ", " identical dielectric layer ", " identical conductive layer " etc. are meant the material that forms one deck in manufacture process in two or more positions simultaneously in this article.
The cross section of Figure 14 has been described many details of the structure of Figure 13.Figure 14 can comprise P type semiconductor substrate 130 (for example, semiconductor wafer) and N type epitaxial loayer 132.Within P type substrate 130, form the N buried layer 140 that is injected into, then, in N type epitaxial loayer 132 and N type buried layer 140, inject PBL 134.Form in above-mentioned opening after the P doped polysilicon layer 136,138, so that P diffusion 142 to be provided, and P type ions diffusion spreads 144 to form P to P type ions diffusion outside polysilicon contact 136 outside the polysilicon isolation structure 138.
Figure 13,14 has described a kind of structure, and wherein, the P+ polysilicon absorbs first degree of depth place of the utmost point 136 in semiconductor layer and touches PBL 134, and exposes at the upper surface place of semiconductor layer 132.In addition, two polysilicon structures 138 and P diffusion 142 isolation structures that provide within semiconductor layer 132, these isolation structures laterally are positioned at the either side of PBL 134, make PBL 134 be inserted directly into by between 138,142 two isolation that provided.Each area of isolation comprises: the first 146 with first horizontal width; And second portion 148, the second horizontal widths with second horizontal width are narrower than first horizontal width.The first 146 of each area of isolation 138 extends to first degree of depth from the upper surface of semiconductor layer 132, and second portion 148 extends to lateral attitude with respect to the buried layer 134 that mixes from first degree of depth.Figure 15 has described a kind of structure that comprises semiconductor substrate 150 and epitaxial loayer 152, although can use the well area in the semiconductor layer to substitute epitaxial loayer 152.Figure 15 has further described the N+ buried layer (NBL) 154 of formation in substrate 150 and epitaxial loayer 152.Comprise the execution mode of above-mentioned technology by use, these structures can be used to form the high-performance bipolar semiconductor device, such as the lateral PNP device.
In one embodiment, by using above-mentioned technology within the single mask layer, to form two wide openings and three narrow openings, and this processing procedure continues with the polysilicon layer that leveling is provided (for example, P+ mix the conformal polysilicon of single leveling) to be provided at the polysilicon within wide opening and the narrow opening as described.In the present embodiment, the polysilicon 156 in the wide opening provides P+ polysilicon isolated material.P+ polysilicon in the narrow opening has formed P+ polysilicon collector electrode 158 and P+ polysilicon emitter 160.If necessary, thus can form a plurality of structures that other structure provides the lateral PNP device.
Thus, include only a mask and include only the treatment process of a polysilicon layer, formed two isolation structures 156, two PNP device collector electrodes 158 and PNP device emitters 160 by use.Be provided for the dark base stage of PNP device by collector electrode 158 and emitter, constitute above-mentioned isolation by the material 158 in the wide opening that mask layer limited.N+ buried layer 154 can be used for isolating horizontal PNP.N+ buried layer 154 also can be used to reduce or eliminate formed parasitics vertical bipolar structure between substrate 150 and lateral PNP collector electrode 158 and emitter 160 zones, as known in the art.
Should be noted that two or more openings that drawn in the cross section may be two different parts of same opening, for example, if opening is square, rectangle or circular words.For example, in Figure 15, material 158 is formed at two parts that wherein those two narrow openings can be the same openings that constitute by annular, is used for being formed at wherein that opening round material 160.Thus, material 158 can fully encase material 160, perhaps can be from three sides round material 160.Thus, be formed at wherein three narrow openings, should be appreciated that the description of three openings will be included in the execution mode that forms two structures 158 in the single groove that forms according to annular, square, rectangle, U-shaped etc. although Figure 15 has described material 158,160.Should notice further that in one embodiment, the lateral PNP transistor that comprises device collector electrode 158 and device emitter 160 of gained can be compacter than normal structure.Can obtain such result, be because dark emitter and collector zone can be to form with little open area.In addition, the lateral PNP of gained can realize the performance higher than standard lateral PNP device (higher current gain, improved high current delivery ability etc.), this is that the high-aspect-ratio of emitter and source electrode causes, and because these emitters and source region are high doped.Two kinds of dissimilar isolation structures that Figure 16 has described to use technology of the present invention to form, for example, as Fig. 1-5 and 8 described.In order to illustrate, these isolation structures are formed within semiconductor substrate 162 (such as semiconductor wafer) and the epitaxial loayer 164.As previous execution mode, the buried layer 166 of doping can be injected in semiconductor substrate 162 and/or the epitaxial loayer 164, and this depends on final purposes.
In the present embodiment, according to above-mentioned technology, formed the mask with two wide openings and two narrow openings, this mask is used to etching epitaxial loayer 164 and semiconductor substrate 162.This has formed wide opening 168 within layer 164,162, and has formed narrow opening 170 in layer 164.Formed conformal dielectric layer (such as oxide), this conformal dielectric layer touches oneself in narrow opening 170, but does not touch oneself in wide opening 168.Next, vertical orientated anisotropic etching has formed dielectric spacers 172 within wide groove 168 and the dielectric plug 174 within narrow opening.
Next, used etching, the part of exposing (is optionally for dielectric spacers 172 and dielectric plug 174) of epitaxial loayer 164 and semiconductor substrate 162 has been removed in this etching, thereby makes the opening darker (promptly having increased its degree of depth) at wide opening 168 places.Remove this mask, form and conformal electrically conductive layers that the material of leveling such as polysilicon constitutes, thus the generation structure that Figure 16 described, and this structure is included in the polysilicon 176 of conduction of the position of wide opening 168.
In the present embodiment, dielectric plug 174 has constituted the dielectric isolation in the narrow opening 170, and the polysilicon 176 of conduction has constituted the isolation of conduction, and the isolation of this conduction is isolated by the dielectric spacers 172 and the upper surface electricity of epitaxial loayer 164.Only use a mask and form isolation 176 whole of wide opening 168, narrow opening 170, dielectric plug 174 (being commonly called " shallow trench isolation from " or " STI "), dielectric spacer 172 and conduction.Form the isolation 176 of the conduction of enough degree of depth, thereby touch substrate (being semiconductor wafer, wafer part, epitaxial loayer etc.) 162.The buried layer 166 that mixes is directly inserted between the conductive layer 176 within the bottom of opening 168, and directly do not insert between the dielectric layer 172 within the opening 168.Dielectric layer within the opening 174 directly covers the buried layer 166 of doping.
Figure 17 has described an execution mode, wherein, uses single mask can form dark isolation and shallow isolation.As example, use the technology identical to form present embodiment with Figure 16, difference is, no longer forms conductive polycrystalline silicon structure 176, but forms another dielectric layer 178, thereby the dark dielectric isolation of downward arrival semiconductor substrate 162 is provided.Thus, Figure 17 buried layer 166, wide opening 168, narrow opening 170, dielectric spacers 172, dielectric plug (STI) 174 and dielectric layer 178 of having described semiconductor substrate 162, epitaxial loayer 164, having injected.In the first half office of epitaxial loayer 164, dielectric spacers 172 and dielectric layer 178 have constituted the isolation of broad together, and dielectric layer 178 has constituted narrower isolation in the Lower Half office of epitaxial loayer 164 and within semiconductor substrate 162.Dielectric layer 178 provides thus round the darker isolation of the buried layer 166 that injects.Buried layer 166 directly inserted be formed at the dielectric layer 178 within the opening 168 and be formed between the dielectric layer 174 within the opening 170, directly cover the buried layer 166 that mixes.The dielectric of use as the oxide can obtain compacter isolation, for example, because when using dielectric, can not form depletion layer in the semiconductor regions.When using polysilicon (in Figure 16 176 in), formed PN junction, these PN junctions can produce depletion layer, and these depletion layers may require bigger lateral separation.
Figure 18-24 has described an execution mode, is used to form a kind of integrated trench capacitor structure, and this structure comprises: the dark isolation, this dark isolation is what to form in the groove of broad with dielectric; STI, this STI form in more shallow groove with dielectric; And the polysilicon capacitor plate, these plates can be to form with the anisotropy polysilicon etching behind oxide, polysilicon, oxidate and the polysilicon deposition alternately in the groove of broad.These materials are exemplary, and also can use different or other material (such as silicide).
In exemplary execution mode, a kind of structure is provided, this structure comprises semiconductor substrate 180 and epitaxial loayer 182.Mask 184 (such as photoresist) with patterning carries out etching to hard mask (such as the oxide that is compacted), thereby the hard mask 186 of patterning is provided.The hard mask 186 of patterning can comprise as three openings shown in 18, i.e. first opening 188, second opening 190 (wideer than first opening 188) and the 3rd opening 192 (wideer than first opening 188 and second opening 190).In the execution mode of being described, first opening 188 is that two arbitrary units are so wide, and second opening 190 is that four units are so wide, and the 3rd opening 192 is that seven units are so wide.The width of three openings is exemplary.
After the structure that forms Figure 18, carry out first etching of the epitaxial loayer 182 that exposes, thereby these three openings are transferred to epitaxial loayer 182 from the hard mask 186 of patterning, such as shown in Figure 19.At this moment, can carry out the optional doping of the epitaxial loayer 182 that exposes.Next, formed first conformal dielectric layer 194, such as silica or silicon nitride.In the present embodiment, first conformal dielectric layer 194 is that a unit is so thick, thereby touches oneself in first opening 188, but does not touch oneself in second opening 190 or the 3rd opening 192, and is such as shown in Figure 19.The thickness of this layer can be greater than half of the width of first opening 188, but less than half of the width of second opening 190, thereby avoid the open centre place that excessive sedimentation is arranged.
Next, remove the structure that dielectric layer 194 obtains Figure 20 thereby the vertical anisotropy second of execution is etched with, this second etching is optionally for the hard mask 186 and the epitaxial loayer 182 of patterning.This vertical anisotropic etching has formed dielectric spacers 200 in second opening 190 and the 3rd opening, and has formed in first opening 188 the dielectric plug 202 of shallow trench isolation from (STI) can be provided.At this moment, also can in the epitaxial loayer 182 that exposes, carry out optional doping.Should be noted that, can form a plurality of parts (drain electrode such as lateral dmos device structure is extended) of multiple device architecture, perhaps can control the parasitic fields threshold region with it with this doping.This doping also can be the part of above-mentioned isolation scheme.
Next, be etched with and remove the structure that epitaxial loayer 182 and semiconductor substrate 180 obtain Figure 21 thereby carry out vertical anisotropy the 3rd, the 3rd etching is optionally for hard mask 186, dielectric spacers 200 and dielectric plug 202.
After forming the structure similar to Figure 21, form conformal dielectric layer 220 and formed conformal conductive layer 222 then, they all are that a unit is so thick, as shown in Figure 22.Conformal dielectric layer 220 touches oneself in second opening 190, but does not touch oneself in the 3rd opening 192.For example, layer 220 can comprise one or more dielectric layers, and conductive layer 222 can comprise one or more polysilicon layers and/or metal level.
Next, can be etched with the sept 230 that forms conduction to conformal conductive layer 222, this etching is optionally for dielectric layer 220, just as shown in Figure 23.Then, can make dielectric layer 220 downward levelings, thereby in opening 190, form dielectric plug 234 to hard mask 186.In alternative embodiment, can carry out single etch, conductive layer 222 and dielectric layer 220 have been removed in this etching, only otherwise dielectric 200 and 202 is etched under the bottom surface level of hard mask 186 just passable.Next, formed another dielectric layer (such as high-quality capacitor dielectric 232), as shown in Figure 23.The thickness of this dielectric layer 232 can be a unit, thereby 192 places, position touch oneself in remaining opening.
Next, for example,, make the structure leveling of Figure 23, to produce the structure of Figure 24 by using chemico-mechanical polishing (CMP) technology.
In the processing procedure of Figure 18-24, only used the photoresist mask layer 184 of a patterning to form as shown in figure 24 following array structure: sti structure is made of the plug 202 at opening 188 places; Broad and darker isolation structure are made of the dielectric spacers 200 and the dielectric plug 234 at opening 190 places; And capacitor, this capacitor is included in two conductive plates 230 and the capacitor dielectric 232 at opening 192 places.First dielectric layer has constituted in the dielectric spacers 200 at 190 and 192 places and at the dielectric plug 202 at 188 places.Second dielectric layer has constituted dielectric plug 234 and dielectric medium structure 220, and the 3rd dielectric layer has constituted the capacitor dielectric 232 at 192 places in the position.Should be noted that,, may need independent patterned etch according to the shape of opening 192, thus with layer 222 (Figure 22) be divided into a plurality of independent condenser armatures (230, Figure 24).Opening 192 can form a kind of closed figure (such as rectangle) that is when observing from the top, in this example, thereby can carry out etching to the end of this layer conductor 222 is divided into a plurality of independent parts 230.Figure 25 has described a kind of alternative processing procedure, and is very similar to the employed processing procedure of structure that forms Figure 24.In this processing procedure, after conductive layer 222 being etched with formation conductive spacer 230 shown in Figure 23, expose semiconductor substrate 180 thereby can carry out etching to the dielectric layer 220 of Figure 22.This processing procedure continues according to the processing procedure that structure is used that forms Figure 24.In the present embodiment, thereby can form dielectric spacers 250 at the conformal dielectric layer 220 of bottom etching Figure 22 of opening 192, and the capacitor dielectric 232 of Figure 23 can physically touch semiconductor substrate 180, as shown in the capacitor dielectric 252 of Figure 25.
The various aspects of one or more execution modes can comprise following element.
Typical narrow groove can have and is about 0.1 to the magnitude that is about 1 micron, thereby realizes 0.5 to 10 micron the degree of depth.By using suitable groove etch tool, up to 10: 1 or bigger length-width ratio be possible.
Usually, in narrow groove, touch dielectric thickness own and that in wide groove, do not touch oneself and be about about 2.5 times to about 4.0 times of narrow groove width, and less than half of the width of wide groove.
The width of the groove of broad usually will be greater than about 2.5 times of the dielectric thickness that touches oneself in narrow groove.For example, for 0.5 micron narrow groove, dielectric should be at least about 0.3 to being about 0.4 micron thickness, thereby fills up narrow groove and do not stay the gap.Therefore, the groove of broad should be greater than 2.5 times of the oxide that is deposited, perhaps greater than about 0.9 micron.
Can form narrow-shallow trench and wide-deep trench simultaneously with single mask.
Thereby these grooves can be filled the connection, the knot that serve as " dark-base stage " horizontal-positive-negative-positive structure with the polysilicon that mixes and be isolated, absorb the utmost point and knot.
Can only use a mask to form deep trench isolation and shallow trench isolation from (STI).
By using a kind of processing procedure, deep trench can be filled with oxide or be filled with polysilicon, this processing procedure has also formed oxide side walls on the top of this groove.
Can use to have the etched oxide/polysilicon that replaces of anisotropy polysilicon/oxidate, be integrated with the capacitor that groove flows with formation.
In the execution mode and other execution mode of Figure 18-24, these openings can comprise three (or more a plurality of) grooves with different in width.Three (or more a plurality of) grooves with three kinds of (or more kinds of) width can constitute the opening that has three kinds of (or more kinds of) degree of depth with formation with single mask.For example, the structure of Figure 21 can form according to above-mentioned processing procedure, and above-mentioned processing procedure has used first to be etched with bottom 182 is carried out etching, thereby forms first groove 188, second groove 190 and the 3rd groove, has arrived first degree of depth.Second groove 190 and the 3rd groove 192 are passed in second etching, at the second groove place and the 3rd groove place bottom are carried out etching, arrive second degree of depth darker than first degree of depth.Second groove has also formed plug 202 and the sept 200 in second groove 190 and the 3rd groove 192 in first groove.
After the structure that forms Figure 21, can then continue above-mentioned processing procedure, as shown in Figure 26-30.As shown in figure 26, formed second conforma layer 260 (such as dielectric layer).Second conforma layer 260 is formed on the plug 202 in first opening 188, ownly makes second opening 190 fill up dielectric thereby touch in second opening 190, and is conformally formed in the 3rd opening 192.
Next, the structure of Figure 26 is carried out the 3rd etching.The 3rd etching is carried out etching by the 3rd groove to the bottom 180,182 that exposes, thereby produces and similar structure shown in Figure 27.Etching second conforma layer is to form second plug 270 and form sept 272 in the 3rd opening 192 in second groove 190.192 places continue this etching at the 3rd groove, to carry out etching by 192 pairs of epitaxial loayers 182 of the 3rd groove and semiconductor substrate 180.This etching makes the 3rd groove darker, reaches three degree of depth darker than first and second degree of depth.
According to specific purposes, this processing procedure can continue.For example, can form the 3rd conforma layer 280 shown in Figure 28, its thickness is enough to touch oneself in the 3rd groove 192, and the 3rd conforma layer 280 also is formed on first plug 202 and second plug 270.The upper surface of structure that can etching Figure 28 and stopping on the hard mask 186, such as shown in Figure 9, thus in the 3rd groove 192, produce the 3rd plug 290.Can further continue this and be etched with the structure of removing hard mask 196 and producing Figure 30.
Thus, this processing procedure can form: first opening 188, and it has first degree of depth that is positioned at bottom 182; Second opening 190, it has second degree of depth darker than first degree of depth; And the 3rd opening 192, it is all darker than first and second degree of depth.Three kinds of openings in the bottom have three kinds of different degree of depth, but all are to form by the mask that uses a patterning.Should be appreciated that,, can form the different groove widths and the degree of depth of any number by using the variant of this processing procedure.Various other combinations also are expected.
Thus, the embodiments of the present invention can reduce the number of times of masks required in the process of making semiconductor device.But use fewer purpose mask simplified manufacturing technique, productivity gain reduces the circulation time of wafer and equipment cost and manufacturing, therefore, has reduced to produce the cost of the semiconductor device of finishing.Can form isolation structure, the absorption utmost point and the employed dark base diffusion of lateral PNP transistor (for example, being used to form dark collector and emitter zone) of layer region on earth with embodiments of the present invention.Can in making the process of various semiconductor device, form these structures, for example, be used for the integrated circuit technique of power management and simulation application or the like.Can use various technology to form these devices, for example, bipolar complementary metal oxide semiconductor (BiCMOS) technology, BIPOLAR technology, complementary bipolar (CBIP) technology, complementary MOS (CMOS) technology, bilateral diffusion MOS (DMOS) technology, complementary double diffusion (CDMOS) technology etc.
In the specific execution mode shown in the block diagram of Figure 31, electronic system 310 can comprise power supply 312, and this power supply can be AC power supplies or the DC power supply (such as DC power supply or battery) through conversion.System 310 also can comprise processor 314, processor 314 can be in microprocessor, microcontroller, flush bonding processor, the digital signal processor one or more or above-mentioned in two or more combinations.Processor 314 can be electrically coupled to memory 318 by bus 316.Bus 316 can be one or more in following or some the combination in them: the bus on the chip (or integrated circuit), such as advanced microprocessor bus architecture (AMBA); The bus that chip is outer is such as Peripheral component interface (PCI) bus; Or quick (PCIe) bus of PCI.Memory 318 can be one or more in following or some the combination in them: static RAM; Dynamic random access memory; Can be with read-only memory; Flash memory.Processor 314, bus 316 and memory 318 are incorporated in one or more integrated circuits and/or other parts.Electronic system 310 can comprise other device 320 (such as other semiconductor device or comprise the subsystem of semiconductor device), and can be coupled to processor 314 by bus 322.In processor 314, memory 318 and/or other device 320 any or all can be powered by power supply 312.As the part of electronic system 310 and the semiconductor device that is comprised or with electronic system 310 interactive semiconductor device in any or all can comprise one or more execution mode of the present invention.Electronic system can comprise and telecommunications, auto industry, semiconductor test and manufacturing equipment, consumer electronics device or almost any consumer or industrial electrical equipment associated device.
Though being used to illustrate the number range and the parameter of broad range of the present invention all is approximation, illustrated numerical value is all as far as possible accurately reported in the concrete example.Yet any numerical value all can comprise some error, this be the standard deviation found in its thermometrically process must cause.In addition, all scopes disclosed herein all should be understood as that and comprise any and all belong to wherein subrange.In addition, " less than 10 " this scope can comprise any and all subranges between minimum value of zero and maximum 10, that is, any and minimum values all subranges are equal to or greater than zero and maximum is equal to or less than 10, for example, and 1 to 5.In some cases, the numerical value claimed of parameter can be got negative value.In this case, the example value of " less than 10 " this scope can adopt negative value, for example, and-1 ,-2 ,-3 ,-10 ,-20 ,-30 etc.
Although show the present invention with respect to one or more implementations, under the situation that does not deviate from the spirit and scope of the present invention, can make various modifications and/or variation to shown example.In addition, although special characteristic of the present invention may only be to disclose in conjunction with one in some implementations, but this feature can combine with one or more further features of other implementation if needed and useful to any given or specific function.In addition, term " comprises ", " having ", " having " or its variant are used in specification and claims, and being intended to is pardon.Term " at least one " be used to mean one or more in lising can be selected.In addition, in above-mentioned discussion and claims, with respect to two employed terms of material " on ", one another " on " mean certain contact at least arranged between the material, and " top " mean described material near but might have one or more extra intermediate materials to make that contact is possible but optional." on " or " top " do not refer to any directivity in this article.A kind of coating material described in term " conformal ", and conformal material has kept the angle of primer.Term " about " is meant that listed numerical value can change a little, as long as this change can not make processing procedure or structure and illustrated embodiment inconsistent just passable.At last, " exemplary " is meant that this description as the example use, is desirable but not mean it.For those of ordinary skills, consider content disclosed herein, other execution mode of the present invention will be tangible.Specification and example are intended to be regarded as exemplary, and true scope of the present invention and spirit are indicated by claims.
The term of the relative position of Shi Yonging is based on that the plane of the conventional plane that is parallel to wafer or substrate or working surface defines in this application, no matter the orientation of wafer or substrate how.The term of Shi Yonging " level " or " laterally " are based on that the plane of the conventional plane that is parallel to wafer or substrate or working surface defines in this application, no matter the orientation of wafer or substrate how.Term " vertically " is meant the direction perpendicular with level.Term " on ", " side " (as in " sidewall "), " higher ", " lower ", " top ", " top " and " under " define with respect to conventional plane or working surface on the end face of wafer or substrate, no matter the orientation of wafer or substrate is how.
Claims (10)
1. employed method in forming the process of semiconductor device comprises:
Form mask on the upper surface of a bottom, wherein, described mask comprises and is positioned at first opening among the described mask and is positioned at second opening among the described mask that wherein, first aperture efficiency, second opening is wide;
By first and second openings described bottom is carried out etching, have first groove of first width and form second groove with second width in described bottom to form in described bottom, wherein, first groove is wideer than second groove;
Forming a conforma layer on the described bottom and within first and second grooves, wherein, described conforma layer does not touch oneself in first groove, but touches own in second groove;
Under the situation that conforma layer in first and second grooves exposes, described conforma layer is carried out etching so that described bottom exposes at the first groove place with second etching, wherein, during second etching, described bottom does not expose at the second groove place; And
Under the situation that conforma layer in second groove exposes, with the 3rd etching described bottom is etched with the degree of depth that increases first groove, wherein, after carrying out the 3rd etching, first groove is darker than second groove.
2. the method for claim 1 is characterized in that,
Described conforma layer is first conformal dielectric layer, and described method also comprises:
Forming second conformal dielectric layer within first groove and on second groove;
Within first groove, forming a conformal conductive layer on second conformal dielectric layer and on second groove;
Described conformal electrically conductive layers is carried out anisotropic etching, and to form first current-carrying part and second current-carrying part, wherein, first and second current-carrying parts are electrically isolated from one; And
Form capacitor dielectric between first and second current-carrying parts, wherein, first current-carrying part is first plate of capacitor, and second current-carrying part is second plate of capacitor, and capacitor dielectric is the capacitor dielectric of described capacitor.
3. the method for claim 1 is characterized in that,
Described conforma layer is first conformal electrically conductive layers, and described method also comprises:
In the 3rd etching process, from described first conformal electrically conductive layers, form conductive spacer; And
After carrying out the 3rd etching, within first groove, form second conformal electrically conductive layers, wherein, first conformal electrically conductive layers in second groove prevents to form second conformal electrically conductive layers in second groove.
4. one kind comprises employed method in the process of semiconductor device of lateral bipolar transistor in formation, and described method comprises:
On semiconductor substrate, form a mask layer, wherein, described mask layer comprises first, second and the 3rd opening and the 4th and the 5th opening, first, second and the 3rd opening all have first width, the the 4th and the 5th opening all has second width wideer than first width, and these openings expose described semiconductor substrate;
By each opening described semiconductor substrate is carried out etching and is etched to first degree of depth, in described semiconductor substrate, to form the first, second, third, fourth and the 5th groove;
Within each groove, form conforma layer, make described conforma layer within first, second and the 3rd groove, touch own and within the 4th and the 5th groove, do not touch oneself;
Described conforma layer is carried out anisotropic etching, so that described semiconductor substrate exposes at the 4th and the 5th groove place, wherein, this anisotropic etching does not make described semiconductor substrate expose at first, second and the 3rd groove place;
After described conforma layer is carried out anisotropic etching, described semiconductor substrate is carried out etching and be etched to second degree of depth darker than first degree of depth by the 4th and the 5th groove; And
Within each groove, form conductive layer, wherein, conductive layer within first and second grooves is adapted the collector electrode that serves as lateral bipolar transistor, conductive layer within the 3rd groove is adapted the emitter that serves as lateral bipolar transistor, and the conductive layer and second conforma layer within the 4th and the 5th groove are adapted the device isolation structure that serves as lateral bipolar transistor.
5. method as claimed in claim 4 also comprises:
After described conforma layer is carried out anisotropic etching, remove described conforma layer from the 4th groove and from the 5th groove.
6. method as claimed in claim 5 is characterized in that,
Forming conductive layer within each groove comprises:
Make conductive layer be formed up to a thickness, this thickness is enough to make conductive layer to touch oneself within each groove; And
On the upper surface of semiconductor substrate, remove conductive layer and conductive layer is stayed within each groove.
7. lateral bipolar transistor comprises:
Semiconductor substrate, described semiconductor substrate comprises first, second and the 3rd opening and the 4th and the 5th opening at least, first, second and the 3rd opening all have first width and first degree of depth, the 4th and the 5th opening all have than wide second width of first width and than first degree of depth dark second degree of depth; And
Conductive layer within each opening, wherein, conductive layer within each opening comprises same conductive layer, wherein, conductive layer within first and second openings is adapted the collector electrode that serves as lateral bipolar transistor, conductive layer within the 3rd opening is adapted the emitter that serves as lateral bipolar transistor, and the conductive layer within the 4th and the 5th opening is adapted the device isolation structure that serves as lateral bipolar transistor.
8. lateral bipolar transistor as claimed in claim 7 also comprises:
Doping buried layer within semiconductor substrate, wherein, conductive layer in first, second and the 3rd opening covers above the doping buried layer, described doping buried layer is directly inserted between the conductive layer in the 4th and the 5th opening, and described doping buried layer is not directly inserted between the conductive layer in the 4th and the 5th opening.
9. semiconductor device comprises:
Semiconductor substrate has at least one first opening in described semiconductor substrate, wherein, described at least one first opening comprises first width, first degree of depth, upper and lower;
Described semiconductor substrate is included at least one second opening in the described semiconductor substrate, and wherein, described at least one second opening comprises second width and second degree of depth, and wherein, first width is wideer than second width, and it is dark that first depth ratio, second degree of depth is wanted;
Ground floor within described at least one first opening and described at least one second opening, wherein, described ground floor is filled described at least one second opening and is not filled described at least one first opening, and described ground floor is positioned at the top of described at least one first opening and is not positioned at the bottom of described at least one first opening; And
At the second layer within described at least one second opening within described at least one first opening and not, wherein, the described second layer is positioned at the top of described at least one first opening and the bottom of described at least one first opening.
10. employed method in forming the process of semiconductor device comprises:
On a bottom, form the mask of patterning, the mask of described patterning has first opening, second opening and the 3rd opening, described first opening has first width, described second opening has second width wideer than first width, and described the 3rd opening has three width wideer than second width;
Described bottom is carried out etching and be etched to first degree of depth by first opening to be formed on first groove in the described bottom, by second opening described bottom is etched with second groove that is formed in the described bottom, and described bottom is etched with the 3rd groove that is formed in the described bottom by the 3rd opening;
Form first conforma layer on described bottom, wherein, first conforma layer touches oneself within first groove, and be conformally formed in second groove with the 3rd groove in;
First conforma layer is etched with in first groove forms first plug and in second groove He in the 3rd groove, form sept, and, described bottom is carried out etching and is etched to second degree of depth darker than first degree of depth by second groove and by the 3rd groove;
Form second conforma layer on described bottom, wherein, second conforma layer is to be formed on described first plug, touches oneself in second groove, and is conformally formed in the 3rd groove; And
Second conforma layer is carried out etching, in second groove, forming second plug and in the 3rd groove, to form sept, and, described bottom is carried out etching and be etched to three degree of depth darker by the 3rd groove than second degree of depth.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26104309P | 2009-11-13 | 2009-11-13 | |
| US61/261,043 | 2009-11-13 | ||
| US12/794,236 | 2010-06-04 | ||
| US12/794,236 US20110115047A1 (en) | 2009-11-13 | 2010-06-04 | Semiconductor process using mask openings of varying widths to form two or more device structures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102064129A true CN102064129A (en) | 2011-05-18 |
Family
ID=43999345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105541778A Pending CN102064129A (en) | 2009-11-13 | 2010-11-11 | Semiconductor process using mask openings of varying widths to form two or more device structures |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102064129A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456675A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure manufacturing method and semiconductor device |
| CN104183534A (en) * | 2013-05-27 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench |
| CN105914179A (en) * | 2016-06-24 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | LDMOS STI structure and process method |
| CN107258019A (en) * | 2015-07-09 | 2017-10-17 | 达尔科技股份有限公司 | The double groove devices of autoregistration |
| CN110223926A (en) * | 2019-06-25 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN110752149A (en) * | 2019-09-18 | 2020-02-04 | 珠海格力电器股份有限公司 | Power device processing method |
| CN113169046A (en) * | 2018-12-14 | 2021-07-23 | 应用材料股份有限公司 | Technique and apparatus for unidirectional aperture extension using angled ion beam |
| WO2022057338A1 (en) * | 2020-09-18 | 2022-03-24 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure and semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020072984A (en) * | 2001-03-14 | 2002-09-19 | 삼성전자 주식회사 | Different size trenches and method of forming the same |
| US6989317B1 (en) * | 2004-10-22 | 2006-01-24 | International Business Machines Corporation | Trench formation in semiconductor integrated circuits (ICs) |
| CN1866508A (en) * | 2005-05-20 | 2006-11-22 | 半导体元件工业有限责任公司 | Semiconductor device having trench structures and manufacturing method thereof |
| CN101425449A (en) * | 2007-11-01 | 2009-05-06 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor substrate, semiconductor device and electronic device |
-
2010
- 2010-11-11 CN CN2010105541778A patent/CN102064129A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020072984A (en) * | 2001-03-14 | 2002-09-19 | 삼성전자 주식회사 | Different size trenches and method of forming the same |
| US6989317B1 (en) * | 2004-10-22 | 2006-01-24 | International Business Machines Corporation | Trench formation in semiconductor integrated circuits (ICs) |
| CN1866508A (en) * | 2005-05-20 | 2006-11-22 | 半导体元件工业有限责任公司 | Semiconductor device having trench structures and manufacturing method thereof |
| CN101425449A (en) * | 2007-11-01 | 2009-05-06 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor substrate, semiconductor device and electronic device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456675A (en) * | 2012-06-05 | 2013-12-18 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure manufacturing method and semiconductor device |
| CN104183534A (en) * | 2013-05-27 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench |
| CN104183534B (en) * | 2013-05-27 | 2017-05-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing shallow trench |
| CN107258019A (en) * | 2015-07-09 | 2017-10-17 | 达尔科技股份有限公司 | The double groove devices of autoregistration |
| CN105914179A (en) * | 2016-06-24 | 2016-08-31 | 上海华虹宏力半导体制造有限公司 | LDMOS STI structure and process method |
| CN113169046A (en) * | 2018-12-14 | 2021-07-23 | 应用材料股份有限公司 | Technique and apparatus for unidirectional aperture extension using angled ion beam |
| CN113169046B (en) * | 2018-12-14 | 2024-05-07 | 应用材料股份有限公司 | Method of patterning a substrate and apparatus for patterning a substrate |
| CN110223926A (en) * | 2019-06-25 | 2019-09-10 | 武汉新芯集成电路制造有限公司 | A kind of semiconductor devices and its manufacturing method |
| CN110752149A (en) * | 2019-09-18 | 2020-02-04 | 珠海格力电器股份有限公司 | Power device processing method |
| WO2022057338A1 (en) * | 2020-09-18 | 2022-03-24 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure and semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101178970B1 (en) | A semiconductor process using mask openings of varying widths to form two or more device structures | |
| CN102064129A (en) | Semiconductor process using mask openings of varying widths to form two or more device structures | |
| US8148784B2 (en) | Semiconductor device having first and second device isolation layers formed of different insulation materials | |
| EP1065710B1 (en) | Semiconductor device having a trench gate and method of manufacturing the same | |
| KR100745917B1 (en) | Method for fabricating semiconductor device | |
| US20160211348A1 (en) | Trench lateral diffusion metal oxide semiconductor device and manufacturing method of the same | |
| CN103378153A (en) | Structure and method for finfet integrated with capacitor | |
| CN104412365B (en) | With the sinker area for reducing width | |
| US9397092B2 (en) | Semiconductor device in a semiconductor substrate and method of manufacturing a semiconductor device in a semiconductor substrate | |
| CN110957318A (en) | Semiconductor structure and manufacturing method thereof | |
| CN108400166B (en) | Power transistor with terminal trenches in terminal reduced surface electric field region | |
| US20190088643A1 (en) | Three dimensional memory device and method for fabricating the same | |
| CN113130649A (en) | LDMOS device and preparation method thereof | |
| US10403725B2 (en) | Method for processing a semiconductor workpiece and semiconductor device | |
| JP5838529B1 (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN209963062U (en) | Semiconductor structure and semiconductor device | |
| US5998266A (en) | Method of forming a semiconductor structure having laterally merged body layer | |
| KR101076565B1 (en) | High integrated mos device and the manufacturing method thereof | |
| CN113327860B (en) | Manufacturing method of shielded gate trench type MOS device | |
| US7790564B2 (en) | Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations | |
| US7709926B2 (en) | Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit | |
| US7714382B2 (en) | Trench gate semiconductor with NPN junctions beneath shallow trench isolation structures | |
| CN210403736U (en) | SGT device | |
| KR101057696B1 (en) | Manufacturing method of bipolar transistor | |
| JP3602242B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110518 |