CN102063265A - Memory device and memory controller for accessing non-volatile memory - Google Patents
Memory device and memory controller for accessing non-volatile memory Download PDFInfo
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- CN102063265A CN102063265A CN2009102264060A CN200910226406A CN102063265A CN 102063265 A CN102063265 A CN 102063265A CN 2009102264060 A CN2009102264060 A CN 2009102264060A CN 200910226406 A CN200910226406 A CN 200910226406A CN 102063265 A CN102063265 A CN 102063265A
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Abstract
The invention discloses a memory device and a memory controller for accessing a non-volatile memory. The memory controller is coupled to the non-volatile memory and is used for accessing the non-volatile memory; and the memory controller and the non-volatile memory are respectively arranged in two independent chips; and when an external data is about to be written into the non-volatile memory, the memory controller compresses the external data and memorizes the compressed external data in the non-volatile memory.
Description
Technical field
The relevant a kind of memory storage of the present invention refers to a kind ofly can be initiatively the outside be write a memory storage that data compress and a Memory Controller that is used for access one non-volatility memorizer especially.
Background technology
In general flash memory, erase (erase) of its each block is conditional with writing (write) number of times, that is, if the number of times of erasing and writing of a block surpasses certain value (for example 100,000 times), then this block probably can be damaged, and causes flash memory can't continue to use.Therefore, in order to prolong the life-span of flash memory, generally can use a kind of on average smear to write store block techniques (wear-leveling) and will write to each block in the flash memory or other similar algorithms fifty-fifty from the data of outside.Yet, though above-mentioned algorithm can reach the effect that prolongs flash memory, how further to reduce erasing and writing indegree of block in the flash memory to prolong the life-span of flash memory, be still an important problem.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of and can be initiatively the outside be write a memory storage that data compress and a Memory Controller that is used for access one non-volatility memorizer, to solve the above problems.
A kind of memory storage that provides according to one aspect of the present invention, include a non-volatility memorizer and a Memory Controller, wherein this Memory Controller is coupled to this non-volatility memorizer, and be used for this non-volatility memorizer of access, and this Memory Controller and this non-volatility memorizer are to be arranged at two respectively independently in the chip; When an external data desired to write to this non-volatility memorizer, this Memory Controller compressed this external data, and the external data after will compressing is stored in this non-volatility memorizer.
Provide a kind of Memory Controller that is used for access one non-volatility memorizer on the other hand according to the present invention, wherein this Memory Controller and this non-volatility memorizer are to be arranged at two respectively independently in the chip, and this Memory Controller includes a compression/decompression processes device.This compression/de-compression device is to be used for an external data is compressed, and the external data after will compressing is stored to this non-volatility memorizer.
According to a kind of memory storage of providing of another aspect of the invention, include a non-volatility memorizer, a Memory Controller and a compression/decompression processes device.This non-volatility memorizer is to be arranged in one first chip; This Memory Controller is coupled to this non-volatility memorizer, and is used for this non-volatility memorizer of access (Access); This compression/decompression processes device couples this Memory Controller, and wherein this Memory Controller and this compression/decompression processes device are to be arranged in one second chip, and this second chip is to be different from this first chip.When an external data desired to write to this non-volatility memorizer, this compression/decompression processes device compressed this external data, and the external data after will compressing is stored in this non-volatility memorizer by this Memory Controller.
According to memory storage of the present invention and Memory Controller, external data is just can be stored to after overcompression in the flash memory earlier, therefore, can reduce erasing and writing indegree of block in the flash memory, and then prolong the life-span of flash memory.
Description of drawings
Fig. 1 is the synoptic diagram according to the memory storage of the present invention one first embodiment.
Fig. 2 is the synoptic diagram according to the memory storage of the present invention one second embodiment.
Embodiment
Please refer to Fig. 1, Fig. 1 is the synoptic diagram according to the memory storage 100 of the present invention one first embodiment.As shown in Figure 1, memory storage 100 includes an interface circuit 110, a physical layer (physical layer) treating apparatus 121, an interface controller 122, a bus 123, a storer 124, a processor 125 and a flash memory control 126 and a non-volatility memorizer (be in the present embodiment be example with flash memory circuit 130), and wherein flash memory control 126 includes a compression/decompression processes device 128.In addition, interface circuit 110 can be serial advanced technology attachment device (Serial Advanced Technology Attachment, SATA) interface, USB (universal serial bus) (Universal Serial Bus, USB) interface or peripheral cell interconnection (Peripheral Component Interconnect Express, PCIE) interface one of them, also can be in conjunction with USB and SATA interface, or the combination in any of USB, SATA and PCIE interface; In addition, physical layer treating apparatus 121 can adopt SATA, USB or PCIE physical layer treating apparatus according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE physical layer treating apparatus; And interface controller 122 can also adopt SATA, USB or PCIE interface controller according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE interface controller; Memory storage 100 can be a portable memory device, and can link with the interface socket 150 in the host computer 140.In addition, flash memory circuit 130 be arranged at least one first chip (that is, flash memory circuit 130 can be one or more chips), and physical layer treating apparatus 121, interface controller 122, bus 123, storer 124, processor 125 and flash memory control 126 are to be arranged in one second chip, and this second chip is respectively independently chip with this first chip at least.
After memory storage 100 and host computer 140 link, and when host computer 140 desires write to data in the flash memory circuit 130, at first, data-signal can be sent to these data in the flash memory control 126 by bus 123 by interface circuit 110, physical layer treating apparatus 121 and interface controller 122 earlier.
Then, receive the external data that transmits by bus 123 when flash memory control 126 after, 128 pairs of received external datas of compression/decompression processes device are compressed, the external data after will compressing again afterwards is stored to flash memory circuit 130.In other words, the data that sent from host computer 140 are just can be stored to the flash memory circuit 130 through overcompression earlier, thus, the data volume that is stored in the flash memory circuit 130 will reduce, and then reducing erasing and writing indegree of block in the flash memory circuit 130, therefore the life-span of flash memory circuit 130 also prolongs.
Specifically, in traditional memory storage, external data is directly to be sent to flash memory circuit by flash memory control, suppose that memory storage receives the data of 1K hyte (byte), and each cycle of memory storage (cycle) is handled 1 hyte data,, to flash memory circuit, and the data volume that is stored in the flash memory circuit is the 1K hyte to the data processing that then traditional memory storage need carry out 1024 cycles with data storing.Compared to traditional memory storage, compression/decompression processes device 128 in the flash controller 126 of the present invention can be with received 1K hyte data, dynamic compression is N hyte data, N＜1024 wherein, afterwards, in real time through N all after date, with N hyte data storing to flash memory circuit 1130.
Be noted that compression/de-compression controller 128 can be desired all to write the data of flash memory circuit 130 and compress, and the data after will compressing enter in the flash memory circuit 130; Or only compress at partial data, and the not packed data of data after the compression partly and part is write in the flash memory circuit 130, the variation in these designs all should be under the jurisdiction of category of the present invention.
In addition, in the present embodiment, after 128 pairs of data of compression/de-compression controller are compressed, can directly the data after the compression be deposited in to flash memory circuit 130, compression back data can also be stored to storer 124 earlier, will be stored in the compression in the storer 124 afterwards again after data be sent in the flash memory circuit 130.
On the other hand, after memory storage 100 and host computer 140 link, and when host computer 140 desires to read a internal data in the flash memory circuit 130, compression/de-compression controller 128 can decompress to this internal data, and the internal data after will decompressing exports host computer 140 to.
Specifically, in the flow process that decompresses, when flash memory control 126 receive one read the order of internal data in the flash memory circuit 130 after, suppose that the required data volume that reads is that (data volume that in fact is stored in the flash memory circuit 130 is the N hyte to the 1K hyte, and N＜1024), after then passing through N the cycle (cycle), compression/de-compression controller 128 can will be stored in N hyte material in the flash memory circuit 130 decompress operation and and be stored in the storer 124, at this moment, the data volume that is stored in the storer 124 is the 1K hyte.In addition, be stored in the process of storer 124 by flash memory control 126 in internal data, compression/decompression processes device 128 can dynamically go the data in the access memory 124, and the data after will decompressing reach interface controller 122 by bus 123, wherein compression/decompression processes device 128 transmission data to the time of interface controller 122 is the cycle of 1K, and data volume is the 1K hyte.
Please refer to Fig. 2, Fig. 2 is the synoptic diagram according to the memory storage 200 of the present invention one second embodiment.As shown in Figure 2, memory storage 200 includes an interface circuit 210, a physical layer (physical layer) treating apparatus 221, an interface controller 222, a bus 223, a storer 224, a processor 225 and a flash memory control 226, a compression/decompression processes device 228 and a non-volatility memorizer (be in the present embodiment be example with flash memory circuit 230).In addition, interface circuit 210 can for SATA interface, USB interface or PCIE interface wherein one, also can be in conjunction with USB and SATA interface, or the combination in any of USB, SATA and PCIE interface; In addition, physical layer treating apparatus 221 can adopt SATA, USB or PCIE physical layer treating apparatus according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE physical layer treating apparatus; And interface controller 222 can also adopt SATA, USB or PCIE interface controller according to the specification of interface circuit, or the combination in any of USB, SATA and PCIE interface controller; Memory storage 200 can be a portable memory device, and can link with the interface socket 250 in the host computer 240.In addition, flash memory circuit 230 be arranged at least one first chip (that is, flash memory 230 can be one or more chips), and physical layer treating apparatus 221, interface controller 222, bus 223, storer 224, processor 225 and flash memory control 226, compression/decompression processes device 228 are to be arranged in one second chip, and this second chip is respectively independently chip with this first chip at least.
Concise and to the point conclusion the present invention, according to memory storage of the present invention and flash memory control, external data is just can be stored in the flash memory circuit through after the compression of Memory Controller earlier, therefore, can reduce erasing and writing indegree of block in the flash memory circuit, and then prolong the life-span of flash memory circuit.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (12)
1. memory storage includes:
One non-volatility memorizer; And
One Memory Controller is coupled to this non-volatility memorizer, is used for this non-volatility memorizer of access, and wherein this Memory Controller and this non-volatility memorizer are to be arranged at two respectively independently in the chip;
Wherein when an external data desired to write to this non-volatility memorizer, this Memory Controller compressed this external data, and the external data after will compressing is stored in this non-volatility memorizer.
2. memory storage according to claim 1 is characterized in that, this non-volatility memorizer is a flash memory.
3. memory storage according to claim 1 is characterized in that, this Memory Controller compresses all external datas of desiring to write to this non-volatility memorizer, and the external data after will compressing is stored in this non-volatility memorizer.
4. memory storage according to claim 1 is characterized in that, when a main frame was desired to read in this non-volatility memorizer an internal data, this Memory Controller decompressed to this internal data, and the internal data after will decompressing exports this main frame to.
5. one kind is used for the Memory Controller of access one non-volatility memorizer, and wherein this Memory Controller and this non-volatility memorizer are to be arranged at two respectively independently in the chip, and this Memory Controller includes:
One compression/decompression processes device be used for an external data is compressed, and the external data after will compressing is stored to this non-volatility memorizer.
6. Memory Controller according to claim 5 is characterized in that, this non-volatility memorizer is a flash memory.
7. Memory Controller according to claim 5 is characterized in that, this compression/decompression processes device to all desire to write in this non-volatility memorizer external data compress, and the external data after will compressing exports this non-volatility memorizer to.
8. Memory Controller according to claim 5, it is characterized in that, when a main frame is desired to read in this non-volatility memorizer an internal data, this compression/decompression processes device reads this internal data, and this internal data is decompressed, and the internal data after will decompressing exports this main frame to.
9. memory storage includes:
One non-volatility memorizer is arranged in one first chip; And
One Memory Controller is coupled to this non-volatility memorizer, is used for this non-volatility memorizer of access;
One compression/decompression processes device couples this Memory Controller, and wherein this Memory Controller and this compression/decompression processes device are to be arranged in one second chip, and this second chip is to be different from this first chip;
Wherein when an external data desired to write to this non-volatility memorizer, this compression/decompression processes device compressed this external data, and the external data after will compressing is stored in this non-volatility memorizer by this Memory Controller.
10. memory storage according to claim 9 is characterized in that, this non-volatility memorizer is a flash memory.
11. memory storage according to claim 9 is characterized in that, this compression/decompression processes device compresses all external datas of desiring to write to this non-volatility memorizer, and the external data after will compressing is stored in this non-volatility memorizer.
12. memory storage according to claim 9, it is characterized in that, when a main frame was desired to read in this non-volatility memorizer an internal data, this compression/decompression processes device decompressed to this internal data, and the internal data after will decompressing exports this main frame to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2009102264060A CN102063265A (en) | 2009-11-17 | 2009-11-17 | Memory device and memory controller for accessing non-volatile memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009102264060A CN102063265A (en) | 2009-11-17 | 2009-11-17 | Memory device and memory controller for accessing non-volatile memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107277347A (en) * | 2012-11-23 | 2017-10-20 | 联发科技股份有限公司 | Data processing equipment and correlation technique |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107277347A (en) * | 2012-11-23 | 2017-10-20 | 联发科技股份有限公司 | Data processing equipment and correlation technique |
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Application publication date: 20110518 |