CN102055442B - Frequency locking method of multi-phase delay lock loop in full frequency width - Google Patents
Frequency locking method of multi-phase delay lock loop in full frequency width Download PDFInfo
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Abstract
The invention provides a multi-phase delay locking method in a full-frequency width operating range. The method comprises the following steps of: receiving a reference frequency signal by using a three-boundary phase detector, processing the signal and connecting the signal with a voltage control delay line; receiving two delay frequency signals one of which serves as a small delay frequency signal and the other serves as a large delay frequency signal in the delay frequency signal by using the three-boundary phase detector; comparing the reference frequency signal with the small delay frequency signal and the large delay frequency signal respectively to obtain a lead phase difference or a lag phase difference; and generating an Up pulse signal or a Down pulse signal which has the same width as the phase difference and serves as the delay time of each delay unit. After being locked, a plurality of phase signals averagely fall in a frequency period and the problem of fuzzy multi-locking can be solved simultaneously.
Description
The present invention is that the dividing an application of invention that application number is 200710163783.5 " the multiple phase delay-locked loop of frequency width and the method for locking frequency " by name starved on November 1st, 2007 application
Technical field
What the present invention relates to is a kind of multiple phase delay-locked loop, but particularly be a kind of multiple phase delay-locked loop of frequency width opereating specification.
Background technology
Along with the development of constantly bringing forth new ideas of the technology of CMOS (Complementary Metal Oxide Semiconductor) (CMOS), high speed processing speed and high density integrated circuit density are all constantly increasing.Therefore, the synchronous processing between modules be important problem, and become the bottleneck that integrated circuit ran in when development.
The high-order electronic circuit has tight demand to the system frequency signal source of a high speed and high-quality now.Yet, when system frequency signal source running during in high speed, because of frequency drives transmission delay time (propagation delay) or frequency plot mistake from the relevant issues that degree causes, but greatly affect system effectiveness and chip reliability.Therefore, in the high-order design of electronic circuits such as microprocessor, real-time system or data communication, just need to add the phase-locked loop (Phase-Locked Loop, PLL) of a tool low-voltage, high-frequency operation and low jitter amount (low jitter) with the characteristic revision auxiliary mechanism as incoming frequency signal source.
The phase-locked loop of CMOS (PLL) and delay-locked loop (Delay-Lock Loop, DLL) be that design is with solving the synchronous problem of circuit medium frequency, because difference is so that delay-locked loop is stable than the phase-locked loop on both structures, and in loop filter the less electric capacity of use.Because delay-locked loop designs and stable characteristic easily, there is being increasing application to bring into use delay-locked loop (DLL) to replace phase-locked loop (PLL) now, delay-locked loop also is widely used in for example frequency restoration and regional oscillator circuit than the phase-locked loop, and these can only use the phase-locked loop before being applied in.In addition, the in confused situation of its signal jitter of delay-locked loop (Jitter) shows, because noise is at voltage controlled delay line (Voltage-Controlled Delay Line, VCDL) can not accumulate through behind several frequency periods, so that delay-locked loop can be used as the ideal circuit unit that Frequency Synchronization is processed, it also can be used on the rf frequency combiner circuit and is connected with high speed serialization certainly.
General traditional delay-locked loop configuration diagram as shown in Figure 1, the signal of several phase retardations of output behind voltage controlled delay line (VCDL) 11 reception one reference frequency (Ref-Clk) signals, the signal of output is feedback and is inputed to phase detectors (phase detector, PD) 12, charge pump (charge pump, CP) 13 with loop filter (loop filter, LF) 14.The operation principles of delay-locked loop, namely be that reference frequency (Ref-Clk) signal with outside input utilizes Delay Element to produce voluntarily delay frequency (DLL-Clk) signal of many fixed skew, more sequentially with these frenquency signals by relatively whether it synchronous with former reference frequency (Ref-Clk) signal of outside behind the purpose function circuit.So, through the screening of control circuit, can select at last one and be used as blocked frenquency signal and finish the work of delay-locked loop to acceptable frenquency signal with the phase difference of former reference frequency signal is little.
Fig. 2 A is depicted as the situation of frequency (DLL-Clk) signal when frequency range AA ' internal ratio reference frequency (Ref-Clk) signal is leading that postpone, and makes two signals can be synchronously shown in Fig. 2 B through the running of delay-locked loop; Fig. 3 A is depicted as the situation of frequency (DLL-Clk) signal when frequency range BB ' internal ratio reference frequency (Ref-Clk) signal falls behind that postpone, and makes two signals can be synchronously shown in Fig. 3 B through the running of delay-locked loop.Yet delay-locked loop can the school signal mistake of card be between AA ' and the BB ' from scope, if the ripple edge that signal rises can not produce the fuzzy multiple lockout issue within scope, its exempt from the inequality of multiple locking suc as formula 1.1 with formula 1.2:
0.5×TCLK＜TVCDL(min)＜TCLK(1.1)
TCLK＜TVCDL(max)＜1.5×TCLK(1.2)
For example as TVCDL (min)=20ns, obtain 20ns＜TCLK＜40ns by formula (1.1), if TVCDL (max)=40ns, obtain 26.7ns＜TCLK＜40ns by formula (1.2), can be learnt by above-mentioned inequality and the framework of traditional delay locked loop the operable delay scope of TCLK to be restricted.
Summary of the invention
In order to address the above problem, but one of the object of the invention provides a kind of multiple phase delay-locked loop of frequency width opereating specification, it has one or three marginal phase detectors can receive the reference frequency signal, less delayed frenquency signal and larger delay frenquency signal, compare the phase difference of rising signal Up and decline signal Dn via three frenquency signals, adjust dynamically time of delay to adjust a control voltage by voltage controlled delay line, change the phase place that postpones frenquency signal, the time average of frequency period is dispensed to all delay frenquency signals, makes the operable scope of institute's time of delay also wide.
Another purpose of the present invention provides a kind of three marginal phase detectors, it uses two comparison circuits, and relatively reference frequency signal and less delayed frenquency signal are exported decline signal Dn at last respectively, the reference frequency signal is exported rising signal Up at last with larger delay frenquency signal, at last decline signal Dn and rising signal Up is sent to charge pump.
But another purpose of the present invention provides a kind of method of multiple phase delay-locked loop locking frequency of frequency width operation, it adjusts the delay signal in the voltage controlled delay line, each zero-time that postpones signal can on average be dropped within the frequency period, avoid the fuzzy multiple lockout issue.
In order to achieve the above object, the multiple phase delay-locked loop of the frequency width opereating specification of one embodiment of the invention, comprise: a voltage controlled delay line receives a reference frequency signal and postpones frenquency signal to produce several, and several postpone frenquency signal and comprise one first delay frenquency signal and one second delay frenquency signal; Three marginal phase detectors postpone frenquency signal and second according to reference frequency signal, first and postpone frenquency signal, produce set of pulses signal; Charge pump receives set of pulses signal and exports a Current Control signal; And one loop filter received current control signal to export a control voltage, wherein voltage controlled delay line is adjusted the time of delay of voltage controlled delay line by control voltage.
In addition, the three marginal phase detectors of one embodiment of the invention, it is to increase the band width opereating specification in the multiple phase delay-locked loop, three marginal phase detectors receive a reference frequency signal, one first and postpone frenquency signal and one second delay frenquency signal, export at last set of pulses signal.
Moreover, but the method for the multiple phase delay-locked loop locking frequency of the frequency width of one embodiment of the invention operation, comprise: in voltage controlled delay line, have between a plurality of delay signals according to the time sequencing arrangement, set the time of delay of a minimum and have each other identical time of delay so that postpone signal, and first postpones the time interval T1 of the beginning leading edge of signal and frequency period, and second time interval that postpones the beginning leading edge of signal and next frequency period was Tn; Relatively the size of T1 and Tn drops on a frenquency signal in the cycle to adjust time of delay so that postpone signal; If T1＜Tn then increases time of delay, have each other identical time of delay so that postpone signal, and the delay signal is to drop on a frenquency signal in the cycle; And if T1＞Tn, then reduce time of delay have each other identical time of delay so that postpone signal, and to postpone signal be to drop on a frenquency signal in the cycle.
Description of drawings
Figure 1 shows that the configuration diagram of existing delay-locked loop;
Fig. 2 A and Fig. 2 B are depicted as the frequency waveform locking schematic diagram of existing delay-locked loop;
Fig. 3 A and Fig. 3 B are depicted as the frequency waveform locking schematic diagram of existing delay-locked loop;
Figure 4 shows that the multiple phase delay-locked loop configuration diagram of one embodiment of the invention frequency width opereating specification;
Fig. 5 A is depicted as one embodiment of the invention frequency signal waveform schematic diagram when initial;
Fig. 5 B is depicted as frenquency signal waveform schematic diagram after one embodiment of the invention adjustment;
Fig. 6 A and Fig. 6 B are depicted as the configuration diagram of one embodiment of the invention three marginal phase detectors;
Be respectively the frenquency signal operation chart of Fig. 6 A figure and Fig. 6 B figure shown in Fig. 7 A and Fig. 7 B;
Figure 8 shows that the method for one embodiment of the invention multiple phase delay-locked loop locking frequency;
Fig. 9 A to Fig. 9 F is depicted as the multiple locking mechanism frequency diagram of avoiding of one embodiment of the invention.
Description of reference numerals: 11-voltage controlled delay line; The 12-phase detectors; The 13-charge pump; The 14-filter; The 21-voltage controlled delay line; 22-three marginal phase detectors; The 23-charge pump; The 24-loop filter; 221,222,226,227-D type flip-flop; 223,228-AND logic lock; S10～S42-step; AA '-one frequency range; BB '-one frequency range; T1, Tn-phase difference.
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
Figure 4 shows that the multiple phase delay-locked loop configuration diagram of one embodiment of the invention frequency width opereating specification.In the present embodiment, one voltage controlled delay line (VCDL) 21 comprises several Delay Elements and sequentially is connected in series, it receives a reference frequency signal Ref-Clk and exports 1 to N and postpones frenquency signal DLL-Ck1, DLL-Ck2, ..., DLL-Ckn, wherein the first delay frenquency signal is exported by the first Delay Element, and the second delay frenquency signal is exported by the N Delay Element, first postpones frenquency signal DLL-Ck1 and last postpones frenquency signal DLL-Ckn back coupling to three marginal phase detectors (3-edgePD) 22, add reference frequency (Ref-Clk) signal and also input to three marginal phase detectors (3-edgePD) 22, so that three marginal phase detectors (3-edgePD) 22 receive 3 input signals, export after treatment set of pulses signal, it comprises decline signal Dn and rising signal Up.
In one embodiment, three marginal phase detectors (3-edgePD), 22 processing modes are for postponing the phase difference value that frequency news DLL-Ckn compares leading (lead) or falls behind (lag) with first delay frequency news DLL-Ck1 and last respectively according to reference frequency signal (Ref-Clk), at last generation and a rising signal Up or the decline signal Dn of phase difference value with width.These three marginal phase detectors (3-edgePD) 22 comprise one first comparison circuit and one second comparison circuit, wherein this first comparison circuit receives this and postpones time pulse signal producing this decline signal Dn with reference to time pulse signal and this first, and this second comparison circuit receives this and postpones time pulse signal to produce this rising signal Up with reference to time pulse signal and this second.
Then, the rising signal Up that three marginal phase detectors (3-edgePD) 22 produce and the information of the difference on the frequency between the decline signal Dn, be sent to charge pump (the Charge Pump that is connected on the back, CP) circuit 23 is done the reference frame of charge or discharge action, with capacitor charging (charging) or the discharge (discharging) of control charge pump (CP) 23 generation current Ip to rear end loop filter (LF) 24, namely increase or reduce the magnitude of voltage of electric capacity on loop filter (LF) 24, loop filter (LF) 24 will filter at three marginal phase detectors (3-edgePD) 22 and the high-frequency noise that charge pump (CP) 23 produces, produce a control voltage Vcntl, this magnitude of voltage can be adjusted the time of delay (TVCDL) of voltage controlled delay line (VCDL) 21 by voltage controlled delay line (VCDL) 21, change the phase place of internal frequency, feedback again to three marginal phase detectors (3-edgePD) 22 comparison of beginning next cycle.In one embodiment, loop filter 24 is an electric capacity.
In above-mentioned framework, first output delay frenquency signal DLL-Ck1 and reference frequency signal Ref-Clk have a phase difference T1, delay frenquency signal DLL-Ckn and the reference frequency signal Ref-Clk of output have a phase difference Tn at last, the phase delay locked loop begins or resets when operating, be to be reset at minimum value (T1＜Tn) shown in Fig. 5 A the time of delay (TVCDL) of voltage controlled delay line (VCDL) 21 when initial, three marginal phase detectors (3-edgePD) 22 detect after the difference of phase difference T1 and phase difference Tn increase time of delay (TVCDL) in the voltage-regulation mode so that T1=Tn shown in Fig. 5 B, the pinning scope TCLK of delay-locked loop as shown in Equation 2:
TVCDL(min)＜TCLK＜TVCDL(max)(2)
The opereating specification of voltage controlled delay line (VCDL) 21 can complete operation in the pinning scope of delay-locked loop (DLL).
Fig. 6 A and Fig. 6 B are depicted as the configuration diagram of three marginal phase detectors, D type flip-flop 221 receives reference frequency signal Ref-Clk and a data signals in Fig. 6 A figure, export at last a decline signal Dn, D type flip-flop 222 receives first and postpones frenquency signal DLL-Ck1 and decline signal Dn, last output signal to AND logic lock 223, the digital sampling signal that AND logic lock 223 receives decline signal Dn signal and 222 outputs of D type flip-flop determines whether transmission replacement signal rst1, start the replacement action of D type flip- flop 221 and 222, its signal action schematic diagram is shown in Fig. 7 A.
D type flip-flop 226 receives n delay frenquency signal DLL-Ckn and data signals in Fig. 6 B, export at last a rising signal Up, D type flip-flop 227 receives reference frequency signal Ref-Clk and rising signal Up, last output signal to AND logic lock 228, the digital sampling signal that AND logic lock 228 receives rising signal Up and 227 outputs of D type flip-flop determines whether transmission replacement signal rst2, start the replacement action of D type flip- flop 226 and 227, its signal action is shown in Fig. 7 B.
Seeing also Fig. 8 is the method for multiple phase delay-locked loop locking frequency of the present invention, and step S10 establishes
A fixed minimum delay time produces T1 and the Tn time interval, in voltage controlled delay line, have between several delay signals according to the time sequencing arrangement, set the time of delay of a minimum and have each other identical time of delay so that postpone signal, and first time interval that postpones the beginning leading edge of signal and frequency period is T1, last postpones the time interval Tn of the beginning leading edge of signal and next frequency period, all postpone signal is to be distributed in a frenquency signal in the cycle, and when initial circuit came into operation, time interval T1 was less than time interval Tn; Step S20 judges whether multiple locking, if step S10 is then got back in multiple locking, then continues if not next step; Step S30 is the magnitude relationship of T1 and Tn relatively, drops on a frenquency signal in the cycle so that all postpone signal time of delay to adjust, and locking time, interval T 1 equaled time interval Tn at last; If T1＜Tn, then execution in step S41 increases time of delay, has each other identical time of delay so that postpone signal, and the delay signal is to drop on a frenquency signal in the cycle; If T1＞Tn, then execution in step S42 reduces time of delay, has each other identical time of delay so that postpone signal, and the delay signal is to drop on a frenquency signal in the cycle.
See also Fig. 9 A to Fig. 9 F and be the multiple locking mechanism of avoiding of this name one embodiment, when circuit working, produce several after one reference frequency signal Ref_Clk is received by voltage controlled delay line and postpone frenquency signal Dll_ck1, Dll_ck2, Dll_ck3, Dll_ck4, Dll_ck5 and Dll_ck6, when the frenquency signal frequency of input when becoming B by A so that circuit whether in an incoming frequency when locking and normal operation, can utilize adjacent three frenquency signals to do following judgement, be described below:
To postpone frenquency signal Ref_Clk, Dll_ck1 and Dll_ck2 are in adjacent three frenquency signals, if postponing the value of upper limb (rising edge) the sampling reference frequency signal Ref_Clk of frenquency signal Dll_ck2 is 0, expression is locked into the 2nd or the 3rd frequency period (cycle), such as Fig. 9 B and Fig. 9 C, or the value that postpones upper limb (rising edge) the sampling delay frenquency signal Dll_ck1 of frenquency signal Dll_ck2 is 0, expression is locked into the 4th, the 5th or the 6th frequency period (cycle), such as Fig. 9 D, Fig. 9 E and Fig. 9 F, (reset) circuit of then need resetting.If postponing the value of upper limb (rising edge) the sampling reference frequency signal Ref_Clk of frenquency signal Dll_ck2 is 1, express possibility and be locked into the 1st, the 4th or the 5th cycle, and the value that upper limb (rising edge) sampling that postpones frenquency signal Dll_ck2 postpones frenquency signal Dll_ck1 is 1, express possibility and be locked into the 1st, the 2nd or the 3rd frequency period (cycle), then to be locked into the 1st frequency period (cycle) be to belong to normal to this circuit, postpone frenquency signal and drop on a frenquency signal in the cycle, shown in Fig. 9 A.
According to above-mentioned, the value that postpones upper limb (rising edge) the sampling reference frequency signal Ref_Clk of frenquency signal Dll_ck2 inputted a logical circuit (not shown) with the value of sampling delay frenquency signal Dll_ck1 can judge.
Comprehensively above-mentioned, three marginal phase detectors of tool detecting phase difference of the present invention and difference on the frequency character, the framework of its formed multiple phase delay-locked loop is benefited to whole phase-locked loop, it can increase the acquisition scope (Acquisition Range) of locked loop, so that the frequency width opereating specification reaches maximum.
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limits, revise, even equivalence, but all will fall within the scope of protection of the present invention.
Claims (9)
1. but the method for the multiple phase delay-locked loop locking frequency of frequency width operation is characterized in that: comprise:
Step 1: in voltage controlled delay line, have between a plurality of delay frenquency signals according to the time sequencing arrangement, set the time of delay of a minimum so that described delay frenquency signal has identical time of delay each other, and one first time interval that postpones frenquency signal and the beginning leading edge in reference frequency cycle was T1, and one second time interval that postpones frenquency signal and the beginning leading edge in next reference frequency cycle was Tn;
Step 2: the size of T1 and Tn relatively, to adjust described time of delay so that drop on the cycle time of described delay frenquency signal in the cycle of a reference frequency signal;
If T1＜Tn, then
Increase described time of delay so that described delay frenquency signal has identical time of delay each other, and the cycle time of described delay frenquency signal be to drop in the cycle of a reference frequency signal; And
If T1〉Tn, then reduce described time of delay so that described delay frenquency signal has identical time of delay each other, and the cycle time of described delay frenquency signal be to drop in the cycle of a reference frequency signal.
2. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 1 operation, it is characterized in that: step 1 also comprises: when beginning at first, described time interval T1 is less than described time interval Tn.
3. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 1 operation, it is characterized in that: the described delay frenquency signal of the setting in the step 1 has identical step time of delay each other, and also comprise: be included in the cycle of a reference frequency signal cycle time of described delay frenquency signal.
4. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 3 operation, it is characterized in that: in the step 2 to adjust described time of delay so that drop on step in cycle of a reference frequency signal cycle time of described delay frenquency signal, also comprise: lock at last described time interval T1 and equal described time interval Tn.
5. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 4 operation, it is characterized in that: step in the cycle of whether dropping on a reference frequency signal cycle time of judging described delay frenquency signal in the step 2 also comprises:
Judge the no change of described reference frequency signal;
If, then take out three adjacent frenquency signals, comprise one first signal, one second signal and one the 3rd signal;
With described the 3rd signal described the first signal of taking a sample, if 0 reset circuit; And
With described the 3rd signal described the second signal of taking a sample, if 0 reset circuit.
6. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 5 operation, it is characterized in that: described the first signal is described reference frequency signal.
7. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 6 operation, it is characterized in that: step 2 also comprises: whether drop in the cycle of a reference frequency signal cycle time of judging described delay frenquency signal, if not reset circuit then.
But 8. the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 4 operation, it is characterized in that: whether drop on a frenquency signal cycle time of judging described delay frenquency signal in the step 2 comprised in the cycle:
Take out three adjacent frenquency signals, comprise one first signal, one second signal and one the 3rd signal;
With described the 3rd signal described the first signal of taking a sample, if 0 reset circuit; And
With described the 3rd signal described the second signal of taking a sample, if 0 reset circuit.
9. but the method for the multiple phase delay-locked loop locking frequency of frequency width according to claim 8 operation, it is characterized in that: described the first signal is described reference frequency signal.
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