CN102054745A - Method for forming contact hole - Google Patents
Method for forming contact hole Download PDFInfo
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- CN102054745A CN102054745A CN 200910198064 CN200910198064A CN102054745A CN 102054745 A CN102054745 A CN 102054745A CN 200910198064 CN200910198064 CN 200910198064 CN 200910198064 A CN200910198064 A CN 200910198064A CN 102054745 A CN102054745 A CN 102054745A
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- contact hole
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- etching
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Abstract
The invention discloses a method for forming a contact hole, which comprises the following steps of: sequentially forming an insulating medium layer, a hard mask layer and a photoresist layer on a semiconductor substrate; forming the graph of a contact hole opening on the photoresist layer; by taking the photoresist layer as a mask, etching the hard mask layer along the graph of the contact hole opening so as to form the contact hole opening; removing the photoresist layer; by taking the hard mask layer as the mask, etching the insulating medium layer to a certain depth along the contact hole opening by a plasma etching process, wherein the depth is one third to three fourths of the depth of a target contact hole; determining the type of charged ions accumulated on the surface of the hard mask layer, and introducing plasmas of which the type is opposite to that of the charged ions into a reaction chamber until the charged ions are neutralized; and by taking the hard mask layer as the mask, continuing to etch the insulating medium layer until the semiconductor substrate is exposed so as to form the target contact hole. The contact holes with uniform opening width can be formed by the method.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to the method that forms contact hole.
Background technology
Along with the develop rapidly of very lagre scale integrated circuit (VLSIC) ULSI (Ultra Large Scale Integration), integrated circuit fabrication process becomes and becomes increasingly complex with meticulous.In order to improve integrated level, reduce manufacturing cost, the critical size of element constantly diminishes, number of elements in the chip unit are constantly increases, plane routing has been difficult to satisfy the requirement that the element high density distributes, can only adopt polylaminate wiring technique, utilize the vertical space of chip, further improve the integration density of device.Between each layer wiring, need in contact hole, deposit metallic material be electrically connected.
Along with the critical size of element diminishes; it is more and more littler that the critical size of contact hole also becomes; simultaneously; increasing (depth-to-width ratio of contact hole increases) that the degree of depth of contact hole but becomes; in order to form the more contact hole of high-aspect-ratio; need to increase the thickness of dielectric layer; and need to increase the time of etching dielectric layer; therefore; form in the technology of contact hole at the etching dielectric layer, only using photoresist layer is not all right as the hard mask in the etching, because darker contact hole needs thicker photoresist layer; but; thick photoresist layer makes photoresist equipment be difficult to define less critical size, in order to address this problem, forms in the technology of contact hole at the etching dielectric layer; usually on dielectric layer, form hard mask layer, form protective dielectric layer in the technology of contact hole with the critical size that guarantees contact hole and at the etching dielectric layer.
The existing technology of contact hole of making is referring to figs. 1 to Fig. 5.As shown in Figure 1, comprising formation wiring layer 102 on the isostructural Semiconductor substrate 101 of drive circuit, wherein the material of wiring layer 102 can be aluminium or aluminium copper or polysilicon; On wiring layer 102, form insulating medium layer 103, be used for the isolation between rete; Form hard mask layer 104 on insulating medium layer 103 surfaces, with the thickness of the photoresist layer that reduces to form subsequently and in etching technics subsequently as etching stop layer and protect insulating medium layer, the material of described hard mask layer 104 for example is indefinite form polysilicon (amorphous poly silicon); Spin coating photoresist layer 106 on hard mask layer 104.
As shown in Figure 2, the contact hole pattern on the photomask 10 12 is transferred on the photoresist layer 106 by photoetching technique, forms contact hole opening figure 105.
As shown in Figure 3, be mask with photoresist layer 106, along contact hole opening figure 105 etching hard mask layers 104, form the contact hole opening with anisotropic etching technics (anisotropic etching).
As shown in Figure 4, remove photoresist layer 106 with ashing method.
As shown in Figure 5, be mask with described hard mask layer, to exposing wiring layer 102, form contact hole 107 along contact hole opening etching insulating medium layer 103, described anisotropic etching technics for example is plasma etching (plasma etching).
The manufacture craft of aforesaid contact hole, in the process of using plasma etching, wafer is exposed in the plasma ambient that includes high density reactive ion (reactive ions) and high energy bombarding ion (bombardment ions) always, etching can cause bombarding ion at the crystal column surface skewness for a long time, the contact hole top at some position is by overetch, the A/F at contact hole top is increased, finally cause the interior deposit metallic material of contact hole to form after the interconnection structure, because the thickness of dielectric layers between the adjacent interconnection structure diminishes, cause taking place between the adjacent interconnection structure phenomenon of puncture or short circuit.
With reference to the accompanying drawings shown in 6, vertical view for the contact hole array, the degree of depth of the contact hole among the figure is greater than 3um, the etching insulating medium layer formed the etch period of contact hole greater than 500 seconds, as can be seen from the figure, space D 1 between two adjacent contact holes is two adjacent contact holes of D1 less than the space D 2 between two other adjacent contact hole for spacing, takes place to puncture or leaky than being easier to.
Summary of the invention
The problem that the present invention solves provides a kind of method that forms contact hole, to avoid forming in the process of the contact hole uneven phenomenon of generation etching between the contact hole at the etching insulating medium layer.
For addressing the above problem, the invention provides a kind of method that forms contact hole, comprising: on Semiconductor substrate, form insulating medium layer, hard mask layer and photoresist layer successively; On photoresist layer, form the contact hole opening figure; With the photoresist layer is mask, along contact hole opening figure etching hard mask layer, forms the contact hole opening; Remove described photoresist layer; With the hard mask layer is mask, and to certain depth, the described degree of depth is for forming 1/3rd to 3/4ths of the target contact hole degree of depth along contact hole opening using plasma etching technics etching insulating medium layer; Judge the charged ion type of hard mask layer surface accumulation, the plasma of feeding and described charged ion type opposite in reaction chamber is to the described charged ion that neutralizes; With the hard mask layer is mask, continues the etching insulating medium layer to exposing Semiconductor substrate, forms the target contact hole.
Compared with prior art, such scheme has the following advantages:
The present invention is by the charged ion type of hard mask layer surface accumulation, in reaction chamber, feed plasma with described charged ion type opposite, to the described charged ion that neutralizes, thereby the charged particle of avoiding hard mask layer surface in technology subsequently changes the direction of motion of plasma etch process ionic medium body, make the etch rate of optional position, hard mask layer surface identical, thereby form the uniform contact hole of A/F, make the spacing between the adjacent contact hole identical.
Description of drawings
Fig. 1 to Fig. 5 is the structural representation that existing technology forms contact hole;
Fig. 6 is the vertical view of the contact hole array of existing technology formation;
Fig. 7 is the first embodiment flow chart that the present invention forms contact hole;
Fig. 8 to Figure 12 is the structural representation that the specific embodiment of the invention forms contact hole;
Figure 13 is the vertical view of the contact hole array that forms of the present invention.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Description according to prior art, contact hole for high-aspect-ratio, because the contact hole degree of depth is big, it is longer that etching forms the required time of contact hole, therefore cause the etching degree difference at different contact hole tops, some contact hole top is because overetch causes the contact hole A/F excessive, and the thickness of dielectric layer reduces between the adjacent contact hole, causes being short-circuited between the adjacent contact hole or puncturing.
The present inventor studies show that, form in the process of contact hole at the etching insulating medium layer, owing to comprise the structure long term exposure of hard mask layer and insulating medium layer in plasma environment, therefore, hard mask layer surface meeting a certain amount of positive charge of irregular gathering or negative electrical charge, positive charge or negative electrical charge are after the hard mask layer surface aggregation, in the technology that continues etching insulating medium layer formation contact hole, the direction of motion that positive charge of assembling or negative electrical charge can change etching ion in the plasma etch process, thereby the etching ion concentration that causes correspondence position changes, thereby cause the etch rate of correspondence position and etching degree to change, thus make etching finish after the top width of diverse location contact hole inhomogeneous.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 7 is the embodiment flow chart that the present invention forms contact hole.As shown in Figure 7, execution in step S101 forms insulating medium layer, hard mask layer and photoresist layer successively on Semiconductor substrate; Execution in step S102 forms the contact hole opening figure on photoresist layer; Execution in step S103 is a mask with the photoresist layer, along contact hole opening figure etching hard mask layer, forms the contact hole opening; Execution in step S104 removes described photoresist layer; Execution in step S105 is a mask with the hard mask layer, and to certain depth, the described degree of depth is for forming 1/3rd to 3/4ths of the target contact hole degree of depth along contact hole opening using plasma etching technics etching insulating medium layer; Execution in step S106 judges the charged ion type that the hard mask layer surface accumulates, and the plasma of feeding and described charged ion type opposite in reaction chamber is to the described charged ion that neutralizes; Execution in step S107 is a mask with the hard mask layer, continues the etching insulating medium layer to exposing Semiconductor substrate, forms the target contact hole.
Fig. 8 to Figure 10 is the specific embodiment schematic diagram that the present invention forms contact hole.
With reference to shown in Figure 8, Semiconductor substrate is provided, described Semiconductor substrate comprises and is formed with the isostructural substrate 201 of drive circuit and is positioned at wiring layer 202 on the substrate 201, wherein the material of wiring layer 202 can be aluminium or aluminium copper or polysilicon, if the material of wiring layer 202 is aluminium, copper or aluminium copper equal sign, then formation method is sputtering method or galvanoplastic etc.; If the material of wiring layer 202 is a polysilicon, then formation method is chemical vapour deposition technique or plasma enhanced chemical vapor deposition method etc.
Continue to form insulating medium layer 203 with reference to shown in Figure 8 with chemical vapour deposition technique or physical vaporous deposition on wiring layer 202, the insulation that is used between rete is isolated, and the material of described insulating medium layer 203 can be silica or tetraethoxysilane etc.; Afterwards, form hard mask layer 204 with chemical vapour deposition technique or physical vaporous deposition on insulating medium layer 203 surfaces, in order to form in the contact hole technology as etch mask at subsequent etching process protection insulating medium layer 203 and at subsequent etching insulating medium layer 203, the material of described hard mask layer 204 can be silicon nitride, silicon oxynitride or indefinite form polysilicon etc., preferably indefinite form polysilicon; Subsequently, spin coating photoresist layer 206 on hard mask layer 204.
Optionally, can also form anti-reflecting layer between hard mask layer 204 and photoresist layer 206, the rete below protection in post-exposure technology is avoided the influence of light.
In the present embodiment, the thickness of insulating medium layer 203 is 2 microns～3 microns, and the thickness of described hard mask layer 204 is 2000 dusts～4000 dusts.
As shown in Figure 9, on photoresist layer 206, form the photoresist opening, afterwards, with described photoresist layer 206 is mask, along photoresist opening etching hard mask layer 204, form contact hole opening 205, the technology of the described hard mask layer 204 of etching for example is dry etch process.
As shown in figure 10, remove photoresist layer 206 with ashing method; With hard mask layer 204 is mask, along contact hole opening 205 using plasma etching technics etching insulating medium layers 203 to certain depth, form contact hole 209, the degree of depth of described contact hole 209 is for forming 1/3rd to 3/4ths of the target contact hole degree of depth, preferably, the degree of depth of described contact hole 209 is for forming 1/2nd of the target contact hole degree of depth.
Form in the technology of contact hole 209 at described etching insulating medium layer 203, the particle that is partly with positive charge or negative electrical charge in the etching gas can accumulate in the surface of hard mask layer 204, thereby has the particle of positive charge or negative electrical charge in the distribution of the surface imperfection of hard mask layer 204.
Difference according to etching gas kind in the etching agent that adopts, the charged ion kind difference of hard mask layer surface accumulation, that is to say, positive charge or negative electrical charge can be gathered in the hard mask layer surface, therefore, need to carry out judge the processing step of the charged ion type of hard mask layer surface accumulation, detect or judge the charged ion type of hard mask layer surface accumulation, just can feed opposite ion with in the positive charge or the negative electrical charge that gather with the hard mask layer surface.
In a specific embodiment of the present invention, in the described plasma etch process, main etching gas is CxFy, wherein, and (1＜X＜6,5＜Y＜9).To adopt C
5F
8With Ar be example as main etching gas, wherein, C
5F
8Flow be 15～25cm
3/ min (sccm), the flow of Ar are 600～900sccm, and etch period is 200 seconds to 550 seconds, the preferred time for example is 250 seconds, and 300 seconds etc., reaction chamber pressure was 15～40mT in the etching process, the top radio-frequency power is 1800～2500W, and the bottom radio-frequency power is 1500～2200W.The degree of depth of the contact hole of the certain depth that etching forms for example is 1.5 microns, 2.0 microns etc.Further, described etching can also comprise oxygen in other, and the flow of oxygen is 35～50sccm.
Employing comprises C
5F
8With the etching gas of Ar, carry out described etching technics, to carry out after the certain hour, hard mask layer surface aggregation certain amount of electrons is as shown in accompanying drawing 10.The electronics of described gathering can change the direction of motion of the etching ion that has positive charge in the plasma etch process, thereby the etching ion concentration that causes correspondence position changes, thereby cause the etch rate of correspondence position to increase, the width at the contact hole top that correspondence position forms increases, the less thick of insulating medium layer between the adjacent contact hole.
As shown in figure 11, the plasma 207 of feeding and described charged ion type opposite in reaction chamber is to the described charged ion that neutralizes;
With hard mask layer surface aggregation certain amount of electrons is example, the plasma that employing has positive charge pours in the reaction chamber, with the described electronics that neutralizes, the gas that produces the described plasma that has a positive charge is argon plasma for example, preferably, can in described argon plasma, add a certain amount of nitrogen plasma, to increase the generation efficient of positively charged plasma.Pouring the described technology that has the plasma of positive charge for example is: the flow of argon gas is 800～1200cm
3/ min (sccm), the flow of nitrogen are 10～30sccm, and etch period is 5～20 seconds, and reaction chamber pressure is 50～150mT in the etching process, and the top radio-frequency power is 1500～2500W, and the bottom radio-frequency power is 0～200W.
Preferably, the flow of argon gas is 1000cm
3/ min (sccm), the flow of nitrogen are 20sccm, and etch period is 5 seconds, and reaction chamber pressure is 100mT in the etching process, and the top radio-frequency power is 2000W, and the bottom radio-frequency power is 100W.In described technology, the bottom radio-frequency power is very low, and this is the particle bombardment of not expecting for fear of too much, thereby avoids hard mask layer is caused physical damnification.
By described technology, neutralize the charged particle on hard mask layer surface, thereby the charged particle of avoiding hard mask layer surface in technology subsequently changes the direction of motion of plasma etch process ionic medium body, make the etch rate of optional position, hard mask layer surface identical, thereby form the uniform contact hole of A/F, make the spacing between the adjacent contact hole identical.
As shown in figure 12, be mask with hard mask layer 204, continue etching insulating medium layer 203 to exposing Semiconductor substrate, form the target contact hole.The depth-to-width ratio of the described target contact hole that forms is greater than 20.
In a specific embodiment of the present invention, described etching insulating medium layer is to exposing Semiconductor substrate, and the technology that forms the target contact hole is plasma etch process, and main etching gas is CxFy, wherein, and (1＜X＜6,5＜Y＜9).To adopt C
5F
8With Ar be example as main etching gas, wherein, C
5F
8Flow be 15～25cm
3/ min (sccm), the flow of Ar are 600～900sccm, and etch period is 250 seconds, the degree of depth of the target contact hole that etching forms is 3 microns, reaction chamber pressure is 15～40mT in the etching process, and the top radio-frequency power is 1800～2500W, and the bottom radio-frequency power is 1500～2200W.
Described technology can form the uniform contact hole of A/F, thereby makes the width of the insulating medium layer between the adjacent contact hole identical.
As shown in figure 13, for adopting the vertical view of the contact hole array that the described method for manufacturing contact hole of present embodiment forms, the degree of depth of the contact hole among the figure is greater than 3um, the etching insulating medium layer formed the etch period of contact hole greater than 500 seconds, as can be seen from the figure, the spacing between adjacent two contact holes is identical.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. a method that forms contact hole is characterized in that, comprising:
On Semiconductor substrate, form insulating medium layer, hard mask layer and photoresist layer successively;
On photoresist layer, form the contact hole opening figure;
With the photoresist layer is mask, along contact hole opening figure etching hard mask layer, forms the contact hole opening;
Remove described photoresist layer;
With the hard mask layer is mask, and to certain depth, the described degree of depth is for forming 1/3rd to 3/4ths of the target contact hole degree of depth along contact hole opening using plasma etching technics etching insulating medium layer;
Judge the charged ion type of hard mask layer surface accumulation, the plasma of feeding and described charged ion type opposite in reaction chamber is to the described charged ion that neutralizes;
With the hard mask layer is mask, continues the etching insulating medium layer to exposing Semiconductor substrate, forms the target contact hole.
2. according to the method for the described formation contact hole of claim 1, it is characterized in that the etching gas of the plasma etch process of etching insulating medium layer comprises C
5F
8And Ar.
3. according to the method for the described formation contact hole of claim 2, it is characterized in that C
5F
8Flow be 15～25sccm, the flow of Ar is 600～900sccm, etch period is 200 seconds to 550 seconds.
4. according to the method for the described formation contact hole of claim 1, it is characterized in that the depth-to-width ratio scope of the described target contact hole of formation is 15: 1 to 30: 1.
5. according to the method for the described formation contact hole of claim 1, it is characterized in that, in and the technology of the charged ion of hard mask layer surface accumulation be: feed the plasma that contains argon and nitrogen.
6. according to the method for the described formation contact hole of claim 5, it is characterized in that the flow of argon gas is 15～25sccm, the flow of nitrogen is 600～900sccm, and etch period is 5～20 seconds.
7. according to the method for the described formation contact hole of claim 6, it is characterized in that reaction chamber pressure is 50～150mT in the etching process, the top radio-frequency power is 200～500W, and the bottom radio-frequency power is 0～50W.
8. according to the method for the described formation contact hole of claim 1, it is characterized in that the material of described hard mask layer is silicon nitride, silicon oxynitride or indefinite form polysilicon.
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| CN 200910198064 CN102054745B (en) | 2009-10-30 | 2009-10-30 | Method for forming contact hole |
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| CN 200910198064 CN102054745B (en) | 2009-10-30 | 2009-10-30 | Method for forming contact hole |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569180A (en) * | 2012-02-10 | 2012-07-11 | 上海宏力半导体制造有限公司 | Production method of power MOS (Metal Oxide Semiconductor) contact hole |
| CN102867778A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Defect solution scheme for 40/45 nano process metal hard photomask structure |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
| CN104465331A (en) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Photoetched wafer treatment method |
| CN106373919A (en) * | 2015-07-20 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method for semiconductor structure |
| CN110931356A (en) * | 2018-09-19 | 2020-03-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112310087A (en) * | 2019-07-30 | 2021-02-02 | 爱思开海力士有限公司 | Semiconductor memory device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006049817A (en) * | 2004-07-07 | 2006-02-16 | Showa Denko Kk | Plasma treatment method and plasma etching method |
| CN100353520C (en) * | 2005-01-07 | 2007-12-05 | 联华电子股份有限公司 | Method for making dual inlay structure and removing its remnant polymer |
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2009
- 2009-10-30 CN CN 200910198064 patent/CN102054745B/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569180A (en) * | 2012-02-10 | 2012-07-11 | 上海宏力半导体制造有限公司 | Production method of power MOS (Metal Oxide Semiconductor) contact hole |
| CN102867778A (en) * | 2012-09-17 | 2013-01-09 | 上海华力微电子有限公司 | Defect solution scheme for 40/45 nano process metal hard photomask structure |
| CN102867778B (en) * | 2012-09-17 | 2015-06-24 | 上海华力微电子有限公司 | Defect solution scheme for 40/45 nano process metal hard photomask structure |
| CN104217964A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Forming method of conductive plug |
| CN104465331A (en) * | 2014-12-24 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Photoetched wafer treatment method |
| CN106373919A (en) * | 2015-07-20 | 2017-02-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method for semiconductor structure |
| CN106373919B (en) * | 2015-07-20 | 2019-09-27 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN110931356A (en) * | 2018-09-19 | 2020-03-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112310087A (en) * | 2019-07-30 | 2021-02-02 | 爱思开海力士有限公司 | Semiconductor memory device |
| CN112310087B (en) * | 2019-07-30 | 2023-11-10 | 爱思开海力士有限公司 | semiconductor memory device |
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