CN102053169B - Method for manufacturing failure analysis sample in interconnection structure - Google Patents
Method for manufacturing failure analysis sample in interconnection structure Download PDFInfo
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- CN102053169B CN102053169B CN200910198593.6A CN200910198593A CN102053169B CN 102053169 B CN102053169 B CN 102053169B CN 200910198593 A CN200910198593 A CN 200910198593A CN 102053169 B CN102053169 B CN 102053169B
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Abstract
The invention relates to a method for manufacturing a failure analysis sample in an interconnection structure. The method comprises the following steps of: carrying out a physical sputtering technology on the cross section of a sample, and testing the sample with an electronic microscope. The method is favorable to the accurate characterization of the failure analysis on technological parameters.
Description
Technical field
The present invention relates to make the method for failure analysis sample in interconnection structure, relate in particular to a kind of method for making of take the failure analysis sample in interconnection structure that copper is material.
Background technology
In semiconductor manufacturing industry, there are various checkout equipments, TEM (TransmissionElectron Microscope wherein, transmission electron microscope) be for detection of an important tool of pattern, size and characteristic that forms the film of device, application number is 200310122961 Chinese patent application file TEM sample of proposing the surface damage that a kind of Observable ion beam causes and preparation method thereof, can observe easy, intuitively FIB prepare in TEM print process, damage failure analysis sample surface being caused by ion beam.
And SEM (Scan Electron Microscope, scanning electron microscope) is for detection of the pattern of xsect and the important tool of characteristic that form device.By the principle of work that SEM detects, be print that need are detected with cutting, grind, then put into the xsect situation that SEM sight chamber is observed sample, then analyze.An outstanding advantages of SEM is to have higher resolution.
After semiconductor devices critical size develops into 0.13 μ m, the effect postponing in order to reduce RC, metallic copper has replaced aluminium gradually as interconnection structure.From material character, aluminium surface can form rapidly the oxide layer of one deck densification and stop aluminium to be further oxidized in air, and therefore, in failure analysis process, it is very stable that aluminium sample seems.Copper can not form the oxide layer of one deck densification and go to stop copper to be oxidized in air, and therefore, in failure analysis process, because copper is very easy to oxidation and corrosion, the preparation of the sample of cupric and preservation are challenges of failure analysis always.
Method therefor is at present: prepare after copper sample, carry out at once scanning electron microscope (SEM) analysis.But this method has obvious shortcoming: cannot avoid sample oxidation.As shown in Figure 1, copper in failure analysis sample exposes after a few minutes oxidized in air, can find out that Cu Metal (copper metal layer) is along interface to external oxidation, cause barrier (restraining barrier) interface unclear, although the live width of Cu Metal is still greater than barrier's, have a strong impact on the accurate sign of failure analysis to technological parameter.And as shown in Figure 2, if failure analysis sample is placed several hours in air, copper is wherein oxidized very serious, can only in the middle of metal valley, see 1 Cu Metal structure, much smaller than barrier thickness, this situation can not be used as analysis to measure completely.
Therefore,, when prior art take in preparation the failure analysis sample in interconnection structure that copper is material, copper metal can be oxidation rapidly within one or two minutes and corrode, and causes copper interconnecting line structural interface unintelligible, has a strong impact on the accurate sign of failure analysis to technological parameter.Once failure analysis sample in interconnection structure has been analyzed, to place after a period of time, data filling can not be analyzed or carry out to copper can, by heavy corrosion, again.Summary of the invention
The problem that the present invention solves is to provide a kind of method for making of failure analysis sample in interconnection structure, prevents that failure analysis from can not accurately characterize or can not carry out failure analysis technological parameter.
For addressing the above problem, the invention provides a kind of method for making of failure analysis sample in interconnection structure, comprising: example cross section is carried out to physical sputtering technology; By electron microscope, described sample is tested.
Optionally, described physical sputtering employing is argon ion.In described physical sputtering process, sample need to be rotated, rotating speed be 20rmp (rev/min)～40rmp.
Optionally, described sample comprises metallic copper and low-k material.
Optionally, the voltage that the described physical sputtering for low-k material adopts is 2.8KV～3.2KV, and electric current is 90 μ A～110 μ A, and sputtering time is 80s～100s.
Optionally, described physical sputtering carries out under vacuum.
Optionally, described electron microscope is scanning electron microscope.
Compared with prior art, the present invention has the following advantages: example cross section is carried out to physical sputtering technology, due to after physical sputtering is processed, because the ion that physical sputtering adopts is different with the speed that metallic copper and restraining barrier tantalum react, after sputter, copper interconnection structure xsect has all been pushed away inward a bit, not only make the interface between unlike material more clear, and find in actual applications effectively to prevent that metallic copper is oxidized at short notice or corrodes, be conducive to the accurate sign of failure analysis to technological parameter; In addition, also can carry out crucial pattern and the technological parameter that repetition sputter reaches replicate analysis observation copper metal interconnect structure to sample.
Further, adopt argon ion as physical sputtering ion, the speed of argon ion bombardment metallic copper is greater than the speed of bombardment restraining barrier tantalum, therefore after sputter copper interconnection structure xsect lower than the xsect of restraining barrier tantalum, make the interface between metallic copper and restraining barrier tantalum clear, effectively prevent that metallic copper is oxidized at short notice or corrodes, be conducive to the accurate sign of failure analysis to technological parameter simultaneously.
Accompanying drawing explanation
Fig. 1 is that the copper in existing failure analysis sample exposes oxidized design sketch after a few minutes in air;
Fig. 2 is that existing failure analysis sample is placed several hours copper by highly oxidized design sketch in air;
Fig. 3 is the embodiment process flow diagram that the present invention makes failure analysis sample in interconnection structure;
Fig. 4 is the schematic diagram of making failure analysis sample in interconnection structure described in the embodiment of the present invention;
Fig. 5 is the design sketch of the failure analysis sample in interconnection structure made of the present invention.
Embodiment
Because semiconductor devices critical size is more and more less, the effect postponing in order to reduce RC, metallic copper has replaced aluminium gradually as interconnection structure, and prior art is when the failure analysis sample in interconnection structure that copper is material is take in preparation, copper metal is easy to oxidized and corrosion, cause copper interconnecting line structural interface unintelligible, have a strong impact on failure analysis.The object of the invention is to example cross section to carry out physical sputtering technology, due to after physical sputtering is processed, because the ion that physical sputtering adopts is different with the speed that metallic copper and restraining barrier tantalum react, after sputter, copper interconnection structure xsect has all been pushed away inward a bit, not only make the interface between unlike material more clear, and find in actual applications effectively to prevent that metallic copper is oxidized at short notice or corrodes, be conducive to the accurate sign of failure analysis to technological parameter; In addition, also can carry out crucial pattern and the technological parameter that repetition sputter reaches replicate analysis observation copper metal interconnect structure to sample.Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 3 is the embodiment process flow diagram that the present invention makes failure analysis sample in interconnection structure.As shown in Figure 3, execution step S1, carries out physical sputtering technology to example cross section.
What described physical sputtering adopted is argon ion.In described physical sputtering process, sample need to be rotated, and rotating speed is 20rmp～40rmp.The voltage that described physical sputtering adopts is 2.8KV～3.2KV, and electric current is 90 μ A～110 μ A, and sputtering time is 80s～100s.
Described physical sputtering carries out under vacuum.
Execution step S2, tests described sample by electron microscope.
Described electron microscope is transmission electron microscope or scanning electron microscope.
A method for making for failure analysis sample in interconnection structure, carries out physical sputtering technology to example cross section, makes the interface between interconnection structure copper and restraining barrier tantalum clear.
Described sample refers to the part that need to carry out SEM test of cutting from wafer, and described crystal column surface has formed rete or the connecting circuit of setting, and described in the present embodiment, sample is for to cut down from wafer the failure analysis sample that comprises copper interconnection structure.
The described method that sample is processed, shown in accompanying drawing 4:
The sample 120 that includes copper interconnection structure is placed in reaction chamber 100, in described reaction chamber 100, example cross section is carried out to physical sputtering, to prevent that metallic copper is oxidized at short notice or corrodes, make copper interconnecting line structural interface clear.
In the present embodiment, described physical sputtering carries out under vacuum, can prevent from that copper surface is directly exposed in air, to cause oxidation or corrosion.
In the present embodiment, described physical sputtering can adopt argon ion, and required sputtering voltage is 2.8KV～3.2KV, and sputtering current is 90 μ A～110 μ A, and sputtering time is 80s～100s.Wherein, the electric current of sputter and Control of Voltage can avoid high-energy sputter to the copper damage of low K (specific inductive capacity) dielectric material around compared with low condition.
Preferred embodiment physical sputtering adopts argon ion as one, and required sputtering voltage is 3KV, and sputtering current is 100 μ A, and sputtering time is 90s.
In the present embodiment, in described physical sputtering process, sample need to be rotated, and to improve the homogeneity of sputter, wherein the rotating speed of rotation is 20rmp～40rmp.
The present embodiment, can guarantee to make copper surface to be difficult for oxidation or corrosion phenomenon occur within the short time (a few minutes are dozens of minutes even), makes restraining barrier and metallic copper interface clear, the accurate sign that can carry out failure analysis.For the sample of already oxidised after placement a period of time and corrosion, the method for applicable physical sputtering, can reanalyse or data filling same sample too.
Fig. 5 is the design sketch of the failure analysis sample in interconnection structure made of the present invention.By the method for electrical location, on sample, find failed areas; By machine cuts method, the xsect of failed areas is exposed to the open air; Then, physical sputtering is carried out in sample fails region, prevent the oxidized or corrosion of the copper of failed areas; Sample is put into electron microscope observation chamber, and the electron beam irradiation failed areas of accelerating with high pressure, amplifies the semiconductor device features of failed areas, project on screen and analyze.Because sample has passed through physical sputtering processing, can see that in Fig. 5, whole sample is very clean, restraining barrier and metallic copper interface are clear, there is no copper oxidation and corrosion completely, metal pattern obtains clear sign, and irregular bottom is also observed, and makes follow-up failure analysis effect very good.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (5)
1. take the method for making of the failure analysis sample in interconnection structure that copper is material for one kind, it is characterized in that, described sample is for putting into the situation that its xsect is observed by observation ward, then analyze, comprise: the sample that includes copper interconnection structure is placed in reaction chamber, example cross section is carried out to physical sputtering technology, make the xsect of metallic copper lower than the xsect on restraining barrier, interface between metallic copper and restraining barrier is clear, and prevent that metallic copper is oxidized at short notice or corrodes, described physical sputtering carries out under vacuum, in described physical sputtering process, sample need to be rotated.
2. the method for making of the failure analysis sample in interconnection structure that the copper of take is according to claim 1 material, is characterized in that, what described physical sputtering adopted is argon ion.
3. the method for making of the failure analysis sample in interconnection structure that the copper of take is according to claim 2 material, is characterized in that, in described physical sputtering process, the rotating speed that sample is rotated is 20rmp～40rmp.
4. the method for making of the failure analysis sample in interconnection structure that the copper of take is according to claim 1 material, is characterized in that, described sample comprises metallic copper and low-k material.
5. the method for making of the failure analysis sample in interconnection structure that the copper of take is according to claim 4 material, it is characterized in that, the voltage that the described physical sputtering for low-k material adopts is 2.8KV～3.2KV, and electric current is 90 μ A～110 μ A, and sputtering time is 80s～100s.
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| CN200910198593.6A CN102053169B (en) | 2009-11-10 | 2009-11-10 | Method for manufacturing failure analysis sample in interconnection structure |
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| CN200910198593.6A CN102053169B (en) | 2009-11-10 | 2009-11-10 | Method for manufacturing failure analysis sample in interconnection structure |
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| CN102053169A CN102053169A (en) | 2011-05-11 |
| CN102053169B true CN102053169B (en) | 2014-02-05 |
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| CN105891239B (en) * | 2016-04-05 | 2019-05-31 | 武汉新芯集成电路制造有限公司 | The preparation method and test sample preparation method of copper tantalum pattern in semiconductor EM test |
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| US20050059258A1 (en) * | 2003-09-12 | 2005-03-17 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
| JP2006165569A (en) * | 2004-12-07 | 2006-06-22 | Samsung Electronics Co Ltd | Analysis structure for failure analysis in semiconductor device, and failure analysis method using the same |
| CN101017793A (en) * | 2007-02-16 | 2007-08-15 | 上海集成电路研发中心有限公司 | A making method for diffusing blocking layer |
| CN101127320A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Making method for interconnection structure |
| CN101211818A (en) * | 2006-12-26 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated circuit interlinkage structure interstitial copper-plating method and structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5135002B2 (en) * | 2008-02-28 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059258A1 (en) * | 2003-09-12 | 2005-03-17 | International Business Machines Corporation | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same |
| JP2006165569A (en) * | 2004-12-07 | 2006-06-22 | Samsung Electronics Co Ltd | Analysis structure for failure analysis in semiconductor device, and failure analysis method using the same |
| CN101127320A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Making method for interconnection structure |
| CN101211818A (en) * | 2006-12-26 | 2008-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated circuit interlinkage structure interstitial copper-plating method and structure |
| CN101017793A (en) * | 2007-02-16 | 2007-08-15 | 上海集成电路研发中心有限公司 | A making method for diffusing blocking layer |
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Effective date of registration: 20121113 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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