CN102045277B - MIMO-based single carrier frequency domain equalizing device - Google Patents
MIMO-based single carrier frequency domain equalizing device Download PDFInfo
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Abstract
The invention discloses a multiple input multiple output (MIMO)-based single carrier frequency domain equalizing device, which comprises first and second extractors, first and second frame synchronizers, first and second sampling phase trackers and first and second shift registers, and also comprises first and second channel estimation units and a decision feedback equalizing unit. Multipath channel information is acquired from aliasing received signals by using a channel estimation sequence orthogonal to frequency domain phase shift, the received signals are subjected to combined frequency domain equalizing and primary time domain decision by using the channel information, and residual inter-symbol interference is estimated and is fed back to a signal before secondary decision so as to reduce an error rate. The device has the advantages that: the device is easy to implement, has excellent performance and can be used for MIMO multiplexing and MIMO diversity, and the like, and the device is particularly applied to single carrier frequency domain equalizing communication devices with limited frequency spectrum resource or severe channel environments.
Description
Technical field
The present invention relates in the communications field to use channel estimating and frequency domain equalization device in the single-carrier frequency domain equalization system of MIMO technology, be particularly useful as the single carrier frequency domain equalization communicator that frequency spectrum resource is limited or channel circumstance is abominable.
Background technology
Traditional single-carrier frequency domain equalization system mostly is the single-shot list and receives system, although anti-multipath performance and ofdm system are equally matched, the availability of frequency spectrum is lower, under the limited condition of frequency spectrum resource, is difficult to transmit Large Volume Data; When channel circumstance was abominable, receive threshold can improve greatly, the bit error rate performance severe exacerbation.And, the employed zero forcing equalization of traditional single-carrier frequency domain equalization system and MMSE equalization algorithm, bit error rate performance is also not satisfactory.
Summary of the invention
The object of the invention is to avoid the weak point in the above-mentioned background technology and a kind of single carrier frequency domain equalization communicator based on MIMO is provided.The present invention utilizes 22 antenna structures of receiving, and when adopting MIMO multiplexing, the availability of frequency spectrum of traditional single-carrier frequency domain equalization system is greatly improved; When adopting the MIMO diversity, can greatly improve the bit error rate performance of traditional single-carrier frequency domain equalization system.And after adopting new decision feedback equalization algorithm, the bit error rate performance of system also will further be promoted.
The object of the present invention is achieved like this:
A kind of single carrier frequency domain equalization device based on MIMO (multiple-input and multiple-output), it comprises the first to second withdrawal device, the first to second frame synchronizer, the first to second sampling phase tracker and the first to second shift register, also comprises first to second channel estimation unit and decision feedback equalization unit;
The input port 1 of described the first to second withdrawal device links to each other with B with oversampled signals stream A respectively, the input port 3 of the first to second withdrawal device receives respectively the sampling location control signal of the first to second sampling phase tracker output port 3 outputs, carries out over-sampling and extracts the rear input port 1 that is exported respectively to the first to second frame synchronizer by the output port 2 of the first to second withdrawal device; Signal after the first to second frame synchronizer extracts over-sampling carries out frame synchronization, the first to second frame synchronizer output port 2 exports the frame synchronization index signal to respectively the enabling signal port one of the first to second sampling phase tracker, and the first to second frame synchronizer output port 3 exports the frame synchronization index signal to respectively the enabling signal port one of the first to second shift register; The input port 2 of the first to second sampling phase tracker receives respectively oversampled signals stream A and B, constantly adjusts timing phase by the cumlative energy of more a plurality of symbol sample values again, and by output port 3 correct sampling phase is returned to withdrawal device; Export the first output port 1 to the second channel estimation unit to by output port 2 respectively behind the signal lag after the first to second shift register will correctly be sampled; The first output port 2,3,4 to the road estimation unit links to each other with the input port 1,2,3 of decision feedback equalization unit respectively, the second output port 2,3,4 to the road estimation unit links to each other with the input port 4,5,6 of decision feedback equalization unit respectively, the first oversampled signals that receives to the utilization of second channel estimation unit obtains the multiplex (MUX) information of packet delivery time, and sends it to the decision feedback equalization unit; The output port 7,8 of decision feedback equalization unit links to each other respectively with port C, D, and decision feedback equalization unit by using multiplex (MUX) information carry out decision feedback equalization to receiving packet, and the output time-domain decision value is to port C, D.
Described the first channel estimating unit is made of to the second channel interpolater the first pilot data frequency domain separator, the 3rd to the 4th shift register, the first read-only memory, the first multiplier, an IFFT converter, the 5th to the 6th shift register, the first to the 2nd FFT converter and first;
Described first the first pilot data frequency domain separator input port 1 to the second channel estimation unit receives the oversampled signals of the first shift register output port 2 outputs, with this signal after FFT transforms to frequency domain, pilot packet signal in the signal is separated with data packet signals, the output port 2 of the first pilot data frequency domain separator is sent into data packet signals 3 input ports 1 of the pilot packet signal being sent into the 4th shift register of output port of input port 1, the first pilot data frequency domain separator of the 3rd shift register; The input port 1 of decision feedback equalization unit sent into data packet signals respectively by the 3rd shift register by output port 2 after time-delay; The 4th shift register is sent into the first input port 1 to multiplier with the pilot packet signal by output port 2 after time-delay; The first read-only memory will the data sequence relevant with frequency domain phase shift orthogonal sequence be exported to the input port 2 of the first multiplier by output port 1; The first multiplier is finished the multiplying from the two-way input data of input port 1 and input port 2, respectively operation result is sent into the input port 1 of the first to IFFT converter by output port 3; After the one IFFT converter will change back to time domain from the input data of input port 1, cut apart the two-way channel information in time domain respectively, and the two-way channel information after will cutting apart is sent into respectively each input port 1 of the 5th and the 6th shift register by output port 2 and output port 3; The the 5th and the 6th shift register after the alignment of two-way channel information, is sent into each path channels information respectively the input port 1 of the first and second FFT converters through time-delay by output port 2; After the first and second FFT converters will become frequency domain again from the channel information of input port 1, again each road frequency domain channel information is sent into respectively the input port 1 of the first and second channel interpolation devices by output port 2; The first and second channel interpolation devices carry out interpolative operation to the frequency domain channel information of input, and operation result is then sent into respectively the input port 2,3 of decision feedback equalization unit by output port 2.
Described second channel estimation unit is made of the second pilot data frequency domain separator, the 7th to the 8th shift register, the second read-only memory, the second multiplier, the 2nd IFFT converter, the 9th to the tenth shift register, the 3rd to the 4th FFT converter and the 3rd to the 4th channel interpolation device;
Described first the second pilot data frequency domain separator input port 1 to the second channel estimation unit receives the oversampled signals of the second shift register output port 2 outputs, with this signal after FFT transforms to frequency domain, pilot packet signal in the signal is separated with data packet signals, the output port 2 of the second pilot data frequency domain separator is sent into data packet signals 3 input ports 1 of the pilot packet signal being sent into the 8th shift register of output port of input port 1, the second pilot data frequency domain separator of the 7th shift register; The input port 4 of decision feedback equalization unit sent into data packet signals respectively by the 7th shift register by output port 2 after time-delay; The 8th shift register is sent into the second input port 1 to multiplier with the pilot packet signal by output port 2 after time-delay; The second read-only memory will the data sequence relevant with frequency domain phase shift orthogonal sequence be exported to the input port 2 of the second multiplier by output port 1; The second multiplier is finished the multiplying from the two-way input data of input port 1 and input port 2, respectively operation result is sent into the input port 1 of the second to IFFT converter by output port 3; After the 2nd IFFT converter will change back to time domain from the input data of input port 1, cut apart the two-way channel information in time domain respectively, and the two-way channel information after will cutting apart is sent into respectively each input port 1 of the 9th to the tenth shift register by output port 2 and output port 3; The the 9th to the tenth shift register after the alignment of two-way channel information, is sent into each path channels information respectively the input port 1 of the 3rd to the 4th FFT converter through time-delay by output port 2; After the 3rd to the 4th FFT converter will become frequency domain again from the channel information of input port 1, again each road frequency domain channel information is sent into respectively the input port 1 of the 3rd to the 4th channel interpolation device by output port 2; The the 3rd to the 4th channel interpolation device carries out interpolative operation to the frequency domain channel information of input, and operation result is then sent into respectively the input port 5,6 of decision feedback equalization unit by output port 2.
Described decision feedback equalization unit is made of to interference estimator between second adder, the first to second time domain decision device, the first to second residue code MMSE joint equalization device, the 3rd to the 4th IFFT converter, the 11 to the 12 shift register, first;
MMSE joint equalization device input port 1,4 receives respectively the frequency domain data packet signal of the 3rd and the 7th shift register output port 2 outputs, and the input port 2,3,5,6 of MMSE joint equalization device links to each other with each output port 2 of first to fourth channel interpolation device respectively; The frequency domain data signal that the output port 7 of MMSE joint equalization device, 8 will be finished the MMSE joint equalization is sent into respectively the input port 1 of the 3rd to the 4th IFFT converter; The the 3rd to the 4th IFFT converter transforms to time domain with the frequency domain data signal of input, sends into respectively the input port 1 of the 11 to the 12 shift register by output port 2; The 11 to the 12 shift register is by output port 2, will repeat identical time domain data packet signal respectively to be sent to first to the input port of second adder 1 twice, between twice delivery time suitable time-delay arranged; When the 11 to the 12 shift register sends the time domain data packet signal for the first time, the first input port 2 to second adder is input as 0, is equivalent to directly the input signal of input port 1 be sent into by output port 3 input port 1 of the first to second time domain decision device; The first to second time domain decision device carries out the judgement first time to the time domain data packet signal from input port 1 respectively, and this court verdict is sent into respectively the input port 1 of interference estimator between the first to second residue code by output port 2; The court verdict that interference estimator utilizes input port 1 to input between the first to second residue code obtains the time domain estimated value of residual intersymbol interference, and this estimated value is sent into respectively the first input port 2 to second adder by output port 2; At this moment, the 11 to the 12 shift register sends the time domain data packet signal for the second time, first to second adder with input port 1,2 input signal addition, from the time domain data packet signal, eliminate the adverse effect of residual intersymbol interference, and operation result is exported to respectively the input port 1 of the first to second time domain decision device; The first to second time domain decision device carries out second time judgement to the time domain data packet signal from input port 1, exports respectively this court verdict to port C, D.
First utilizes frequency domain phase shift orthogonal sequence as channel estimation sequence to the second channel estimation unit, obtains multiplex (MUX) information from the reception signal of aliasing.
The multiplex (MUX) information butt joint that decision feedback equalization unit by using first to second channel estimation unit obtains is collected mail and number is carried out the MMSE joint equalization, and utilizes between residue code the Interference Estimation value to carry out disturbing between residue code before judgement and eliminate.
Used a plurality of shift registers, FFT converter, IFFT converter among the present invention, and the devices such as adder, multiplier, they enable with termination signal flow in order to guarantee signal all by the unified control of a synchronous state machine.
The present invention compares background technology and has following advantage:
1. the present invention adopts frequency domain phase shift orthogonal sequence as channel estimation sequence, and the channel estimation sequence of two-way transmitted signal can send simultaneously, can effectively simplify the transmission frame structure, reduces redundancy, improves band efficiency.
2. the present invention is behind the channel information that obtains the channel estimation sequence delivery time, utilize interpolation algorithm, try to achieve the channel information of packet delivery time, adopt associating MMSE balanced to the two paths of data packet signal, the MMSE equalization algorithm performance that adopts in its equalization performance and the traditional single-shot list receipts single-carrier frequency domain equalization system is suitable.
3. among the present invention, each time domain data grouping that register 17-1,17-2 will unite after the MMSE equilibrium repeats to send twice, sends for the first time to be used for first judgement, and utilizes this decision value to come the residual intersymbol interference of reconstruct; For the second time be sent to adder, before second judgement, eliminate the residual intersymbol interference in the packet, to reduce the error rate.
4. the present invention both can be used for the multiplexing MIMO diversity that also can be used for of MIMO, and can switch under two kinds of patterns according to the channel conditions under the environment for use, used flexibly, and adaptive capacity to environment is strong.
Description of drawings
Fig. 1 is electric functional-block diagram of the present invention.
Fig. 2 is that the present invention first is to the electric functional-block diagram of second channel estimation unit and decision feedback equalization unit.
Embodiment
Referring to figs. 1 through Fig. 2, the present invention includes the first to second withdrawal device 1-1 to 1-2, the first to second frame synchronizer 2-1 to 2-2, the first to second sampling phase tracker 3-1 to 3-2 and the first to second shift register 4-1 to 4-2, also comprise first to second channel estimation unit 5-1 to 5-2 and decision feedback equalization unit 6; As shown in Figure 1, Fig. 1 is electric functional-block diagram of the present invention, and embodiment presses Fig. 1 connection line.Wherein the effect of the first to second withdrawal device 1-1 to 1-2 is to carry out sending into the first to second frame synchronizer 2-1 to 2-2 after over-sampling extracts through the reception signal A behind the analog/digital converter A/D and B; The effect of the first to second frame synchronizer 2-1 to 2-2 is to carry out frame synchronization, and output synchronous indicating signal control the first to second sampling phase tracker 3-1 to 3-2 and the first to second shift register 4-1 to 4-2 start working after the frame synchronization success; The effect of the first to second sampling phase tracker 3-1 to 3-2 is that the optimum sampling phase place is followed the tracks of, and output optimum sampling phase place can correctly sample it to the first to second withdrawal device 1-1 to 1-2; The effect of the first to second shift register 4-1 to 4-2 is that the oversampled signals of input is delayed time; The first effect to second channel estimation unit 5-1 to 5-2 is the multiplex (MUX) information that obtains the packet delivery time; The effect of decision feedback equalization unit 6 is to utilize the channel information of trying to achieve, and carries out decision feedback equalization to receiving packet; The Stratix Series FPGA chip manufacturing that embodiment the first to second withdrawal device 1-1 to 1-2, the first to second frame synchronizer 2-1 to 2-2, the first to second sampling phase tracker 3-1 to 3-2 and the first to second shift register 4-1 to 4-2 all adopt U.S. altera corp to produce.
The present invention first is the multiplex (MUX) information that obtains the packet delivery time to the effect of second channel estimation unit 5-1 to 5-2; The first channel estimating unit 5-1 is made of the first pilot data frequency domain separator 7-1, the 3rd to the 4th shift register 8-1 to 8-2, the first read-only memory 9-1, the first multiplier 10-1, an IFFT converter 11-1, the 5th to the 6th shift register 12-1 to 12-2, the first to the 2nd FFT converter 13-1 to 13-2 and first to second channel interpolater 14-1 to 14-2; Second channel estimation unit 5-2 is made of the second pilot data frequency domain separator 7-2, the 7th to the 8th shift register 8-3 to 8-4, the second read-only memory 9-2, the second multiplier 10-2, the 2nd IFFT converter 11-2, the 9th to the tenth shift register 12-3 to 12-4, the 3rd to the 4th FFT converter 13-3 to 13-4 and the 3rd to the 4th channel interpolation device 14-3 to 14-4.
The effect of decision feedback equalization of the present invention unit 6 is to utilize the channel information of trying to achieve, and carries out decision feedback equalization to receiving packet; It is made of interference estimator 20-1 to 20-1 between MMSE joint equalization device 15, the 3rd to the 4th IFFT converter 16-1 to 16-2, the 11 to the 12 shift register 17-1 to 17-2, the first to second adder 18-1 to 18-2, first to second time domain decision device 19-1 to 19-2, the first to second residue code;
As shown in Figure 2, Fig. 2 is the present invention first to the electric functional-block diagram of second channel estimation unit 5-1 to 5-2 with decision feedback equalization unit 6, and embodiment presses Fig. 2 connection line.Wherein the effect of the first to second pilot data frequency domain separator 7-1 to 7-2 is that the reception signal after the correct sampling of two-way is transformed to frequency domain, and according to sending frame structure, packet in every frame is separated with pilot packet, the 3rd shift register 8-1 and the 7th shift register 8-3 are sent into respectively in packet, pilot packet is sent into respectively the 4th shift register 8-2 and the 8th shift register 8-4; The effect of the 3rd to the 4th shift register 8-1 to 8-2 and the 7th to the 8th shift register 8-3 to 8-4 is that packet or the pilot packet of input are delayed time; The effect of the first to second read-only memory 9-1 to 9-2 is to carve in due course the output data sequence relevant with channel estimation sequence to the first to second multiplier 10-1 to 10-2; The effect of the first to second multiplier 10-1 to 10-2 is carried out multiplying to 1,2 data from input port; The effect of the first to the 2nd IFFT converter 11-1 to 11-2 is that the operation result with the first to second multiplier 10-1 to 10-2 transforms to time domain; The effect of the 5th to the 6th shift register 12-1 to 12-2 and the 9th to the tenth shift register 12-3 to 12-4 is that the multichannel time domain channel information of input is delayed time; The effect of first to fourth FFT converter 13-1 to 13-4 is that frequency domain is arrived in the multichannel time domain channel information conversion of input; The effect of first to fourth channel interpolation device 14-1 to 14-4 is the channel information that estimates the packet delivery time according to the channel information of pilot packet delivery time;
The effect of MMSE joint equalization device 15 is to utilize multiplex (MUX) information that the two paths of data packet signal is carried out the MMSE joint equalization; The effect of the 3rd to the 4th IFFT converter 16-1 to 16-2 is that the packet behind the MMSE joint equalization is transformed to time domain; The effect of the 11 to the 12 shift register 17-1 to 17-2 be with the time domain data packet signal through suitable time-delay, send to first to second adder 18-1 to 18-2 twice; The first effect to second adder 18-1 to 18-2 is that the first time domain data packet signal that receives is directly sent to the first to second time domain decision device 19-1 to 19-2, and sends to the first to second time domain decision device 19-1 to 19-2 behind the signal plus of the time domain data packet signal that will receive for the second time and input port 2 inputs; The effect of the first to second time domain decision device 19-1 to 19-2 is that the data packet signal is adjudicated in time domain; The effect of interference estimator 20-1 to 20-1 is the time thresholding of utilizing the residual intersymbol interference of first decision value reconstruct of the first to second time domain decision device 19-1 to 19-2 between the first to second residue code; Embodiment first all adopts the Stratix Series FPGA chip manufacturing of U.S. altera corp production to second channel estimation unit 5-1 to 5-2 and decision feedback equalization unit 6.
The concise and to the point operation principle of the present invention is as follows:
The first to second withdrawal device carries out the over-sampling extraction to the reception signal A behind analog/digital converter A/D and B; Reception signal after extracting is sent into the first to second frame synchronizer carry out frame synchronization, startup the first to second sampling phase tracker and the first to second shift register are started working after the frame synchronization success, and the oversampled signals that will finish after the frame synchronization is sent in the first to second shift register; The first to second sampling phase tracker then is that the optimum sampling phase place is followed the tracks of, and output optimum sampling phase place can correctly sample it to the first to second withdrawal device; The first to second shift register is delayed time the oversampled signals of input, gives first to the second channel estimation unit; The first oversampled signals that receives to the utilization of second channel estimation unit obtains the multiplex (MUX) information of packet delivery time, and sends it to the decision feedback equalization unit; The decision feedback equalization unit then utilizes multiplex (MUX) information, carry out decision feedback equalization to receiving packet, and the output time-domain decision value is to port C, D.
Claims (3)
1. single carrier frequency domain equalization device based on MIMO, it comprises the first to second withdrawal device (1-1,1-2), the first to second frame synchronizer (2-1,2-2), the first to second sampling phase tracker (3-1,3-2) and the first to second shift register (4-1,4-2), it is characterized in that: also comprise first to second channel estimation unit (5-1,5-2) and decision feedback equalization unit (6);
The input port 1 of described the first to second withdrawal device (1-1,1-2) links to each other with B with oversampled signals stream A respectively, the input port 3 of the first to second withdrawal device (1-1,1-2) receives respectively the sampling location control signal of the first to second sampling phase tracker (3-1,3-2) output port 3 outputs, carries out over-sampling and extracts the rear input port 1 that is exported respectively to the first to second frame synchronizer (2-1,2-2) by the output port 2 of the first to second withdrawal device (1-1,1-2); Signal after the first to second frame synchronizer (2-1,2-2) extracts over-sampling carries out frame synchronization, the first to second frame synchronizer (2-1,2-2) output port 2 exports the frame synchronization index signal to respectively the enabling signal port one of the first to second sampling phase tracker (3-1,3-2), and the first to second frame synchronizer (2-1,2-2) output port 3 exports the frame synchronization index signal to respectively the enabling signal port one of the first to second shift register (4-1,4-2); The input port 2 of the first to second sampling phase tracker (3-1,3-2) receives respectively oversampled signals stream A and B, constantly adjust timing phase by the cumlative energy of more a plurality of symbol sample values again, and by output port 3 correct sampling phase is returned to withdrawal device (1-1,1-2); Export the first output port 1 to second channel estimation unit (5-1,5-2) to by output port 2 respectively behind the signal lag after the first to second shift register (4-1,4-2) will correctly be sampled; The output port 2,3,4 of the first channel estimating unit (5-1) links to each other with the input port 1,2,3 of decision feedback equalization unit (6) respectively, the output port 2,3,4 of second channel estimation unit (5-2) links to each other with the input port 4,5,6 of decision feedback equalization unit (6) respectively, the first oversampled signals that receives to the utilization of second channel estimation unit obtains the multiplex (MUX) information of packet delivery time, and sends it to the decision feedback equalization unit; The output port 7,8 of decision feedback equalization unit (6) links to each other with port C, D respectively, and decision feedback equalization unit by using multiplex (MUX) information carry out decision feedback equalization to receiving packet, and the output time-domain decision value is to port C, D;
Described the first channel estimating unit (5-1) is by the first pilot data frequency domain separator (7-1), the the 3rd to the 4th shift register (8-1,8-2), the first read-only memory (9-1), the first multiplier (10-1), the one IFFT converter (11-1), the the 5th to the 6th shift register (12-1,12-2), the first to the 2nd FFT converter (13-1,13-2) with first to second channel interpolater (14-1,14-2) consist of;
The first pilot data frequency domain separator (7-1) input port 1 in described the first channel estimating unit (5-1) receives the oversampled signals of the first shift register (4-1) output port 2 outputs, with this signal after FFT transforms to frequency domain, pilot packet signal in the signal is separated with data packet signals, the output port 2 of the first pilot data frequency domain separator (7-1) is sent into data packet signals 3 input ports 1 of the pilot packet signal being sent into the 4th shift register (8-2) of output port of input port 1, the first pilot data frequency domain separator (7-1) of the 3rd shift register (8-1); The input port 1 of decision feedback equalization unit (6) sent into data packet signals by the 3rd shift register (8-1) by output port 2 after time-delay; The input port 1 of the first multiplier (10-1) sent into the pilot packet signal by the 4th shift register (8-2) by output port 2 after time-delay; The first read-only memory (9-1) will the data sequence relevant with frequency domain phase shift orthogonal sequence be exported to the input port 2 of the first multiplier (10-1) by output port 1; The first multiplier (10-1) is finished the multiplying from the two-way input data of input port 1 and input port 2, operation result is sent into the input port 1 of an IFFT converter (11-1) by output port 3; After the one IFFT converter (11-1) will change back to time domain from the input data of input port 1, cut apart the two-way channel information in time domain, and the two-way channel information after will cutting apart is sent into respectively each input port 1 of the 5th and the 6th shift register (12-1,12-2) by output port 2 and output port 3; The the 5th and the 6th shift register (12-1,12-2) after the alignment of two-way channel information, is sent into each path channels information respectively the input port 1 of the first and second FFT converters (13-1,13-2) through time-delay by output port 2; After the first and second FFT converters (13-1,13-2) will become frequency domain again from the channel information of input port 1, again each road frequency domain channel information is sent into respectively the input port 1 of the first and second channel interpolation devices (14-1,14-2) by output port 2; The first and second channel interpolation devices (14-1,14-2) carry out interpolative operation to the frequency domain channel information of input, and operation result is then sent into respectively the input port 2,3 of decision feedback equalization unit (6) by output port 2;
Described second channel estimation unit (5-2) is by the second pilot data frequency domain separator (7-2), the the 7th to the 8th shift register (8-3,8-4), the second read-only memory (9-2), the second multiplier (10-2), the 2nd IFFT converter (11-2), the the 9th to the tenth shift register (12-3,12-4), the the 3rd to the 4th FFT converter (13-3,13-4) with the 3rd to the 4th channel interpolation device (14-3,14-4) consist of;
The second pilot data frequency domain separator (7-2) input port 1 in the described second channel estimation unit (5-2) receives the oversampled signals of the second shift register (4-2) output port 2 outputs, with this signal after FFT transforms to frequency domain, pilot packet signal in the signal is separated with data packet signals, the output port 2 of the second pilot data frequency domain separator (7-2) is sent into data packet signals 3 input ports 1 of the pilot packet signal being sent into the 8th shift register (8-4) of output port of input port 1, the second pilot data frequency domain separator (7-2) of the 7th shift register (8-3); The input port 4 of decision feedback equalization unit (6) sent into data packet signals by the 7th shift register (8-3) by output port 2 after time-delay; The input port 1 of the second multiplier (10-2) sent into the pilot packet signal by the 8th shift register (8-4) by output port 2 after time-delay; The second read-only memory (9-2) will the data sequence relevant with frequency domain phase shift orthogonal sequence be exported to the input port 2 of the second multiplier (10-2) by output port 1; The second multiplier (10-2) is finished the multiplying from the two-way input data of input port 1 and input port 2, operation result is sent into the input port 1 of the 2nd IFFT converter (11-2) by output port 3; After the 2nd IFFT converter (11-2) will change back to time domain from the input data of input port 1, cut apart the two-way channel information in time domain, and the two-way channel information after will cutting apart is sent into respectively each input port 1 of the 9th to the tenth shift register (12-3,12-4) by output port 2 and output port 3; The the 9th to the tenth shift register (12-3,12-4) after the alignment of two-way channel information, is sent into each path channels information respectively the input port 1 of the 3rd to the 4th FFT converter (13-3,13-4) through time-delay by output port 2; After the 3rd to the 4th FFT converter (13-3,13-4) will become frequency domain again from the channel information of input port 1, again each road frequency domain channel information is sent into respectively the input port 1 of the 3rd to the 4th channel interpolation device (14-3,14-4) by output port 2; The the 3rd to the 4th channel interpolation device (14-3,14-4) carries out interpolative operation to the frequency domain channel information of input, and operation result is then sent into respectively the input port 5,6 of decision feedback equalization unit (6) by output port 2;
Described decision feedback equalization unit (6) is made of to interference estimator (20-1,20-1) between second adder (18-1,18-2), the first to second time domain decision device (19-1,19-2), the first to second residue code MMSE joint equalization device (15), the 3rd to the 4th IFFT converter (16-1,16-2), the 11 to the 12 shift register (17-1,17-2), first;
MMSE joint equalization device (15) input port 1,4 receives respectively the frequency domain data packet signal of the 3rd and the 7th shift register (8-1,8-3) output port 2 outputs, and the input port 2,3,5,6 of MMSE joint equalization device (15) links to each other with each output port 2 of first to fourth channel interpolation device (14-1,14-2,14-3,14-4) respectively; The frequency domain data signal that the output port 7 of MMSE joint equalization device (15), 8 will be finished the MMSE joint equalization is sent into respectively the input port 1 of the 3rd to the 4th IFFT converter (16-1,16-2); The the 3rd to the 4th IFFT converter (16-1,16-2) transforms to time domain with the frequency domain data signal of input, sends into respectively the input port 1 of the 11 to the 12 shift register (17-1,17-2) by output port 2; The 11 to the 12 shift register (17-1,17-2) is by output port 2, respectively identical time domain data packet signal is repeated to be sent to first to the input port of second adder (18-1,18-2) 1 twice, between twice delivery time suitable time-delay is arranged; When the 11 to the 12 shift register (17-1,17-2) sends the time domain data packet signal for the first time, the first input port 2 to second adder (18-1,18-2) is input as 0, is equivalent to directly the input signal of input port 1 be sent into by output port 3 input port 1 of the first to second time domain decision device (19-1,19-2); The first to second time domain decision device (19-1,19-2) carries out the judgement first time to the time domain data packet signal from input port 1 respectively, and this court verdict is sent into respectively the input port 1 of interference estimator between the first to second residue code (20-1,20-2) by output port 2; The court verdict that interference estimator between the first to second residue code (20-1,20-2) utilizes input port 1 to input obtains the time domain estimated value of residual intersymbol interference, and this estimated value is sent into respectively the first input port 2 to second adder (18-1,18-2) by output port 2; At this moment, the 11 to the 12 shift register (17-1,17-2) sends the time domain data packet signal for the second time, first to second adder (18-1,18-2) with input port 1,2 input signal addition, from the time domain data packet signal, eliminate the adverse effect of residual intersymbol interference, and operation result is exported to respectively the input port 1 of the first to second time domain decision device (19-1,19-2); The first to second time domain decision device (19-1,19-2) carries out second time judgement to the time domain data packet signal from input port 1, exports respectively this court verdict to port C, D.
2. the single carrier frequency domain equalization device based on MIMO according to claim 1, it is characterized in that: first utilizes frequency domain phase shift orthogonal sequence as channel estimation sequence to second channel estimation unit (5-1,5-2), obtains multiplex (MUX) information from the reception signal of aliasing.
3. the single carrier frequency domain equalization device based on MIMO according to claim 1 and 2, it is characterized in that: decision feedback equalization unit (6) utilize the first multiplex (MUX) information butt joint that obtains to second channel estimation unit (5-1,5-2) to collect mail number to carry out the MMSE joint equalization, and utilize between residue code the Interference Estimation value to carry out disturbing between residue code before judgement and eliminate.
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