CN102044419B - Preparation method of Si-Ge film and manufacture method of semiconductor device - Google Patents
Preparation method of Si-Ge film and manufacture method of semiconductor device Download PDFInfo
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- CN102044419B CN102044419B CN2009101974537A CN200910197453A CN102044419B CN 102044419 B CN102044419 B CN 102044419B CN 2009101974537 A CN2009101974537 A CN 2009101974537A CN 200910197453 A CN200910197453 A CN 200910197453A CN 102044419 B CN102044419 B CN 102044419B
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Abstract
The invention relates to a preparation method of a Si-Ge film and a manufacture method of a semiconductor device. The preparation method of the Si-Ge film comprises the following steps of: providing a substrate and forming a grid electrode on the substrate surface and comprehension layers arranged at both sides of the grid electrode; etching the substrate at one side of the grid electrode far from the comprehension layers to form a groove; baking the groove at a temperature from 828 DEG C to 850 DEG C and then forming a Si-Ge layer covering the groove. By setting a suitable baking temperature and baking time, a Si-Ge interface in favorable shape is obtained and the product quality is improved.
Description
Technical field
The manufacturing method of semiconductor device that the present invention relates to the germanium-silicon thin membrane preparation method and use said germanium-silicon thin membrane preparation method.
Background technology
Germanium silicon (Si1-xGex) material is the instead type solid solution that infinitely dissolves each other that silicon and germanium form through covalent bonds.Germanium silicon material generally has amorphous, polycrystalline, monocrystalline and four kinds of forms of superlattice; Since its have carrier mobility height, bandwidth with the change of component of germanium advantage such as continuously adjustable; And can be compatible mutually with the silicon planner technology of present maturation; Therefore, germanium silicon material can be widely used in multiple devices such as making high speed HBT (HBT), modulation-doped field effect pipe (MODFET), photo-detector aspect microelectronics and the photoelectron.
The application of germanium silicon material during integrated circuit is made in modern times be very extensively: for example can mix the Ge element of certain component through the base at HBT; Thereby reduce bandwidth; Reduce the potential barrier of base minority carrier from the emitter region to the base, improve emission effciency and current amplification factor; In addition, for 45 nanometer technology nodes and following PMOS technology, owing to reducing significantly of device size; The junction depth of source-drain electrode is more and more shallow; Usually after source-drain electrode carries out silicon etching, form the germanium silicon layer, to fill the groove of institute's etching through epitaxy technique; The stress of reply raceway groove improves the mobility in hole.
In concrete technology, carry out before the germanium and silicon epitaxial, need carry out preliminary treatment to silicon substrate usually, this mainly is because the pollution that surface of silicon can produce one deck natural oxidizing layer and some other impurity.For the quality of the germanium and silicon epitaxial layer that guarantees to grow in surface of silicon, usually before epitaxial growth Ge-Si, the method that adopts high-temperature baking reacts silicon dioxide and the silicon of surface of silicon, forms to be prone to the silicon monoxide that gasifies.Extract silicon monoxide and other pollutants after the gasification out reaction chamber, thereby obtain the complete surface of silicon of cleaning, for next step epitaxial growth creates favorable conditions.Application number is 200510050891.2, name is called the epitaxial preparation method that discloses a kind of germanium-silicon thin membrane in the one Chinese patent application of " a kind of preparation method of selective epitaxial germanium-silicon thin membrane "; Wherein, Before epitaxial growth Ge-Si, silicon substrate is put in the thermal oxidation furnace, and feeds pure oxygen; In temperature is under 900-1200 degree centigrade, the oxidation growth layer of silicon dioxide.
Yet; With reference to the people such as H.Aikawa of Toshiba in 2008 Institute of Electrical and Electric Engineers (IEEE) ultra-large semiconductor integrated circuit technical seminar (Symposium on VLSITechnology Digest of Technical Papers) on the paper (" Variability AwareModeling and Characterization in Standard Cell in 45nm CMOS with StressEnhancement Technique ") delivered; Specifically; With reference to figure 1; When employing is higher than after 900 degrees centigrade temperature toasts silicon substrate; Deposit Germanium is to form as the germanium silicon layer again, and the interface 101 of said germanium silicon layer and silicon substrate will become arc.This is because high-temperature baking technology makes the mobility of silicon atom be greatly improved; Under the effect of stress; Produce the mismatch dislocation on the interface of germanium silicon layer and silicon substrate; Form arc-shaped interface, and the germanium silicon layer interface 101 with arc will increase raceway groove 102 length of the actual process of charge carrier, thereby influence device performance.In addition,, for example be lower than 600 degrees centigrade temperature, silicon substrate is handled, can't remove the impurity component of silicon face, influence contacting of germanium silicon interface and silicon face, thereby influence device subsequent technique and product quality when adopting low temperature.
Summary of the invention
The technical problem that the present invention solves provides a kind of germanium-silicon thin membrane preparation method, before germanium and silicon epitaxial, adopts suitable baking temperature that silicon substrate is handled, and so that the interface of the germanium silicon layer with excellent in shape to be provided, improves product quality.
For solving the problems of the technologies described above, the invention provides a kind of germanium-silicon thin membrane preparation method, comprise at least: substrate is provided, the layer of compensation that said substrate surface is formed with grid and is positioned at the grid both sides; Said layer of compensation away from a side substrate of said grid in etching form groove; Adopt 828 degrees centigrade to 850 degrees centigrade temperature, said groove is toasted, then, form the germanium silicon layer that covers said groove.
In addition, the present invention also provides a kind of manufacturing method of semiconductor device, comprising: substrate is provided, the layer of compensation that said substrate surface is formed with grid and is positioned at the grid both sides; Form side wall at said layer of compensation away from said grid one side; Said side wall away from a side substrate of said grid in etching form groove; Adopt 828 degrees centigrade to 850 degrees centigrade temperature conditions, said groove is toasted, then, form the germanium silicon layer that covers said groove; Said germanium silicon layer is carried out ion doping, to be formed with the source region.
Compared with prior art, the present invention has the following advantages: before growth germanium silicon layer, through rational baking temperature is set; And adopt rational stoving time; Silicon substrate is toasted, and the migration rate of control silicon atom cleans surface of silicon simultaneously; Thereby the germanium silicon interface that acquisition has excellent in shape has improved product quality.
Description of drawings
Fig. 1 is the generalized section at existing arc germanium silicon layer interface;
Fig. 2 is the schematic flow sheet of a kind of execution mode of germanium-silicon thin membrane preparation method of the present invention;
Fig. 3 to Fig. 5 adopts a kind of embodiment of germanium-silicon thin membrane preparation method of the present invention to form the generalized section of germanium silicon layer forming process;
Fig. 6 is the schematic flow sheet of a kind of manufacturing method of semiconductor device execution mode provided by the present invention.
Embodiment
The invention provides a kind of germanium-silicon thin membrane preparation method, comprise the steps: at least before the germanium-silicon thin membrane under temperature is 828 degrees centigrade to 850 degrees centigrade condition, silicon substrate to be toasted in growth.According to embodiment of the present invention, can form germanium silicon layer interface with better shape, improve product quality.
With reference to figure 2, in a kind of embodiment of germanium-silicon thin membrane preparation method of the present invention, can comprise the steps: at least
Step S1 provides substrate, and said substrate surface is formed with grid and is positioned at the layer of compensation of grid both sides (Off-set Layer);
Step S2, said layer of compensation away from a side substrate of said grid in etching form groove;
Step S3 adopts 828 degrees centigrade to 850 degrees centigrade temperature, and said groove is toasted, and then, forms the germanium silicon layer that covers said groove.
Below in conjunction with accompanying drawing and specific embodiment, germanium-silicon thin membrane preparation method execution mode of the present invention is elaborated.
With reference to figure 3, substrate 100 is provided, the layer of compensation 110 that said substrate surface is formed with grid 200 and is positioned at grid 200 both sides.
Said substrate 100 can be substrate (part that comprises integrated circuit and other elements), the patterning of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes or the substrate that is not patterned.Said grid 200 can be polysilicon etc.
Said layer of compensation 110 materials can adopt for example silicon nitride.What need to specify is, said layer of compensation 110 also can be selected other material for use, the operate as normal of the device that forms not influencing, and layer of compensation 110 material chosen should not cause undue restriction to protection scope of the present invention.
The formation technology of said layer of compensation 110 can be selected known technology for use, can adopt different processes according to the material of being selected for use is different, and technological parameter is adjusted, and does not give unnecessary details at this.
With reference to figure 4, S2 is said like step, said layer of compensation 110 away from a side substrate of said grid 200 in etching form groove 120.
The formation technology of said groove 120 can be selected known physical etchings or chemical etching technology for use.In embodiment,, can adopt dry etch process in order to obtain border profile preferably.
For example; But using plasma dry etching; Specifically, etching cavity pressure can be 10mTorr (millitorr) to 50mTorr, the top radio-frequency power that is used to produce plasma be 200w (watt) to 500w; The bottom radio-frequency power that is used to control the plasma ion direction is 50w to 150w, and the etching gas of employing comprises: CHF
3, its flow be 20sccm (per minute standard cubic centimeter) to 40sccm, and CH
2F
2, its flow is 25sccm to 50sccm and oxygen, its flow is 20sccm to 40sccm.
With reference to figure 5, S3 is said like step, at first, said groove 120 is toasted.Wherein, can be set to 828 degrees centigrade to 850 degrees centigrade by baking temperature, stoving time is 60 seconds to 120 seconds.Then, on groove 120, form the germanium silicon layer 130 that covers groove 120, specifically, can adopt selective epitaxial growth process,, avoid harmful effect raceway groove with the connection interface that acquisition has excellent in shape.
The inventor finds that through long-term experiment repeatedly and summary said baking temperature is set to 828 degrees centigrade to 850 degrees centigrade, can suppress the migration of silicon atom effectively, thereby avoid forming the germanium silicon layer interface of arc, improves product quality.
In a kind of specific embodiment, the formed angle in the sidewall of said groove and bottom is 95 degree, then, adopts temperature T 1-T3 that substrate is toasted respectively.Wherein, T1 is 828 degrees centigrade, and T2 is 835 degrees centigrade, and T3 is 850 degrees centigrade, and stoving time is set to 120 seconds.Then, adopt formation germanium silicon layer in the groove of same epitaxy technology in said substrate respectively.
After also epitaxial growth covered the germanium silicon layer of said groove after the temperature (more than 900 degrees centigrade) of employing prior art was toasted, the formed angle of sidewall and bottom was greater than 140 degree in the said germanium silicon layer; And after adopting the T1 temperature to toast, the formed angle of sidewall and bottom is 103.7 degree in the formed germanium silicon layer; After adopting the T2 temperature to toast, the formed angle of sidewall and bottom is 105 degree in the formed germanium silicon layer; After adopting the T3 temperature to toast, the formed angle of sidewall and bottom is 135.5 degree in the formed germanium silicon layer.
When baking temperature raise, the migration rate of silicon atom raise with temperature and increases, at germanium silicon layer and silicon substrate at the interface; Silicon atom and germanium atom have produced the coupling dislocation; Make the formed angle of sidewall and bottom of germanium silicon layer increase gradually, the germanium silicon interface becomes arc gradually, produces difference thereby make near the raceway groove of substrate surface and length near the raceway groove of substrate interior; Make the channel length of the actual process of charge carrier that variation take place, and then have influence on device performance.
The inventor finds in experiment; When baking temperature is lower than 828 when spending, the silicon dioxide of silicon face and the sluggish between the silicon, and the gasification of the silicon monoxide that is unfavorable for being generated; It is residual to make that silicon face is easy to generate impurity, and can't form good germanium silicon interface.And when baking temperature surpassed 850 degrees centigrade, the angle of formed germanium silicon layer sidewall and bottom will be above 135 degree, and the influence that the length variations of raceway groove both sides is brought can't be left in the basket.Therefore, when the temperature that adopts 828 degrees centigrade to 850 degrees centigrade is baking temperature, not only can clean silicon face preferably, be beneficial to the formation of germanium silicon interface, and arcization that can also the germanium silicon interface, to avoid harmful effect to raceway groove.
In a kind of specific embodiment, the formed angle in the sidewall of said groove and bottom is 95 degree, then; Adopt 835 degrees centigrade temperature that substrate is toasted, stoving time is set to t11 respectively, t12, t13 and t14; Wherein, t11 is 60 seconds, and t12 is 90 seconds; T13 is 120 seconds, and t14 is 180 seconds.Then, adopt formation germanium silicon layer in the groove of same epitaxy technology in said substrate respectively.
Toasted t11 after the time, the angle that sidewall and bottom form in the formed germanium silicon layer is 102 degree; Toasted t12 after the time, the angle that sidewall and bottom form in the formed germanium silicon layer is 100 degree; Toasted t13 after the time, the angle that sidewall and bottom form in the formed germanium silicon layer is 105 degree.And having toasted t14 after the time, the angle that sidewall and bottom form in the formed germanium silicon layer will be above 140 degree.
The baking of proper temperature and the stoving time that adopts appropriateness can promote the reaction of the silicon dioxide and the silicon atom of surface of silicon, produce the silicon monoxide that is prone to gasification; With clean silicon surface, promote the germanium that is deposited to combine, and then form germanium silicon interface with excellent in shape with the further of silicon substrate; Yet after having prolonged stoving time, the migration rate of silicon atom is exacerbated; Make that the coupling dislocation of germanium and silicon is serious, thereby cause the distortion of germanium silicon interface.
In addition, in bake process, can in annealing furnace, feed protective gas, avoiding in the hot environment, oxygen and device produce bad reaction, and said protective gas can be hydrogen specifically.
After said groove toasted, can adopt the said germanium silicon layer of selective epitaxial technology growth.For example, in specific embodiment, the pressure of epitaxial Germanium silicon layer technology is 5Torr to 50Torr, and temperature is 600 degrees centigrade to 800 degrees centigrade, and adopting flow is the SiH of 50sccm to 150sccm
4Perhaps SiH
2Cl
2As the silicon source, flow be the germanic mist of 5sccm to 100sccm as the germanium source, wherein, GeH
4Account for 10%, H
2Account for 90%, flow is the removing gas of the HCl of 50sccm to 200sccm as the germanium silicon layer.
Compared to prior art, germanium-silicon thin membrane preparation method of the present invention is before forming the germanium silicon layer, through rational baking temperature is set; And adopt rational stoving time; Silicon substrate is toasted, and the migration rate of control silicon atom cleans surface of silicon simultaneously; Thereby the germanium silicon interface that acquisition has excellent in shape has improved product quality.
In addition, with reference to figure 6, the present invention also provides a kind of manufacturing method of semiconductor device of using above-mentioned germanium-silicon thin membrane preparation method, comprises the steps: at least
Step S101 provides substrate, the layer of compensation that said substrate surface is formed with grid and is positioned at the grid both sides;
Step S102 forms side wall at said layer of compensation away from said grid one side;
Step S103, said side wall away from a side substrate of said grid in etching form groove;
Step S104 adopts 828 degrees centigrade to 850 degrees centigrade temperature conditions, and said groove is toasted, and then, forms the germanium silicon layer that covers said groove;
Step S105 carries out ion doping to said germanium silicon layer, to be formed with the source region.
Owing to adopt 828 degrees centigrade to 850 degrees centigrade baking temperature; Make formed germanium silicon layer interface have good profile; Thereby can overcome the stress of raceway groove between the source-drain electrode; Avoid channel length to increase and produce very big variation, and then influence the performance of formed semiconductor device with its degree of depth.
Though the present invention through the preferred embodiment explanation as above, these preferred embodiments are not in order to limit the present invention.Those skilled in the art is not breaking away from the spirit and scope of the present invention, should have the ability various corrections and additional are made in this preferred embodiment, and therefore, protection scope of the present invention is as the criterion with the scope of claims.
Claims (8)
1. a germanium-silicon thin membrane preparation method is characterized in that, comprises at least:
Substrate is provided, the layer of compensation that said substrate surface is formed with grid and is positioned at the grid both sides;
Said layer of compensation away from a side substrate of said grid in etching form groove;
Adopt 828 degrees centigrade to 850 degrees centigrade temperature, said groove is toasted, then, form the germanium silicon layer that covers said groove.
2. germanium-silicon thin membrane preparation method as claimed in claim 1 is characterized in that, said stoving time is 60 seconds to 120 seconds.
3. germanium-silicon thin membrane preparation method as claimed in claim 2 is characterized in that, said stoving time is 90 seconds.
4. germanium-silicon thin membrane preparation method as claimed in claim 2 is characterized in that, said groove forms through dry etching method.
5. germanium-silicon thin membrane preparation method as claimed in claim 1 is characterized in that, the angle of formed germanium silicon layer sidewall and bottom is spent between 135.5 degree between 90.
6. germanium-silicon thin membrane preparation method as claimed in claim 1 is characterized in that, the process conditions that form said germanium silicon layer are: pressure is 5Torr to 50Torr, and temperature is 600 degrees centigrade to 800 degrees centigrade, and adopting flow is the SiH of 50sccm to 150sccm
4Perhaps SiH
2Cl
2As the silicon source, and flow be the germanic mist of 5sccm to 100sccm as the germanium source, wherein, GeH
4Account for 10%, and H
2Account for 90%.
7. germanium-silicon thin membrane preparation method as claimed in claim 6 is characterized in that, in the process that forms said germanium silicon layer, adopting flow is the removing gas of the HCl of 50～200sccm as the germanium silicon layer.
8. a manufacturing method of semiconductor device is characterized in that, comprising:
Substrate is provided, the layer of compensation that said substrate surface is formed with grid and is positioned at the grid both sides;
Form side wall at said layer of compensation away from said grid one side;
Said side wall away from a side substrate of said grid in etching form groove;
Adopt 828 degrees centigrade to 850 degrees centigrade temperature conditions, said groove is toasted, then, form the germanium silicon layer that covers said groove;
Said germanium silicon layer is carried out ion doping, to be formed with the source region.
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| CN1921086A (en) * | 2005-08-25 | 2007-02-28 | 中芯国际集成电路制造(上海)有限公司 | Integrated producing method for strain CMOS |
| CN101226899A (en) * | 2007-01-19 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Structure and process for subsequently epitaxial growing strain silicon MOS chip tube in silicon dent |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1921086A (en) * | 2005-08-25 | 2007-02-28 | 中芯国际集成电路制造(上海)有限公司 | Integrated producing method for strain CMOS |
| CN101226899A (en) * | 2007-01-19 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Structure and process for subsequently epitaxial growing strain silicon MOS chip tube in silicon dent |
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