CN102034555A - On-line error correcting device for fault by parity check code and method thereof - Google Patents

Abstract

The invention relates to an on-line error correcting device for faults by parity check codes and a method thereof, belonging to the field of on-line test. The invention solves the problem of huge redundant cost when traditional error correcting codes are used for the on-line test for an embedded memory. The on-line error correcting device for faults comprises two processes of error detection and error correction, wherein the error detection comprises the following steps of: detecting whether new addresses are input or read-write signals are changed; calculating check codes for data; reading the data and comparing the data with memorized check codes; writing a compared result in a fault flag bit memory; and respectively writing fault addresses and the error correcting codes in corresponding memories. The process of the error correction comprises the following steps of: detecting whether the new addresses are input or the read-write signals are changed; judging fault flag bits; and searching the error correcting codes. By using the invention, the on-line test is carried out for the embedded memory under the condition that the memories are not changed to memorize data and the normal read-write operation of the memories is not influenced, and all the faults of odd numbers are detected.

Description

A kind of parity check code that utilizes carries out On-line Fault error correction device and method

Technical field

The present invention relates to a kind of parity check code that utilizes and carry out On-line Fault error correction device and method, belong to the on-line testing field.

Background technology

Integrated circuit has been followed Moore's Law with surprising ground speed development always since coming out.At present, integrated circuit has entered the sub-micro epoch, and the integrated circuit electron device is more and more littler, and chip-scale is increasing.Be accompanied by the raising at full speed of integrated circuit technology level, the design tool of integrated circuit has also had significantly leap.Under these technical backgrounds, can integrated more than one hundred million transistors on the single silicon chip, so just make the complication system that had a plurality of chips cooperations to realize originally, just can realize by one chip.This chip of forming complication systems with the alternative original a plurality of chips of single silicon chip is that (SoC System-on-a-Chip), claims SOC (system on a chip) again to System on Chip/SoC.Appearance along with SoC, traditional circuit testing method has been difficult to satisfy the demands, the difficulty of circuit test is increasing, test duration and cost improve day by day, test and maintenance ensures that expense proportion in product " overall life cycle cost " increases, even the situation of testing cost and development cost reversal of the natural order of things occurs.Therefore, people more and more recognize research method of testing and the urgency and the importance of carrying out design for Measurability.

In the SoC in modern times, storer has occupied space on the sheet of largest portion.At present in chip, storer has accounted for 50%～60%, and in microprocessor commonly used, the shared area of the high-speed cache (cache) that embeds also surpasses 30%, mixed signal circuit almost accounts for less than 5% of chip area, according to the ITRS prediction, by 2014, the storer proportion will reach 94% in the System on Chip/SoC.Therefore, chip reliability depends on the reliability of storer to a great extent.

In order to improve the reliability of storer, except the quality of the design that at first improves it and production, another extremely important measure is exactly in the memory operation process, periodically tests, and it comprises and starts test and on-line testing.Start test class and be similar to off-line test, use be traditional in-line memory method of testing.And on-line testing generally is used for detecting specific use or high reliability application memory, tests under the situation that system can't shut down, and its objective is to detect fault and take suitable measure.It is under the prerequisite that does not influence the storer operate as normal, a kind of method of test in-line memory function correctness.

Several critical problems of in-line memory on-line testing are: under the immovable prerequisite of data of being stored in ensureing storage unit, in-line memory is applied test; Under alap hardware spending, improve the fault coverage of on-line testing, this also is the emphasis that will study.

On-line testing for in-line memory, because storer to be measured is in the course of work, the data in the storer can not be lost, and have been subjected to very big restriction so it is applied test vector, (BIST, Built-inSelf-Test) method is just no longer proved effective to utilize traditional built-in self-test.Modal solution is utilized error correcting code (ECC, error correctingcode) exactly.Error correcting code can realize online detection of storer and error correction, but the hardware redundancy that this method is brought is very huge, is not to be used for extensive use.

Summary of the invention

The present invention seeks in order to solve existingly when utilizing error correcting code that in-line memory is carried out on-line testing, the problem that the redundancy overhead of bringing is too huge provides a kind of parity check code that utilizes to carry out On-line Fault error correction device and method.

A kind of parity check code that utilizes of the present invention carries out the On-line Fault error correction device, it comprises signal analyzer, controller, RAM storer, parity checking code memory, newly imports data parity scrambler, storage data parity scrambler, check code comparer, Reflector bit memory, data selector and Hamming code error-corrector

Read-write control signal r_w and address signal addr send to signal analyzer, described read-write control signal r_w sends to controller and data selector simultaneously, described address signal addr sends to RAM storer, parity checking code memory, Reflector bit memory and Hamming code error-corrector simultaneously

Signal analyzer is exported to controller with new signal input sign signal_check; Controller output read-write id signal r_w_flag and failure identification signal data_in_flag give the Reflector bit memory; Controller also output storage read-write control signal r_w_control is given the RAM memory; Controller is also exported error correction control signal hanming_control and is given the Hamming code error-corrector; Controller is output encoder enable signal encoder1_en and encoder2_en also; Give respectively new input data parity encoder and storage data parity encoder

New input data data_in sends to the RAM storer simultaneously, newly imports data parity scrambler and data selector, new input data check sign indicating number code_in behind the new input data parity scrambler output encoder gives the parity checking code memory, and the new input of parity checking code memory output data check sign indicating number code_out2 give the check code comparer;

RAM storer output storage data data_out_temp give storage data parity scrambler; Storage data parity scrambler output storage data check sign indicating number code_out1 give the check code comparer;

The compare result signal of check code comparer feeds back to controller,

Data selector output error data fault_data gives the Hamming code error-corrector, the data data_out after the Hamming code error-corrector output error correction.

The Hamming code error-corrector comprises the Hamming code controller, address register, address generator, the fail address storer, first comparer, second comparer, the Hamming code scrambler, Hamming code storer and Hamming code code translator, the Hamming code controller receives error correction control signal hanming_control, Hamming code controller output register enable signal reg_en gives address register, Hamming code controller also OPADD enable signal addr_en is given address generator, address generator output calculated address signal addr1 give address register simultaneously, the fail address storer and first comparer, address register output register address signal addr2 gives first comparer, first comparer is exported the first comparator results result1 and is returned to the Hamming code controller

Address signal addr sends to the fail address storer and second comparer simultaneously,

Hamming code controller output fault read-write control signal rw_a and fail address enable signal en_a give the fail address storer, storer output error address signal in fail address is given second comparer, second comparer, the second comparator results result2 returns to the Hamming code controller

Hamming code controller output hamming code read-write control signal rw_h and Hamming code storer enable signal en_h give the Hamming code storer,

Hamming code controller output Hamming code scrambler enable signal encoder_en give the Hamming code scrambler,

Hamming code controller output Hamming code demoder enable signal dncoder_en give the Hamming code code translator,

The Hamming code scrambler receives misdata fault_data, and output hamming code data code_in_h gives Hamming code storer and Hamming code code translator simultaneously, Hamming code storer output Hamming check sign indicating number code_out_h give the Hamming code code translator, the Hamming code code translator receives misdata fault_data, and data data_out after the output error correction.

Be divided into the operation of reading and writing two parts based on above-mentioned a kind of online error correction method that utilizes parity check code to carry out the On-line Fault error correction device,

Detection method may further comprise the steps during write operation:

Whether step 1, signal analyzer check and analysis have new write signal input,

If detect new write signal input, signal analyzer identifies signal_check=(100) with its output with the new signal input _B, execution in step two then; Do not have new write signal input if detect, signal analyzer is with the new signal input sign signal_check=(000) of its output _B, continue to detect;

Step 2, data selector select new input data data_in as misdata fault_data output, and as the input of Hamming code error-corrector,

Step 3, controller receive new signal input sign signal_check=(100) _B, controller output storage read-write control signal r_w_control gives the RAM storer, and the RAM storer will be imported in the storage unit that data data_in writes this address correspondence according to the address signal addr of input,

Simultaneously, new input data parity scrambler is encoded to new input data data_in according to the coding enable signal encoder1_en that controller sends, the new input of output data check sign indicating number code_in, and then store by the parity checking code memory, parity checking code memory and RAM storer use identical Input Address;

Step 4, the read-write control signal r_w_control that sends according to controller read the data data_out_temp in the RAM storer, send into storage data parity scrambler and encode, and obtain exporting canned data check code code_out1;

Step 5, the output of parity checking code memory is input data check sign indicating number code_out2 newly, and compares in the check code comparer with canned data check code code_out1, and comparative result is fed back to controller;

Step 6, when comparative result for not simultaneously, show that this moment, there was mistake in the storage unit corresponding with addr, the comparative result output fault flag that controller obtains according to step 5 is given in the Reflector bit memory, and the Reflector bit memory uses identical address signal with the RAM storer

Simultaneously, controller sends error correction control signal hanming_control and gives the Hamming code error-corrector, and the Hamming code error-corrector begins error correction, and error correction procedure is:

Step 7, Hamming code controller are according to the error correction control signal hanming_control that receives, and the address signal that the Hamming code controller will receive this moment deposits the fail address storer in, and storing process is:

Step 71, Hamming code controller send address enable signal addr_en and give address generator, calculated address signal addr1, the fail address storer is transferred the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, feed back to the Hamming code controller

When fault_addr_out=addr, the second comparative result result2=1,

If do not wait, the second comparative result result2=0 then;

Step 72, is simultaneously sent register enable signal reg_en=0 and is given address register, and register address signal addr2 has been deposited in address register output,

Step 73, address signal addr1 and register address signal addr2 are compared, the first comparative result result1 feeds back to the Hamming code controller,

When addr1=addr2, the first comparative result result1=1,

If do not wait, the second comparative result result1=0 then;

As the second comparative result result2=1, during and addr1＜addr2, presentation address signal addr has been stored in the fail address storer, returns dummy status, waits for next error correction control signal hanming_control input;

When addr1=addr2, presentation address signal addr is not stored in the storer of fail address, and execution in step 74 then;

Step 74, Hamming code controller send Hamming code scrambler enable signal encoder_en and give the Hamming code scrambler, and fault_data encodes to misdata, and the misdata fault_data of this moment is chosen as new input data data_in by data selector,

Simultaneously, Hamming code controller (10-1) sends register enable signal reg_en=1 and gives address register (10-2), and address register (10-2) is preserved addr1+1, and execution in step eight then;

Step 8, Hamming code controller send fault read-write control signal rw_a and fail address enable signal en_a gives the fail address storer, and the control fault addressed memory is stored address signal addr;

Simultaneously, the Hamming code controller sends hamming code read-write control signal rw_h and Hamming code storer enable signal en_h gives the Hamming code storer, and control Hamming code storer is with the hamming code data code_in_h storage of Hamming code scrambler output;

Detection method may further comprise the steps during read operation:

Whether step 1, signal analyzer check and analysis have new read signal input,

If detect new read signal input, what signal analyzer was exported identifies signal_check=(010) with the new signal input _B, execution in step two then; Do not have new read signal input if detect, signal analyzer identifies signal_check=(000) with regard to its output with the new signal input _B, continue to detect;

Step 2, controller receive new signal input sign signal_check=(010) _B, controller output read-write id signal r_w_flag give the Reflector bit memory, and control fault zone bit storer reads the fault flag that has stored this address according to Input Address signal addr, and gives controller with this fault flag;

Step 3, judge whether described failure identification position is 1,

If the failure identification position is 1, indicate that there is fault in this corresponding stored unit, address, execution in step five in the process of write data; If the failure identification position is 0, this corresponding stored unit, address non-fault in the process of write data then, execution in step four;

Step 4, controller output storage read-write control signal r_w_control are given the RAM storer, and the storage data data_out_temp of this address in the RAM storer is read, and as data output, return execution in step one then;

Step 5, controller output storage read-write control signal r_w_control are given the RAM storer, read to store data and send into the Hamming code error-corrector as misdata fault_data,

Simultaneously, controller sends error correction control signal hanming_control and gives the Hamming code error-corrector, and the Hamming code error-corrector begins error correction, and error correction procedure is:

Step 51, Hamming code controller send address enable signal addr_en and give address generator, calculated address signal addr1, the fail address storer is transferred the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, the second comparative result result2 feeds back to the Hamming code controller

Step 52, when the second comparative result result2=1, illustrate to find the corresponding address signal addr1 of this address signal addr institute, simultaneously this address signal is sent into the Hamming code storer;

Step 53, Hamming code controller send hamming code read-write control signal rw_h and hamming code enable signal en_h gives the Hamming code storer, and the Hamming check sign indicating number code_out_h of control Hamming code storer output gives the Hamming code code translator;

Step 54, Hamming code code translator carry out error correction according to storage data data_out_temp and Hamming check sign indicating number code_out_h, the data data_out after the output error correction.

Advantage of the present invention: the present invention can directly apply to in-line memory on-line testing field, can not influence under the in-line memory normal operating conditions, detects single position faults all in the in-line memory, and with its correction.The information redundancy that this method produced is much smaller than using the information redundancy that Hamming code and other error correcting codes produce.

Description of drawings

Fig. 1 is the theory diagram that utilizes parity check code to carry out the On-line Fault error correction device of the present invention;

Fig. 2 is the theory diagram of Hamming code error-corrector;

Fig. 3 is the error correction constitutional diagram, and Idle is an idle condition.

Embodiment

Embodiment one: present embodiment is described below in conjunction with Fig. 1 to Fig. 3, the described a kind of parity check code that utilizes of present embodiment carries out the On-line Fault error correction device, it comprises signal analyzer 1, controller 2, RAM storer 3, parity checking code memory 4, newly imports data parity scrambler 5, storage data parity scrambler 6, check code comparer 7, Reflector bit memory 8, data selector 9 and Hamming code error-corrector 10

Read-write control signal r_w and address signal addr send to signal analyzer 1, described read-write control signal r_w sends to controller 2 and data selector 9 simultaneously, described address signal addr sends to RAM storer 3, parity checking code memory 4, Reflector bit memory 8 and Hamming code error-corrector 10 simultaneously

Signal analyzer 1 is exported to controller 2 with new signal input sign signal_check; Controller 2 output read-write id signal r_w_flag and failure identification signal data_in_flag give Reflector bit memory 8; Controller 2 is gone back output storage read-write control signal r_w_control and is given RAM memory 3; Controller 2 is also exported error correction control signal hanming_control and is given Hamming code error-corrector 10; Controller 2 is gone back output encoder enable signal encoder1_en and encoder2_en; Give respectively new input data parity encoder 5 and storage data parity encoder 6

New input data data_in sends to RAM storer 3 simultaneously, newly imports data parity scrambler 5 and data selector 9, new input data check sign indicating number code_in behind new input data parity scrambler 5 output encoders gives parity checking code memory 4, and the new input of parity checking code memory 4 outputs data check sign indicating number code_out2 give check code comparer 7;

The RAM storer 3 output storage data data_out_temp give storage data parity scrambler 6; Storage data parity scrambler 6 output storage data check sign indicating number code_out1 give check code comparer 7;

The compare result signal of check code comparer 7 feeds back to controller 2,

Data selector 9 output error data fault_data give Hamming code error-corrector 10, the data data_out after the 10 output error correction of Hamming code error-corrector.

Hamming code error-corrector 10 comprises Hamming code controller 10-1, address register 10-2, address generator 10-3, fail address storer 10-4, the first comparer 10-5, the second comparer 10-6, Hamming code scrambler 10-7, Hamming code storer 10-8 and Hamming code code translator 10-9, Hamming code controller 10-1 receives error correction control signal hanming_control, Hamming code controller 10-1 output register enable signal reg_en gives address register 10-2, Hamming code controller 10-1 also OPADD enable signal addr_en gives address generator 10-3, address generator 10-3 output calculated address signal addr1 give address register 10-2 simultaneously, the fail address storer 10-4 and the first comparer 10-5, address register 10-2 output register address signal addr2 gives the first comparer 10-5, the first comparer 10-5 exports the first comparator results result1 and returns to Hamming code controller 10-1

Address signal addr sends to the fail address storer 10-4 and the second comparer 10-6 simultaneously,

Hamming code controller 10-1 output fault read-write control signal rw_a and fail address enable signal en_a give fail address storer 10-4, storer 10-4 output error address signal in fail address is given the second comparer 10-6, the second comparer 10-6, the second comparator results result2 returns to Hamming code controller 10-1

Hamming code controller 10-1 output hamming code read-write control signal rw_h and Hamming code storer enable signal en_h give Hamming code storer 10-8,

Hamming code controller 10-1 output Hamming code scrambler enable signal encoder_en give Hamming code scrambler 10-7,

Hamming code controller 10-1 output Hamming code demoder enable signal dncoder_en give Hamming code code translator 10-9,

Hamming code scrambler 10-7 receives misdata fault_data, and output hamming code data code_in_h gives Hamming code storer 10-8 and Hamming code code translator 10-9 simultaneously, Hamming code storer 10-8 output Hamming check sign indicating number code_out_h give Hamming code code translator 10-9, Hamming code code translator 10-9 receives misdata fault_data, and data data_out after the output error correction.

Embodiment two:, it is characterized in that this method is divided into the operation of reading and writing two parts based on embodiment one described a kind of online error correction method that utilizes parity check code to carry out the On-line Fault error correction device,

Detection method may further comprise the steps during write operation:

Whether step 1, signal analyzer 1 check and analysis have new write signal input,

If detect new write signal input, signal analyzer 1 identifies signal_check=(100) with its output with the new signal input _B, execution in step two then; Do not have new write signal input if detect, signal analyzer 1 is with the new signal input sign signal_check=(000) of its output _B, continue to detect;

Step 2, data selector 9 selects new input data data_in as misdata fault_data output, and as the input of Hamming code error-corrector 10,

Step 3, controller 2 receive new signal input sign signal_check=(100) _B, controller 2 output storage read-write control signal r_w_control give RAM storer 3, and RAM storer 3 will be imported in the storage unit that data data_in writes this address correspondence according to the address signal addr of input,

Simultaneously, new input data parity scrambler 5 is encoded to new input data data_in according to the coding enable signal encoder1_en that controller 2 sends, the new input of output data check sign indicating number code_in, and then store by parity checking code memory 4, parity checking code memory 4 and RAM storer 3 use identical Input Address;

Step 4, the read-write control signal r_w_control that sends according to controller 2 read the data data_out_temp in the RAM storer 3, send into storage data parity scrambler 6 and encode, and obtain exporting canned data check code code_out1;

Step 5,4 outputs of parity checking code memory are input data check sign indicating number code_out2 newly, and compares in check code comparer 7 with canned data check code code_out1, and comparative result is fed back to controller 2;

Step 6, when comparative result for not simultaneously, show that this moment, there was mistake in the storage unit corresponding with addr, the comparative result output fault flag that controller 2 obtains according to step 5 is given in the Reflector bit memory 8, and Reflector bit memory 8 uses identical address signal with RAM storer 3

Simultaneously, controller 2 sends error correction control signal hanming_control and gives Hamming code error-corrector 10, the 10 beginning error correction of Hamming code error-corrector, and error correction procedure is:

Step 7, Hamming code controller 10-1 are according to the error correction control signal hanming_control that receives, and the address signal that Hamming code controller 10-1 will receive this moment deposits fail address storer 10-4 in, and storing process is:

Step 71, Hamming code controller 10-1 send address enable signal addr_en and give address generator 10-3, calculated address signal addr1, fail address storer 10-4 transfers the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, feed back to Hamming code controller 10-1

When fault_addr_out=addr, the second comparative result result2=1,

If do not wait, the second comparative result result2=0 then;

Step 72, is simultaneously sent register enable signal reg_en=0 and is given address register 10-2, and register address signal addr2 has been deposited in address register 10-2 output,

Step 73, address signal addr1 and register address signal addr2 are compared, the first comparative result result1 feeds back to Hamming code controller 10-1,

When addr1=addr2, the first comparative result result1=1,

If do not wait, the second comparative result result1=0 then;

As the second comparative result result2=1, during and addr1＜addr2, presentation address signal addr has been stored in fail address storer 10-4, returns dummy status, waits for next error correction control signal hanming_control input;

When addr1=addr2, presentation address signal addr is not stored in the storer 10-4 of fail address, and execution in step 74 then;

Step 74, Hamming code controller 10-1 send Hamming code scrambler enable signal encoder_en and give Hamming code scrambler 10-7, fault_data encodes to misdata, the misdata fault_data of this moment is chosen as new input data data_in by data selector 9

Simultaneously, Hamming code controller (10-1) sends register enable signal reg_en=1 and gives address register (10-2), and address register (10-2) is preserved addr1+1, and execution in step eight then;

Step 8, Hamming code controller 10-1 send fault read-write control signal rw_a and fail address enable signal en_a gives fail address storer 10-4, and control fault addressed memory 10-4 stores address signal addr;

Simultaneously, Hamming code controller 10-1 sends hamming code read-write control signal rw_h and Hamming code storer enable signal en_h gives Hamming code storer 10-8, and control Hamming code storer 10-8 is with the hamming code data code_in_h storage of Hamming code scrambler 10-7 output;

Detection method may further comprise the steps during read operation:

Whether step 1, signal analyzer 1 check and analysis have new read signal input,

If detect new read signal input, what signal analyzer 1 was exported identifies signal_check=(010) with the new signal input _B, execution in step two then; Do not have new read signal input if detect, signal analyzer 1 identifies signal_check=(000) with regard to its output with the new signal input _B, continue to detect;

Step 2, controller 2 receive new signal input sign signal_check=(010) _B, controller 2 output read-write id signal r_w_flag give Reflector bit memory 8, and control fault zone bit storer 8 reads the fault flag that has stored this address according to Input Address signal addr, and gives controller 2 with this fault flag;

Step 3, judge whether described failure identification position is 1,

If the failure identification position is 1, indicate that there is fault in this corresponding stored unit, address, execution in step five in the process of write data; If the failure identification position is 0, this corresponding stored unit, address non-fault in the process of write data then, execution in step four;

Step 4, controller 2 output storage read-write control signal r_w_control are given RAM storer 3, and the storage data data_out_temp of this address in the RAM storer 3 is read, and as data output, return execution in step one then;

Step 5, controller 2 output storage read-write control signal r_w_control are given RAM storer 3, read to store data and send into Hamming code error-corrector 10 as misdata fault_data,

Simultaneously, controller 2 sends error correction control signal hanming_control and gives Hamming code error-corrector 10, the 10 beginning error correction of Hamming code error-corrector, and error correction procedure is:

Step 51, Hamming code controller 10-1 send address enable signal addr_en and give address generator 10-3, calculated address signal addr1, fail address storer 10-4 transfers the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, the second comparative result result2 feeds back to Hamming code controller 10-1

Step 52, when the second comparative result result2=1, illustrate to find the corresponding address signal addr1 of this address signal addr institute, simultaneously this address signal is sent into Hamming code storer 10-8;

Step 53, Hamming code controller 10-1 send hamming code read-write control signal rw_h and hamming code enable signal en_h gives Hamming code storer 10-8, and the Hamming check sign indicating number code_out_h of control Hamming code storer 10-8 output gives Hamming code code translator 10-9;

Step 54, Hamming code code translator 10-9 carry out error correction according to storage data data_out_temp and Hamming check sign indicating number code_out_h, the data data_out after the output error correction.

Embodiment three: present embodiment further specifies embodiment two, and the process that Hamming code scrambler 10-7 encodes during write operation is:

The input data are: a ₀a ₁A _K-1, the Hamming code data are: H ₀H ₁H _K-1

The check matrix H of step a, the best strange weighted code of structure:

Each element h in the check matrix H _{I, j}=0/1, n is the error correcting code code word, and k is an information bit length, and satisfies: n＜2 ^N-k-1;

Step b, calculation check position:

${\mathrm{<figure-callout\; id="0"\; label="H"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_0=a_0\&CenterDot;h_{00}\&CirclePlus;a_1\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;{\mathrm{<figure-callout\; id="0"\; label="h"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{0,k-1}$

${\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_1=a_0\&CenterDot;{\mathrm{<figure-callout\; id="10"\; label="h"\; filenames="HDA0000044436840000011.png"\; state="\{\{state\}\}">h</figure-callout>}}_{10}\&CirclePlus;a_1\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;{\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{1,k-1}.$

$\begin{array}{ccc}...& ...& ...\end{array}$

$H_{n-k-1}=a_0\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{n-k-1,k-1}$

Embodiment four: present embodiment further specifies embodiment two, and Hamming code code translator 10-9 carries out the process of error correction and is during write operation:

The input data are: a ₀a ₁A _K-1, the Hamming code data are: H ₀H ₁H _K-1

The check matrix H of step a, the best strange weighted code of structure:

Each element h in the check matrix H _{I, j}=0/1, n is the error correcting code code word, and k is an information bit length, and satisfies: n＜2 ^N-k-1;

Step b, calculation check position:

${\mathrm{<figure-callout\; id="0"\; label="H"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_0=a_0\&CenterDot;h_{00}\&CirclePlus;a_1\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;{\mathrm{<figure-callout\; id="0"\; label="h"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{0,k-1}$

${\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_1=a_0\&CenterDot;{\mathrm{<figure-callout\; id="10"\; label="h"\; filenames="HDA0000044436840000011.png"\; state="\{\{state\}\}">h</figure-callout>}}_{10}\&CirclePlus;a_1\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;{\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{1,k-1};$

$\begin{array}{ccc}...& ...& ...\end{array}$

$H_{n-k-1}=a_0\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{n-k-1,k-1}$

Hamming code code translator 10-9 carries out the process of error correction and is during read operation:

Step a, according to the Hamming check sign indicating number code_out_h that stored and storage data data_out_temp, obtain the adjoint matrix P of Hamming code _i, i=0,1 ... n-k-1:

${\mathrm{<figure-callout\; id="0"\; label="P"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">P</figure-callout>}}_0=a_0^{\&prime;}\&CenterDot;h_{00}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;{\mathrm{<figure-callout\; id="0"\; label="h"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{0,k-1}\&CirclePlus;{\mathrm{<figure-callout\; id="0"\; label="H"\; filenames="HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_0$

${\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">P</figure-callout>}}_1=a_0^{\&prime;}\&CenterDot;{\mathrm{<figure-callout\; id="10"\; label="h"\; filenames="HDA0000044436840000011.png"\; state="\{\{state\}\}">h</figure-callout>}}_{10}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;{\mathrm{<figure-callout\; id="1"\; label="h"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">h</figure-callout>}}_{1,k-1}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="H"\; filenames="HDA0000044436840000011.png,HDA0000044436840000031.png"\; state="\{\{state\}\}">H</figure-callout>}}_1;$

$\begin{array}{ccc}...& ...& ...\end{array}$

$P_{n-k-1}=a_0^{\&prime;}\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;h_{n-k-1,k-1}\&CirclePlus;H_{n-k-1}$

Step b, according to the adjoint vector decoding table, find the data bit that has fault;

Adjoint vector P i	0	F 0	F 1	......	F n-k-1
						Error bit	Do not have	a 0	a 1	......	a n-k-1

Step c, this data bit is overturn, and as data data_out output after the error correction.

Claims (6)

1. one kind is utilized parity check code to carry out the On-line Fault error correction device, it is characterized in that, it comprises signal analyzer (1), controller (2), RAM storer (3), parity checking code memory (4), newly imports data parity scrambler (5), storage data parity scrambler (6), check code comparer (7), Reflector bit memory (8), data selector (9) and Hamming code error-corrector (10)

Read-write control signal r_w and address signal addr send to signal analyzer (1), described read-write control signal r_w sends to controller (2) and data selector (9) simultaneously, described address signal addr sends to RAM storer (3), parity checking code memory (4), Reflector bit memory (8) and Hamming code error-corrector (10) simultaneously

Signal analyzer (1) is exported to controller (2) with new signal input sign signal_check, controller (2) output read-write id signal r_w_flag and failure identification signal data_in_flag give Reflector bit memory (8), controller (2) is gone back output storage read-write control signal r_w_control and is given RAM storer (3), controller (2) is also exported error correction control signal hanming_control and is given Hamming code error-corrector (10), controller (2) is gone back output encoder enable signal encoder1_en and encoder2_en, give new input data parity scrambler (5) and storage data parity scrambler (6) respectively

New input data data_in sends to RAM storer (3) simultaneously, newly imports data parity scrambler (5) and data selector (9), new input data check sign indicating number code_in behind new input data parity scrambler (5) output encoder gives parity checking code memory (4), and the new input of parity checking code memory (4) output data check sign indicating number code_out2 give check code comparer (7);

RAM storer (3) output storage data data_out_temp give storage data parity scrambler (6); Storage data parity scrambler (6) output storage data check sign indicating number code_out1 give check code comparer (7);

The compare result signal of check code comparer (7) feeds back to controller (2),

Data selector (9) output error data fault_data gives Hamming code error-corrector (10), the data data_out after Hamming code error-corrector (10) the output error correction.

2. a kind of parity check code that utilizes according to claim 1 carries out the On-line Fault error correction device, it is characterized in that, and when write operation, the new input of data selector (9) output data data_in; When read operation, data selector (9) output storage data data_out_temp.

3. a kind of parity check code that utilizes according to claim 1 and 2 carries out the On-line Fault error correction device, it is characterized in that, Hamming code error-corrector (10) comprises Hamming code controller (10-1), address register (10-2), address generator (10-3), fail address storer (10-4), first comparer (10-5), second comparer (10-6), Hamming code scrambler (10-7), Hamming code storer (10-8) and Hamming code code translator (10-9), Hamming code controller (10-1) receives error correction control signal hanming_control, Hamming code controller (10-1) output register enable signal reg_en gives address register (10-2), Hamming code controller (10-1) also OPADD enable signal addr_en is given address generator (10-3), address generator (10-3) output calculated address signal addr1 give address register (10-2) simultaneously, fail address storer (10-4) and first comparer (10-5), address register (10-2) output register address signal addr2 gives first comparer (10-5), first comparer (10-5) output, the first comparator results result1 returns to Hamming code controller (10-1)

Address signal addr sends to fail address storer (10-4) and second comparer (10-6) simultaneously,

Hamming code controller (10-1) output fault read-write control signal rw_a and fail address enable signal en_a give fail address storer (10-4), fail address storer (10-4) output error address signal is given second comparer (10-6), second comparer (10-6), the second comparator results result2 returns to Hamming code controller (10-1)

Hamming code controller (10-1) output hamming code read-write control signal rw_h and Hamming code storer enable signal en_h give Hamming code storer (10-8),

Hamming code controller (10-1) output Hamming code scrambler enable signal encoder_en give Hamming code scrambler (10-7),

Hamming code controller (10-1) output Hamming code demoder enable signal dncoder_en give Hamming code code translator (10-9),

Hamming code scrambler (10-7) receives misdata fault_data, and output hamming code data code_in_h gives Hamming code storer (10-8) and Hamming code code translator (10-9) simultaneously, Hamming code storer (10-8) output Hamming check sign indicating number code_out_h give Hamming code code translator (10-9), Hamming code code translator (10-9) receives misdata fault_data, and data data_out after the output error correction.

4. based on the described a kind of online error correction method that utilizes parity check code to carry out the On-line Fault error correction device of claim 3, it is characterized in that this method is divided into the operation of reading and writing two parts,

Detection method may further comprise the steps during write operation:

Whether step 1, signal analyzer (1) check and analysis have new write signal input,

If detect new write signal input, signal analyzer (1) identifies signal_check=(100) with its output with the new signal input _B, execution in step two then; Do not have new write signal input if detect, signal analyzer (1) is with the new signal input sign signal_check=(000) of its output _B, continue to detect;

Step 2, data selector (9) select new input data data_in as misdata fault_data output, and as the input of Hamming code error-corrector (10),

Step 3, controller (2) receive new signal input sign signal_check=(100) _B, controller (2) output storage read-write control signal r_w_control gives RAM storer (3), and RAM storer (3) will be imported in the storage unit that data data_in writes this address correspondence according to the address signal addr of input,

Simultaneously, new input data parity scrambler (5) is encoded to new input data data_in according to the coding enable signal encoder1_en that controller (2) sends, the new input of output data check sign indicating number code_in, and then store by parity checking code memory (4), parity checking code memory (4) and RAM storer (3) use identical Input Address;

Step 4, the read-write control signal r_w_control that sends according to controller (2) read the data data_out_temp in the RAM storer (3), send into storage data parity scrambler (6) and encode, obtain exporting canned data check code code_out1;

Step 5, parity checking code memory (4) output is input data check sign indicating number code_out2 newly, and compares in check code comparer (7) with canned data check code code_out1, and comparative result is fed back to controller (2);

Step 6, when comparative result for not simultaneously, show that this moment, there was mistake in the storage unit corresponding with addr, the comparative result output fault flag that controller (2) obtains according to step 5 is given in the Reflector bit memory (8), Reflector bit memory (8) uses identical address signal with RAM storer (3)

Simultaneously, controller (2) sends error correction control signal hanming_control and gives Hamming code error-corrector (10), Hamming code error-corrector (10) beginning error correction, and error correction procedure is:

Step 7, Hamming code controller (10-1) are according to the error correction control signal hanming_control that receives, and the address signal that Hamming code controller (10-1) will receive this moment deposits fail address storer (10-4) in, and storing process is:

Step 71, Hamming code controller (10-1) send address enable signal addr_en and give address generator (10-3), calculated address signal addr1, fail address storer (10-4) is transferred the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, feed back to Hamming code controller (10-1)

When fault_addr_out=addr, the second comparative result result2=1,

If do not wait, the second comparative result result2=0 then;

Step 72, is simultaneously sent register enable signal reg_en=0 and is given address register (10-2), and register address signal addr2 has been deposited in address register (10-2) output,

Step 73, address signal addr1 and register address signal addr2 are compared, the first comparative result result1 feeds back to Hamming code controller (10-1),

When addr1=addr2, the first comparative result result1=1,

If do not wait, the second comparative result result1=0 then;

As the second comparative result result2=1, during and addr1＜addr2, presentation address signal addr has been stored in fail address storer (10-4), returns dummy status, waits for next error correction control signal hanming_control input;

When addr1=addr2, presentation address signal addr is not stored in the fail address storer (10-4), and execution in step 74 then;

Step 74, Hamming code controller (10-1) send Hamming code scrambler enable signal encoder_en and give Hamming code scrambler (10-7), fault_data encodes to misdata, the misdata fault_data of this moment is chosen as new input data data_in by data selector (9)

Simultaneously, Hamming code controller (10-1) sends register enable signal reg_en=1 and gives address register (10-2), and address register (10-2) is preserved addr1+1, and execution in step eight then;

Step 8, Hamming code controller (10-1) send fault read-write control signal rw_a and fail address enable signal en_a gives fail address storer (10-4), and control fault addressed memory (10-4) is stored address signal addr;

Simultaneously, Hamming code controller (10-1) sends hamming code read-write control signal rw_h and Hamming code storer enable signal en_h gives Hamming code storer (10-8), and control Hamming code storer (10-8) is with the hamming code data code_in_h storage of Hamming code scrambler (10-7) output;

Detection method may further comprise the steps during read operation:

Whether step 1, signal analyzer (1) check and analysis have new read signal input,

If detect new read signal input, what signal analyzer (1) was exported identifies signal_check=(010) with the new signal input _B, execution in step two then; Do not have new read signal input if detect, signal analyzer (1) identifies signal_check=(000) with regard to its output with the new signal input _B, continue to detect;

Step 2, controller (2) receive new signal input sign signal_check=(010) _BController (2) output read-write id signal r_w_flag give Reflector bit memory (8), control fault zone bit storer (8) reads the fault flag that has stored this address according to Input Address signal addr, and gives controller (2) with this fault flag;

Step 3, judge whether described failure identification position is 1,

If the failure identification position is 1, indicate that there is fault in this corresponding stored unit, address, execution in step five in the process of write data; If the failure identification position is 0, this corresponding stored unit, address non-fault in the process of write data then, execution in step four;

Step 4, controller (2) output storage read-write control signal r_w_control are given RAM storer (3), and the storage data data_out_temp of this address in the RAM storer (3) is read, and as data output, return execution in step one then;

Step 5, controller (2) output storage read-write control signal r_w_control are given RAM storer (3), read to store data and send into Hamming code error-corrector (10) as misdata fault_data,

Simultaneously, controller (2) sends error correction control signal hanming_control and gives Hamming code error-corrector (10), Hamming code error-corrector (10) beginning error correction, and error correction procedure is:

Step 51, Hamming code controller (10-1) send address enable signal addr_en and give address generator (10-3), calculated address signal addr1, fail address storer (10-4) is transferred the address information fault_addr_out of the fault data of this address storage according to address signal addr1, and with this moment address signal addr compare, the second comparative result result2 feeds back to Hamming code controller (10-1)

Step 52, when the second comparative result result2=1, illustrate to find the corresponding address signal addr1 of this address signal addr institute, simultaneously this address signal is sent into Hamming code storer (10-8);

Step 53, Hamming code controller (10-1) send hamming code read-write control signal rw_h and hamming code enable signal en_h gives Hamming code storer (10-8), and the Hamming check sign indicating number code_out_h of control Hamming code storer (10-8) output gives Hamming code code translator (10-9);

Step 54, Hamming code code translator (10-9) carry out error correction according to storage data data_out_temp and Hamming check sign indicating number code_out_h, the data data_out after the output error correction.

5. a kind of online error correction method that utilizes parity check code to carry out the On-line Fault error correction device according to claim 4 is characterized in that the process that Hamming code scrambler (10-7) is encoded during write operation is:

The input data are: a ₀a ₁A _K-1, the Hamming code data are: H ₀H ₁H _K-1

The check matrix H of step a, the best strange weighted code of structure:

Each element h in the check matrix H _{I, j}=0/1, n is the error correcting code code word, and k is an information bit length, and satisfies: n＜2 ^N-k-1;

Step b, calculation check position:

$H_0=a_0\&CenterDot;h_{00}\&CirclePlus;a_1\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{0,k-1}$

$H_1=a_0\&CenterDot;h_{10}\&CirclePlus;a_1\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{1,k-1}.$

$\begin{array}{ccc}...& ...& ...\end{array}$

$H_{n-k-1}=a_0\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{n-k-1,k-1}$

6. a kind of online error correction method that utilizes parity check code to carry out the On-line Fault error correction device according to claim 4 is characterized in that, Hamming code code translator (10-9) carries out the process of error correction and is during write operation:

The input data are: a ₀a ₁A _K-1, the Hamming code data are: H ₀H ₁H _K-1

The check matrix H of step a, the best strange weighted code of structure:

Each element h in the check matrix H _{I, j}=0/1, n is the error correcting code code word, and k is an information bit length, and satisfies: n＜2 ^N-k-1;

Step b, calculation check position:

$H_0=a_0\&CenterDot;h_{00}\&CirclePlus;a_1\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{0,k-1}$

$H_1=a_0\&CenterDot;h_{10}\&CirclePlus;a_1\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{1,k-1};$

$\begin{array}{ccc}...& ...& ...\end{array}$

$H_{n-k-1}=a_0\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}\&CenterDot;h_{n-k-1,k-1}$

Hamming code code translator (10-9) carries out the process of error correction and is during read operation:

Step a, according to the Hamming check sign indicating number code_out_h that stored and storage data data_out_temp, obtain the adjoint matrix P of Hamming code _i, i=0,1 ... n-k-1:

$P_0=a_0^{\&prime;}\&CenterDot;h_{00}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{01}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;h_{0,k-1}\&CirclePlus;H_0$

$P_1=a_0^{\&prime;}\&CenterDot;h_{10}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{11}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;h_{1,k-1}\&CirclePlus;H_1;$

$\begin{array}{ccc}...& ...& ...\end{array}$

$P_{n-k-1}=a_0^{\&prime;}\&CenterDot;h_{n-k-\mathrm{1,0}}\&CirclePlus;a_1^{\&prime;}\&CenterDot;h_{n-k-\mathrm{1,1}}\&CirclePlus;...\&CirclePlus;a_{k-1}^{\&prime;}\&CenterDot;h_{n-k-1,k-1}\&CirclePlus;H_{n-k-1}$

Step b, according to the adjoint vector decoding table, find the data bit that has fault;

Adjoint vector P _i 0 F ₀ F ₁ ...... F _n-k-1 Error bit Do not have a ₀ a ₁ ...... a _n-k-1

Step c, this data bit is overturn, and as data data out output after the error correction.

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