CN102024781A - Integrated circuit structure - Google Patents

Integrated circuit structure Download PDF

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Publication number
CN102024781A
CN102024781A CN2010102837900A CN201010283790A CN102024781A CN 102024781 A CN102024781 A CN 102024781A CN 2010102837900 A CN2010102837900 A CN 2010102837900A CN 201010283790 A CN201010283790 A CN 201010283790A CN 102024781 A CN102024781 A CN 102024781A
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China
Prior art keywords
metal
guide hole
integrated circuit
semiconductor substrate
substrate
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Granted
Application number
CN2010102837900A
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Chinese (zh)
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CN102024781B (en
Inventor
陈明发
邱文智
眭晓林
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Advanced Manufacturing Innovation Co
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN102024781A publication Critical patent/CN102024781A/en
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Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. By forming backside interconnect structures using dual damascene processes, multiple interconnect layers may be stacked to provide a great routing ability.

Description

Integrated circuit structure
Technical field
The present invention relates to integrated circuit structure, particularly be formed on the wafer backside and connect and run through substrate guide hole (through-substrate via; TSV) internal connection-wire structure.
Background technology
Because the integration density (integration density) of various electronic building bricks (for example transistor, diode, resistance, electric capacity etc.) improves constantly, semi-conductor industry has experienced continuous quick growth.Under most situation, the raising of integration density is to come from minimum feature size (minimum feature size) over and over again to dwindle, and dwindling of minimum feature size can make more assembly be integrated in the given chip area.
Integrated progress is actually the progress on two dimension (plane), because the occupied volume of integrated package is basically on the surface of semiconductor wafer.Though the remarkable lifting of photoetching technique has made the obvious improvement that is formed with of two-dimentional integrated circuit, yet accessible density has restriction physically on two dimension.These limit one of them is the minimum dimension that needs to make these assemblies.Moreover, when inserting in the chip, can need more complicated design to more element.
When the quantity of element increased, an extra restriction was the remarkable increase that comes from the quantity of interelement intraconnections and length.When the quantity of intraconnections and length increased, the RC of circuit postpones (RC delay) all can be increased with power consumption (power consumption).
Solve in many effort of above-mentioned restriction in desire, what generally use is three-dimensional integrated circuit (three-dimensional integrated circuit, 3D IC) and stacked chips (stacked dies).Therefore, the substrate guide hole be will run through and three-dimensional integrated circuit and stacked chips will be used for to connect chip.At this, run through the substrate guide hole and often be used to connect integrated circuit on the chip to the dorsal part of this chip.In addition, run through the substrate guide hole and also be used to provide path, short circuit ground, so that integrated circuit is via the dorsal part ground connection of chip, wherein a grounded metal film can cover the dorsal part of chip.
Since engage a plurality of comprise chip needs that run through the substrate guide hole big relatively run through the substrate feed pitch, therefore, the position of running through the substrate guide hole is restricted and the spacing that runs through the substrate guide hole need reach greatly so that for example enough spaces of soldered ball to be provided.In addition, with the method for existing formation wafer backside structure, making the electric connection structure that runs through the substrate guide hole is impossible away from separately the substrate guide hole that runs through.
Summary of the invention
For overcoming defective of the prior art, one embodiment of the invention provides a kind of integrated circuit structure, comprises the semiconductor substrate, has a positive and back side; One guide hole runs through semiconductor substrate; One metal structure is positioned on the back side of semiconductor substrate, and metal structure comprises a metal gasket, covers and the contact guide hole; And a metal wire, be positioned on the guide hole, wherein metal wire comprises a dual-damascene structure; And a projection, on metal wire.
Another embodiment of the present invention provides a kind of integrated circuit structure, comprises the semiconductor substrate, has a positive and back side; One guide hole is arranged in semiconductor substrate; One first metal structure extends to the semiconductor substrate from the back side of semiconductor substrate and contacts guide hole; And a projection, on first metal structure and electrically connect first metal structure.
Further embodiment of this invention provides a kind of integrated circuit structure, comprises the semiconductor substrate, has a positive and back side; One guide hole runs through semiconductor substrate; One first metal structure is formed on the back side of semiconductor substrate and contacts guide hole, and wherein first metal structure comprises a dual-damascene structure; And a projection, be formed on first metal structure.
Use dual-damascene technics to form the dorsal part internal connection-wire structure, can pile up a plurality of internal connecting layer so that big coiling property to be provided.
Description of drawings
Fig. 1-Figure 11, Figure 12 A, Figure 12 B illustrate the profile in interstage of the making one dorsal part internal connection-wire structure of one embodiment of the invention, and wherein the substrate guide hole is run through for depression in the back side of a substrate and one.
Figure 13-Figure 22, Figure 23 A, Figure 23 B illustrate the profile in interstage of the making one dorsal part internal connection-wire structure of another embodiment of the present invention, and wherein cave in the back side of a substrate.
Figure 24-Figure 28, Figure 29 A, Figure 29 B illustrate the profile in interstage of the making one dorsal part internal connection-wire structure of further embodiment of this invention, and wherein the dorsal part internal connection-wire structure is formed on the back side of a substrate.
Wherein, description of reference numerals is as follows:
2～chip;
10～substrate;
10b～back side;
10f～front side;
12～internal connection-wire structure;
14～connection pad;
15～square;
20～run through the substrate guide hole;
22～insulating barrier;
24～opening;
25～carrier;
26,31～photoresist;
27～(groove) openings;
28～bottom;
30～dielectric insulation layer;
32,128,148,236～electrically conductive barrier;
33,136,226～guide hole opening;
34～copper;
36～metal structure;
36-1～metal wire;
36-2～metal structure, metal gasket;
38,48,222～dielectric layer;
40～photoresist;
42～projection;
46,220～etch stop layer;
50,146～guide hole;
52～metal wire;
60～extra play, intraconnections extra play;
124,124 '～dielectric layer;
125～dielectric layer;
126～opening;
130～metal material;
132～metal wire/pad;
132-1～metal structure, metal gasket;
132-2,234～metal wire;
134～photoresist;
138,228～groove opening;
140～photoresist, additional photoresist, patterning photoresist;
144～metal wire;
232～through hole;
D1～cup depth;
D2～etch-back the degree of depth.
Embodiment
Making and the occupation mode of a plurality of embodiment of the present invention below will be described in detail in detail.It should be noted that so these embodiment provide many inventive concepts of supplying usefulness, it can be implemented in multiple particular environment.The specific embodiment of being discussed in the literary composition only goes in a particular manner to make in order to explanation and uses the present invention, is not in order to limit the scope of the invention.
The invention provides one and be connected to dorsal part connecting line construction that runs through the substrate guide hole and forming method thereof.The interstage of making an embodiment below will be described, and the multiple variation of embodiment will be discussed.In whole accompanying drawings and explanation embodiment, similar label will be in order to indicate similar element.
Please refer to Fig. 1, chip 2 is provided, comprise substrate 10 and integrated circuit (not shown) in it.Chip 2 can be the wafer of a part.Substrate 10 can be the semiconductor substrate, a bulk silicon substrate (bulk silicon substrate) for example, but substrate 10 also can comprise other semi-conducting material, for example three races, four families and/or group-v element.The semiconductor element of active formula (for example transistor is represented with square 15) can be formed on the front side 10f of substrate 10.In this article, " dorsal part " speech is meant substrate 10 with respect to the side with active formula semiconductor element.The front side 10f that internal connection-wire structure 12 is formed on substrate 10 goes up and is connected to active formula semiconductor element, and wherein internal connection-wire structure 12 comprises metal wire and is formed at its interior guide hole (not shown).Metal wire and guide hole are made of copper or copper alloy, and the available mosaic technology of knowing (damascene process) is made.Internal connection-wire structure 12 can comprise interlayer dielectric layer known to general (inter-layer dielectric, ILD) and metal intermetallic dielectric layer (inter-metal dielectrics, IMDs).Connection pad 14 is formed on the front side 10f of substrate 10.
Run through substrate guide hole 20 and be formed in the substrate 10, and extend into the substrate 10 from front side 10f.In one embodiment, as shown in Figure 1, before forming internal connection-wire structure 12, utilize pilot hole method (Via-first approach) to form and run through substrate guide hole 20.Therefore, run through 20 of substrate guide holes and extend to the interlayer dielectric layer in the internal connection-wire structure 12 and do not extend in the metal intermetallic dielectric layer, wherein interlayer dielectric layer is in order to cover active element.In other embodiments, after forming internal connection-wire structure 12, utilize back guide hole method (via-last approach) to form and run through substrate guide hole 20.Therefore, run through substrate guide hole 20 and run through substrate 10 and internal connection-wire structure 12.Insulating barrier (isolation layer) 22 is formed on the sidewall and end that runs through substrate guide hole 20, and makes and run through substrate guide hole 20 and be electrically insulated with substrate 10.Insulating barrier 22 general available dielectric materials form, and wherein dielectric material for example is silicon nitride, silica (for example tetraethyl-metasilicate oxide, tetra-ethyl-ortho-silicate oxide, TEOS oxide) and homologue thereof.Chip 2 and corresponding wafer are adhered to carrier 25.
Please refer to Fig. 2, carry out a dorsal part grinding technics (backside grinding), come out via the back side 10b of substrate 10 so that run through substrate guide hole 20.Can utilize and run through substrate guide hole 20 as the stop layer in the dorsal part grinding technics (stop layer).Then, as shown in Figure 3, make and run through substrate guide hole 20 depressions, therefore, its upper surface is lower than the back side 10b of substrate 10.Cup depth D1 is slightly larger than 0.5 micron approximately, and can be 3 microns in an exemplary embodiment.Because this recess process forms opening 24.
Fig. 4 introduces the recess process of substrate 10, and is to be that mask carries out recess process with photoresist 26.Because this recess process, the horizontal size of opening 24 increases and greater than the horizontal size that runs through substrate guide hole 20.Although the bottom 28 of the opening 24 of back side 10b illustrated in fig. 4 flushes in the exposed junction that runs through substrate guide hole 20.In other embodiments, bottom 28 can also be to be higher than or to be lower than the exposed junction that runs through substrate guide hole 20, also as shown in (among Fig. 4) dotted line.Opening 24 forms simultaneously with (groove) opening 27.
Please refer to Fig. 5, deposit dielectric insulating barrier 30.Deposition process comprise low temperature chemical vapor deposition (10w-temperature chemical vapor deposition, LTCVD), but the method that also can use other generally to use.In an exemplary embodiment, dielectric insulation layer 30 comprises silicon nitride (silicon nitride, SiN x) and the thickness of dielectric insulation layer 30 can be hundreds of dusts (angstrom).Then, as shown in Figure 6, by painting photoresist 31 and carry out the part that covering that photoetching process makes dielectric insulation layer 30 runs through the end of substrate guide hole 20 and be exposed in the guide hole opening (via opening) 33, so that the projection of Xing Chenging (bump) can be electrically connected to and runs through substrate guide hole 20 afterwards.
Fig. 7-Fig. 9 illustrates the technology of reshuffling circuit (redistribution line) and connection pad.Please refer to Fig. 7, for example the method with sputter (sputtering) forms electrically conductive barrier (conductive barrier layer) 32, and the material of electrically conductive barrier 32 can comprise titanium, titanium nitride (titanium nitride), tantalum (tantalum), tantalum nitride (tantalum nitride) or its homologue.Then, copper facing 34 (as shown in Figure 8).Afterwards, (chemical mechanical polish, CMP) to form metal structure (metal feature) 36 (being denoted as 36-1 and 36-2 among the figure), its final structure as shown in Figure 9 to carry out cmp.Metal structure 36 can comprise metal wire 36-1, and what in fact it can connect other runs through substrate guide hole (not shown).Therefore, metal wire 36-1 reshuffles circuit in order to conduct.Metal structure 36-2 can be metal gasket or metal wire.The size of metal gasket can be greater than the size that runs through substrate guide hole 20 (when overlooking metal gasket when running through substrate guide hole 20), and on whole horizontal directions, the extensible mistake of metal gasket runs through the edge of substrate guide hole 20.Therefore, metal gasket 36-2 is with to run through bonding area (interface area) between the substrate guide hole 20 big and have reliable the connection, so contact impedance (contact resistance) is little.Moreover metal gasket 36-2 aims at the accuracy requirement (accuracy requirement) that runs through substrate guide hole 20 can be comparatively loose.
Figure 10-Figure 12 A illustrates the technology of projection 42.Please refer to Figure 10, comprehensively dielectric layer 38.In an exemplary embodiment, dielectric layer 38 comprises silicon nitride, and the thickness of dielectric layer 38 can for example be about 0.2 micron.Afterwards, as shown in figure 11, utilize photoresist 40 in dielectric layer 38, to form an opening, to expose metal gasket 36-2.Figure 12 A illustrates the technology of projection 42, projection 42 also can be described as the dimpling piece (micro-bump, U-bump) because its horizontal size (length or width) is approximately less than 30 microns.The formation method of projection 42 comprise electrochemistry plating (electrical chemical plating, ECP), electroless plating (electroless plating) and immersion plating (immersion).The projection 42 that produces can soak gold (electroless nickel immersion gold by having nickel, ENIG) structure, change nickel palladium soak gold (nickel electroless palladium immersion gold, ENEPIG) structure or nickel palladium structure (nickel palladium structure).Scrutablely be, though shown in Figure 12 A is that projection 42 is positioned at directly over the metal gasket 36-2, in fact connect metal gasket 36-2 by reshuffling circuit (metalloid line 36-1) but projection 42 also can not be positioned at directly over the metal gasket 36-2, wherein reshuffle circuit and metal structure 36 and form simultaneously.
Figure 12 B illustrates another embodiment of the present invention.Can form extra reconfiguration line layer with replace with projection 42 be formed on metal gasket 36-2 directly over.For instance, can insert an extra play (additional layer) 60 between metal gasket 36-2 and projection 42, extra play 60 comprises etch stop layer (etch stop layer) 46, dielectric layer 48, guide hole 50 and metal wire 52.If situation needs, can on extra play 60, pile up the more heterogeneous rete of extra play 60 that is similar to increase the coiling property (routability) of internal connection-wire structure dorsal part.The formation details of extra play 60 can be identical with Figure 18-21 in fact, and it will be in hereinafter describing in detail.
Figure 13-Figure 23 B illustrates another embodiment of the present invention.Present embodiment step at the beginning is as shown in Fig. 1-2.Afterwards, please refer to Figure 13, from dorsal part etch-back (etch back) substrate 10, so that run through the back side that substrate guide hole 20 protrudes in substrate 10.In an exemplary embodiment, etch-back depth D 2 is approximately greater than 0.5 micron, and is about 1 micron.Also can be from running through the end face etch-back insulating barrier 22 of substrate guide hole 20, so that insulating barrier 22 is lower than for example about 0.5 micron of the end face that runs through substrate guide hole 20.Therefore, expose the part of the sidewall that runs through substrate guide hole 20.
Please refer to Figure 14, dielectric layer 124 is formed on the back side of substrate 10 and covers and runs through substrate guide hole 20.In one embodiment, dielectric layer 124 is made of polyimides (polyimide), and its thickness is reducible greater than 2 microns, and an exemplary thickness is about 3 microns.In another embodiment, also can use other dielectric material.
Figure 15-Figure 17 illustrates the technology of the metal wire of one embodiment of the invention.Please refer to Figure 15, for example under the help of a photoresist (not shown), form a plurality of openings 126 by etching dielectric layer 124.In one embodiment, for example use temporal mode (time mode) to control the forming process of opening, come out via an opening 126 wherein so that run through substrate guide hole 20, simultaneously, the bottom (being denoted as dielectric layer 124 ') that keeps dielectric layer 124 is to separate opening 126 and substrate 10.
Please refer to Figure 16, carry out prerinse technology (pre-clean) and for example with the mode depositing electrically conductive barrier layer (conductive barrier layer) 128 of sputter.Electrically conductive barrier 128 can comprise titanium, tantalum or its homologue.Then, metal material 130 is plating to the end face that is higher than dielectric layer 124.Metal material 130 can comprise copper, but also can use other metal, for example aluminium, tungsten or its homologue.Afterwards, carry out cmp (as shown in figure 17), thereby form metal wire/pad 132 (being denoted as 132-1 and 132-2).Metal wire 132-2 can electrically connect a plurality of one of the substrate guide holes that run through in the chip.Therefore, metal wire 132-2 can be used as and reshuffles circuit.Metal structure 132-1 can be metal gasket or metal wire (metal trace).The size of metal gasket (when overlooking) can be greater than the size that runs through substrate guide hole 20, and wherein, in vertical view, in a lateral direction all, metal gasket 132-1 is extensible above the edge that runs through substrate guide hole 20.
Figure 18-Figure 21 illustrates the technology of extra play of the intraconnections of one embodiment of the invention.Please refer to Figure 18, form dielectric layer 125.In one embodiment, dielectric layer 125 is made of polyimides, and its thickness is about several microns, for example is about 2.5 microns.Afterwards, coating and patterning photoresist 134.Then, by patterning photoresist 134 etching dielectric layers 125 up to exposing metal wire 132-2, to form a plurality of guide hole openings 136.
Please refer to Figure 19, remove photoresist 134, and formation and the additional photoresist 140 of patterning.Afterwards, as shown in figure 20, by patterning photoresist 140 further etching dielectric layers 125 to form a plurality of groove opening (trench opening) 138.The up duration pattern is carried out etch process, so that etch process stops at the centre of dielectric layer 125.Then, for example remove photoresist 140 in the mode of ashing (ashing).Scrutablely be, Figure 18-step shown in Figure 20 is the pilot hole method, and it is to form guide hole opening 136 before groove opening 138 forms.Those of ordinary skills can understand structure shown in Figure 20 and can first ditch channel process form, and wherein Figure 19-step shown in Figure 20 can be carried out before step shown in Figure 180.
Figure 21 illustrates the technology of the mosaic texture that comprises metal wire 144 and guide hole 146 of one embodiment of the invention, and it can comprise depositing electrically conductive barrier layer 148 (a for example titanium layer), copper facing and carry out cmp to remove too much copper.Figure 22-23A illustrates the technology of dielectric layer 38 and projection 42.This technology is substantially the same in the foregoing description, so no longer repeat in this.Figure 23 B illustrates another embodiment of the present invention, and wherein metal wire 144 is formed in the dielectric layer 124 with guide hole 146.
Figure 24-Figure 29 B illustrates further embodiment of this invention.The initial step of present embodiment is identical with Fig. 1-Fig. 2.Afterwards, as shown in figure 24, form etch stop layer 220.In one embodiment, etch stop layer 220 is formed by silicon nitride, and its thickness can for example be about 750 dusts
Figure BSA00000272680300081
Then, on etch stop layer 220, form dielectric layer 222.In one embodiment, a kind of in can various chemical vapour deposition techniques forms dielectric layer 222, and dielectric layer 222 can comprise for example oxide.The thickness of the dielectric layer 222 of chemical vapour deposition (CVD) can for example be about 8000 dusts
Figure BSA00000272680300082
In another embodiment, dielectric layer 222 is made of polyimides, therefore, can have a thickness obviously greater than the thickness of the dielectric layer made from chemical vapour deposition technique.The thickness of the dielectric layer 222 that polyimides constituted approximately can be greater than 2 microns, and in an exemplary embodiment, are about 5 microns.
Figure 25-Figure 27 illustrates the technology of guide hole opening 226 and groove opening 228.It is identical with Figure 18-Figure 20 in fact to form details, so no longer repeat in this.Afterwards, as shown in figure 28, form a dual-damascene structure (dual damascene structure), dual-damascene structure comprises through hole 232 and is covered in metal wire 234 on the through hole 232 that wherein metal wire 234 is made of copper.Also form electrically conductive barrier 236.
Figure 29 A illustrates the technology of dielectric layer 38 and projection 42.The material of dielectric layer 38 and projection 42 and technology can be identical with Figure 10-12A basically.Figure 29 B illustrates another embodiment with intraconnections extra play 60, and intraconnections extra play 60 comprises additional dual-damascene structure.If be necessary, can insert more internal connecting layer.
These embodiment have many advantages.Use dual-damascene technics to form the dorsal part internal connection-wire structure, can pile up a plurality of internal connecting layer so that big coiling property to be provided.By on substrate, making groove to form metal gasket (36-2 among Figure 10 and the 132-1 among Figure 17) and to make the metal gasket contact run through the substrate guide hole, metal gasket can have large scale so that metal gasket aim at the accuracy requirement run through the substrate guide hole can be comparatively loose.Moreover, because metal gasket and the contact area that runs through the substrate guide hole under it are big, therefore, can reduce contact impedance.
Though the present invention with preferred embodiment openly as above; so it is not in order to limit scope of the present invention; those of ordinary skill under any in the technical field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the protection range that claim defined of enclosing.

Claims (10)

1. integrated circuit structure comprises:
The semiconductor substrate has a positive and back side;
One guide hole runs through this semiconductor substrate;
One metal structure is positioned on the back side of this semiconductor substrate, and this metal structure comprises:
One metal gasket covers and contacts this guide hole; And
One metal wire is positioned on this guide hole, and wherein this metal wire comprises a dual-damascene structure; And
One projection is on this metal wire.
2. integrated circuit structure as claimed in claim 1, wherein this metal is paid somebody's debt and expected repayment later and is comprised:
One first bottom surface contacts an end face of this guide hole; And
One second bottom surface is higher than this back side of this semiconductor substrate and is lower than this first bottom surface.
3. integrated circuit structure as claimed in claim 1, wherein this dual-damascene structure and this metal gasket are arranged in same dielectric layer.
4. integrated circuit structure as claimed in claim 1, wherein this dual-damascene structure is arranged in the dielectric layer on this metal gasket.
5. integrated circuit structure as claimed in claim 1, wherein all horizontal sizes of this metal gasket are respectively greater than the horizontal size of this guide hole.
6. integrated circuit structure comprises:
The semiconductor substrate has a positive and back side;
One guide hole is arranged in this semiconductor substrate;
One first metal structure extends to this semiconductor substrate from this back side of this semiconductor substrate and contacts this guide hole; And
One projection is positioned on this first metal structure and electrically connects this first metal structure.
7. integrated circuit structure as claimed in claim 6 also comprises:
One second metal structure is formed between this first metal structure and this projection, and wherein this second metal structure comprises a dual-damascene structure.
8. integrated circuit structure as claimed in claim 6, wherein all horizontal sizes of this first metal structure are respectively greater than the horizontal size of this guide hole.
9. integrated circuit structure as claimed in claim 6, wherein this first metal structure comprises an end face, this end face flushes with this back side of this semiconductor substrate in fact.
10. integrated circuit structure as claimed in claim 6, wherein this first metal structure comprises:
One electrically conductive barrier contacts this guide hole; And
The metal material of one cupric is positioned on this electrically conductive barrier.
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US20170005069A1 (en) 2017-01-05
US9449875B2 (en) 2016-09-20

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