CN102024777A - Semiconductor chip encapsulation structure and encapsulation method - Google Patents
Semiconductor chip encapsulation structure and encapsulation method Download PDFInfo
- Publication number
- CN102024777A CN102024777A CN200910195984.2A CN200910195984A CN102024777A CN 102024777 A CN102024777 A CN 102024777A CN 200910195984 A CN200910195984 A CN 200910195984A CN 102024777 A CN102024777 A CN 102024777A
- Authority
- CN
- China
- Prior art keywords
- lead
- wire
- pad
- die pad
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor chip encapsulation structure and an encapsulation method. The semiconductor chip encapsulation structure comprises a lead frame and a forward chip. The lead frame comprises a tube core pad and a lead arranged on the periphery of the tube core pad. A through hole corresponding to a lead is arranged on the tube core pad and arranged on the periphery of the tube core pad. The surface of the common chip, opposite to a substrate, is glued with the tube core pad, and a signal solder pad on the forward chip is electrically connected with the lead frame by penetrating a bonding wire through the through hole. The semiconductor chip encapsulation structure invention not only has reduced manufacture cost, but also can obtain low functional/grounding impedance and improves the electrical properties of devices.
Description
Technical field
The present invention relates to semiconductor chip package and method for packing.
Background technology
Along with the demand of miniaturization, lightweight and the multifunction of electronic component day by day increases, cause semiconductor packages density constantly to increase, thereby shared area must dwindle package dimension and encapsulation the time.Develop in the technology that for satisfying above-mentioned demand, the semiconductor die package technology has far-reaching contribution for whole cost, usefulness and the reliability of packaged chip.
Yet, in the semiconductor die package process, because the encapsulation of positive cartridge chip, need positive cartridge chip be connected with lead frame with adhesive, and need encapsulate with the bonding line bonding, and bonding line bonding type package is electrically connected path length, thereby thermal characteristics and electrical characteristics are not good, are not suitable for premium quality product.
In addition, in the encapsulating structure of positive cartridge chip, improve in order to make I/O (I/O) wire bond rate, the pin on the lead frame is bigger than the bonding pad area on the chip usually.In order to encapsulate, generally need provide the coupling of the peripheral pads on a hundreds of I/O pin and the chip on the lead frame.
But because the restriction of the physical dimension of lead frame, the space between the size of lead-in wire and lead-in wire can be very little, like this electrical property of the induction coefficient of the bonding line that the lead-in wire on the lead frame is connected with pad on chip meeting limited chip encapsulation.
For solving the above-mentioned patent No. is that the technical scheme of the U.S. Patent Publication of US5386141 has been described with the chip-stacked method that encapsulates on lead frame of formal dress as illustrated in fig. 1 and 2, Fig. 2 is the vertical view of lead frame among Fig. 1, lead frame 10 comprises the die pad 14 of carries chips 12, lead 22 and the outer lead 20 that is connected with lead 22, wherein lead 22 closes on die pad 14; Die pad 14 is as first conductive layer; Outer lead 20 is used for connecting power supply terminal, and lead 22 is connected with die pad 14 by bonding line 24; In addition, 14 4 jiaos of support bars that connect of die pad do not disconnect die pad 14 with whole lead frame.Except that above-mentioned situation, lead 22 can extend directly and is connected with die pad 14, has substituted employing bonding line 24 and has connected.In Fig. 2, die pad 14 is connected with pad 28 on the chip by bonding line 26.
With reference to figure 1, be formed with adhesive phase 30 on the die pad 14 again, polymeric media layer 32 is bonding by adhesive phase 30 and die pad 14.Be formed with metal level 34 and conductive layer 36 on polymeric media layer 32 successively, the material of described conductive layer 36 can be a gold, is used for welding chip 12.
With reference to figure 2, wherein one group of lead-in wire 40 connects pad 42 and the conductive layers 36 on the chips 12; Another group lead-in wire 48 connects the power voltage source that is applicable to chip 12.Wherein metal level 34 and conductive layer 36 have the effect of distributing to chip 12 functions equally as the conductive layer beyond the die pad 14, do not have through hole to be connected between die pad 14 and metal level 34 and the conductive layer 36.
This method for packing is connected with I/O signal pad on the chip by adopting metal level and conductive layer, by adopt a plurality of conductive layers to improve because the too concentrated electric current that causes of distribute power is excessive, and make the increase of I/O weld size.
But above-mentioned method for packing more complicated spends higherly, and can't reduce the area of whole packaging body.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor chip package and method for packing, prevents to make complexity, and cost improves.
For addressing the above problem, the invention provides a kind of semiconductor chip package, comprising: lead frame and positive cartridge chip, described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery; The through hole corresponding with lead-in wire arranged on the die pad and be positioned at the die pad edge; The substrate opposite face of positive cartridge chip is bonding with die pad and pass through hole by bonding line the signal pad on the positive cartridge chip is electrically connected with lead frame.
Optionally, described signal pad is I/O signal pad or ground signalling pad or reference voltage signal pad.
Optionally, to be connected with lead frame be to be connected with the lead-in wire of lead frame or to be connected with the die pad of lead frame or simultaneously with the die pad of lead frame with go between and be connected for described signal pad.
Optionally, the through hole edge is not being communicated with lead-in wire of sealing, or open being communicated with lead-in wire.
Optionally, the material of described bonding line is gold, copper, aluminium or albronze.
Optionally, just cartridge chip is bonded on the die pad by film-insulated isolated substance.Described film-insulated isolated substance is an organic compound, is epoxy resin or polyimides.
The present invention also provides a kind of semiconductor die package method, comprises the following steps: to provide lead frame and positive cartridge chip, and described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery, through hole wherein arranged on the die pad and be positioned at the die pad edge; The substrate opposite face of positive cartridge chip is bonded on the die pad; Bonding line passes through hole the signal pad on the positive cartridge chip is electrically connected with lead frame; With positive cartridge chip, lead-frame packages moulding.
Optionally, described signal pad is I/O signal pad or ground signalling pad or reference voltage signal pad.
Optionally, to be connected with lead frame be to be connected with the lead-in wire of lead frame or to be connected with the die pad of lead frame or simultaneously with the die pad of lead frame with go between and be connected for described signal pad.
Optionally, the through hole edge is not being communicated with lead-in wire of sealing, or open being communicated with lead-in wire.
Optionally, the material of described bonding line is gold, copper, aluminium or albronze.
Optionally, just cartridge chip is bonded on the die pad by film-insulated isolated substance.Described film-insulated isolated substance is an organic compound, is epoxy resin or polyimides.
Compared with prior art, the present invention has the following advantages: through hole is arranged on die pad, and through hole is positioned at the die pad edge, the follow-up chip of installing in the die pad both sides is placed by equidirectional, so chip internal wiring symmetry of die pad both sides, the semiconductor die package process is simplified, improved the flexibility and the effect of processing procedure; Utilize the through hole on the die pad, add simultaneously bonding line can be up and down before the latter linked degree of freedom, be equivalent to provide the function of multilayer joint face, reduce manufacturing cost greatly.
In addition, bonding line passes through hole the signal pad on the positive cartridge chip is electrically connected with lead frame, and need not form other conductive layers on die pad again, has not only reduced manufacturing cost, can also obtain low function/impedance ground, and the electrical property of device is improved.
Description of drawings
Fig. 1 is the schematic diagram of the semiconductor chip package of prior art formation;
Fig. 2 is the vertical view of lead frame among Fig. 1;
Fig. 3 is the embodiment flow chart that technology of the present invention is carried out semiconductor die package;
Fig. 4 is the first embodiment lead frame schematic diagram of semiconductor die package of the present invention;
Fig. 5 A, Fig. 5 B, Fig. 5 C are respectively first example, second example, the 3rd example schematic that technology of the present invention is carried out first embodiment of semiconductor die package;
Fig. 6 is the second embodiment lead frame schematic diagram of semiconductor die package of the present invention;
Fig. 7 A, Fig. 7 B, Fig. 7 C are respectively first example, second example, the 3rd example schematic that technology of the present invention is carried out second embodiment of semiconductor die package.
Embodiment
The present invention has through hole on die pad, and through hole is positioned at the die pad edge, and the follow-up chip of installing in the die pad both sides is placed by equidirectional, so the chip internal wiring symmetry of die pad both sides, the semiconductor die package process is simplified, improved the flexibility and the effect of processing procedure; Utilize the through hole on the die pad, add simultaneously bonding line can be up and down before the latter linked degree of freedom, be equivalent to provide the function of multilayer joint face, reduce manufacturing cost greatly.In addition, bonding line passes through hole the signal pad on the positive cartridge chip is electrically connected with lead frame, and need not form other conductive layers on die pad again, and not only the manufacturing cost of Jiang Diing can also obtain low function/impedance ground, and the electrical property of device is improved.
Fig. 3 is the embodiment flow chart that technology of the present invention is carried out semiconductor die package.As shown in Figure 3, execution in step S11 provides lead frame and positive cartridge chip, and described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery, through hole wherein arranged on the die pad and be positioned at the die pad edge; Execution in step S12 is bonded in the substrate opposite face of positive cartridge chip on the die pad; Execution in step S13, bonding line pass through hole the signal pad on the positive cartridge chip are electrically connected with lead frame; Execution in step S14 is with positive cartridge chip, lead-frame packages moulding.
Semiconductor chip package based on above-mentioned execution mode forms comprises: lead frame and positive cartridge chip, and described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery; The through hole corresponding with lead-in wire arranged on the die pad and be positioned at the die pad edge; The substrate opposite face of positive cartridge chip is bonding with die pad and pass through hole by bonding line the signal pad on the positive cartridge chip is electrically connected with lead frame.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 4 is the first embodiment lead frame schematic diagram of semiconductor die package of the present invention.As shown in Figure 4, lead frame 400 comprises die pad 404 and is positioned at lead-in wire A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and the B ' of die pad 404 peripheries that lead-in wire A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ' stretch out with comb shape and separate with die pad 404; Sealing through hole 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44 is arranged on the described die pad 404, and described sealing through hole 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44 is positioned at die pad 404 edges; Wherein seal through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 with 44 big or small identical, and sealing through hole 22 is corresponding with the B that goes between, sealing through hole 23 is corresponding with lead-in wire C, sealing through hole 24 is corresponding with lead-in wire D, sealing through hole 25 is corresponding with lead-in wire E, sealing through hole 26 is corresponding with lead-in wire F, sealing through hole 28 is corresponding with lead-in wire I, sealing through hole 29 is corresponding with lead-in wire J, sealing through hole 30 is corresponding with lead-in wire K, sealing through hole 31 is corresponding with lead-in wire L, sealing through hole 32 is corresponding with lead-in wire M, sealing through hole 34 is corresponding with lead-in wire P, sealing through hole 35 is corresponding with lead-in wire Q, sealing through hole 36 is corresponding with lead-in wire R, sealing through hole 37 is corresponding with lead-in wire S, sealing through hole 38 is corresponding with lead-in wire T, sealing through hole 40 is corresponding with lead-in wire W, sealing through hole 41 is corresponding with lead-in wire X, sealing through hole 42 is corresponding with lead-in wire Y, sealing through hole 43 is corresponding with lead-in wire Z and sealing through hole 44 is corresponding with lead-in wire A '; And lead-in wire A and the corresponding same sealing through hole 21 of lead-in wire B ', lead-in wire G and the corresponding same sealing through hole 27 of lead-in wire H, lead-in wire O and the corresponding same sealing through hole 33 of lead-in wire N, lead-in wire U and the corresponding same sealing through hole 39 of lead-in wire V.
In the present embodiment, the shared sealing through hole 21 of lead-in wire A lead-in wire B ', the shared sealing through hole 27 of lead-in wire G and lead-in wire H, the shared sealing through hole 33 of lead-in wire O and lead-in wire N, the shared sealing through hole 39 of lead-in wire U and lead-in wire V is to avoid reducing the overall construction intensity of die pad 404.
In the present embodiment, sealing through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 with 44 big or small identical, for greater than 0.2mm * 0.2mm; Sealing through hole 21,27,33 with 39 big or small consistent, for greater than 0.4mm * 0.4mm; Except that embodiment, as long as the size of sealing through hole 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44 does not disconnect die pad 404 with whole lead frame 400, and makes the zone that carries chips is arranged on the die pad 404.
In the present embodiment, 404 4 jiaos of support bars 411 that connect of die pad are used to support die pad 404, not only make it firm, and prevent that die pad 404 and whole lead frame 400 from disconnecting.
Except that embodiment, sealing through hole 22,23,24,25,26 can be a shared through hole; 28,29,30,31,32 can be a shared through hole; Sealing through hole 34,35,36,37,38 can be a shared through hole; Sealing through hole 40,41,42,43 and 44 can be a shared through hole.
Fig. 5 A, Fig. 5 B, Fig. 5 C are respectively first example, second example, the 3rd example schematic that technology of the present invention is carried out first embodiment of semiconductor die package.Shown in Fig. 5 A, at first, positive cartridge chip 200 is just being put on the die pad 404 of the lead frame 400 that is assemblied in as shown in Figure 4, and by adhesive phase 405 that the substrate opposite face and the die pad 404 of positive cartridge chip 200 band signal pads 202 is bonding; Then, the sealing through hole 407 (label is 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44 among Fig. 4) that passes on the die pad 404 by bonding line 408 carries out corresponding electrical connection with the signal pad 202 on the positive cartridge chip 200 with lead-in wire 402 (label is A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ' among Fig. 4) on the lead frame 400.
Shown in Fig. 5 B, at first, positive cartridge chip 200 is just being put on the die pad 404 of the lead frame 400 that is assemblied in as shown in Figure 4, and by adhesive phase 405 that the substrate opposite face and the die pad 404 of positive cartridge chip 200 band signal pads 202 is bonding; Then, the sealing through hole 407 (label is 21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44 among Fig. 4) that passes on the die pad 404 by bonding line 408 carries out corresponding electrical connection with the pad on the die pad 404 of the signal pad 202 on the positive cartridge chip 200 and lead frame 400.
Shown in Fig. 5 C, at first, positive cartridge chip 200 is just being put on the die pad 404 of the lead frame 400 that is assemblied in as shown in Figure 4, and by adhesive phase 405 that the substrate opposite face and the die pad 404 of positive cartridge chip 200 band signal pads 202 is bonding; Then, (label is 21 among Fig. 4 to pass sealing through hole 407 on the die pad 404 by bonding line 408,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43 and 44) with the signal pad 202 on the positive cartridge chip 200 respectively with lead frame 400 on die pad 404 on pad and go between 402 (label be A among Fig. 4, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ') carry out the correspondence electrical connection, the function pads on the die pad 404 is connected with lead-in wire.
In the present embodiment, described adhesive phase 405 is film-insulated separators, and material is an organic compound, concrete example such as epoxy resin or polyimides.
Described signal pad 202 refers to I/O signal pad or ground signalling pad or reference voltage signal pad etc.Its material is a metal or alloy, concrete example such as copper, aluminium or albronze.
The material of bonding line 408 is gold, copper, aluminium or albronze.
Except that embodiment, the stacked package that can also be used for the multicore sheet, for example just do not putting one second positive cartridge chip of assembling again on the lead frame 400 of homonymy with positive cartridge chip 200, and the second formal dress chip base face is bonding by adhesive phase and lead frame, radiator is installed on the basal surface of positive cartridge chip 200 then equally is used for heat radiation, and then improve electrical property; In addition can also be on positive cartridge chip 200 again with the substrate opposite face of tape welding dish and lead frame is bonding and bonding line passes sealing through hole on the lead frame, on positive cartridge chip 200, just putting one the 3rd positive cartridge chip of assembling, and the substrate opposite face of the tape welding dish of the 3rd positive cartridge chip is bonding with positive cartridge chip 200 basal surfaces by adhesive phase, at the basal surface of the 3rd positive cartridge chip radiator is installed then and is used for heat radiation, and then improve electrical property.
Continue with reference to figure 5A, Fig. 5 B and Fig. 5 C, lead frame 400 comprises die pad 404 and is positioned at the lead-in wire 402 of die pad 404 peripheries, wherein have sealing through hole 407 on the die pad 404, and sealing through hole 407 is positioned at die pad 404 edges; Positive cartridge chip 200 is positioned on the lead frame 400, and bonding by adhesive phase 405 and die pad 404, wherein with die pad 404 bonding be the substrate opposite face; Signal pad 202 is positioned at the substrate opposite face of positive cartridge chip 200; Bonding line 408, pass sealing through hole 407 with the pad on signal pad 202 and lead-in wire 402 or the die pad 404 or simultaneously with go between 402 and die pad 404 on pad be electrically connected.
Fig. 6 is the second embodiment lead frame schematic diagram of semiconductor die package of the present invention.Lead frame 400 comprises die pad 404 and is positioned at lead-in wire A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and the B ' of die pad 404 peripheries that lead-in wire A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ' stretch out with comb shape and separate with die pad 404; Open through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44 is arranged on the described die pad 404, sealing through hole 21,27,33 and 39, described open through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44 disconnects at die pad 404 edges, is communicated with corresponding lead-in wire; Wherein open through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 with 44 big or small identical, and open through hole 22 is corresponding with the B that goes between, open through hole 23 is corresponding with lead-in wire C, open through hole 24 is corresponding with lead-in wire D, open through hole 25 is corresponding with lead-in wire E, open through hole 26 is corresponding with lead-in wire F, open through hole 28 is corresponding with lead-in wire I, open through hole 29 is corresponding with lead-in wire J, open through hole 30 is corresponding with lead-in wire K, open through hole 31 is corresponding with lead-in wire L, open through hole 32 is corresponding with lead-in wire M, open through hole 34 is corresponding with lead-in wire P, open through hole 35 is corresponding with lead-in wire Q, open through hole 36 is corresponding with lead-in wire R, open through hole 37 is corresponding with lead-in wire S, open through hole 38 is corresponding with lead-in wire T, open through hole 40 is corresponding with lead-in wire W, open through hole 41 is corresponding with lead-in wire X, open through hole 42 is corresponding with lead-in wire Y, open through hole 43 is corresponding with lead-in wire A ' with the corresponding and open through hole 44 of lead-in wire Z; And lead-in wire A and the corresponding same sealing through hole 21 of lead-in wire B ', lead-in wire G and the corresponding same sealing through hole 27 of lead-in wire H, lead-in wire O and the corresponding same sealing through hole 33 of lead-in wire N, lead-in wire U and the corresponding same sealing through hole 39 of lead-in wire V.
In the present embodiment, the shared sealing through hole 21 of lead-in wire A lead-in wire B ', the shared sealing through hole 27 of lead-in wire G and lead-in wire H, the shared sealing through hole 33 of lead-in wire O and lead-in wire N, the shared sealing through hole 39 of lead-in wire U and lead-in wire V is to avoid reducing the overall construction intensity of die pad 404.
In the present embodiment, open through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 with 44 big or small identical, be 0.2mm * 0.3mm; The sealing through hole 21,27,33 with 39 big or small consistent, be 0.4mm * 0.4mm; Except that embodiment, open through hole 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44 and the size of sealing through hole 21,27,33 and 39 can be that die pad 404 is not disconnected with whole lead frame 400, and make the zone that carries chips is arranged on the die pad 404.
In the present embodiment, 404 4 jiaos of support bars 411 that connect of die pad are used to support die pad 404, not only make it firm, and prevent that die pad 404 and whole lead frame 400 from disconnecting.
Except that embodiment, open through hole 22,23,24,25,26 can be a shared through hole; 28,29,30,31,32 can be a shared through hole; Open through hole 34,35,36,37,38 can be a shared through hole; Open through hole 40,41,42,43 and 44 can be a shared through hole.
Fig. 7 A, Fig. 7 B, Fig. 7 C are respectively first example, second example, the 3rd example schematic that technology of the present invention is carried out second embodiment of semiconductor die package.Shown in Fig. 7 A, at first, positive cartridge chip 200 is positioned on the die pad 404 of lead frame 400 as shown in Figure 6, and it is the substrate opposite face and the die pad 404 of positive cartridge chip 200 is bonding by adhesive phase 405, has signal pad 202 on the described positive cartridge chip 200, positive cartridge chip 200 surfaces that wherein have signal pad 202 are the substrate opposite face, and corresponding with the substrate opposite face is basal surface; Bonding line 408 passes the open through hole 407 (label among Fig. 6 is 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44) on the die pad 404, and the signal pad 202 on the positive cartridge chip 200 is carried out corresponding electrical connection with lead-in wire 402 (label is A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ' among Fig. 6) on the lead frame 400.
Shown in Fig. 7 B, at first, positive cartridge chip 200 is positioned on the die pad 404 of lead frame 400 as shown in Figure 6, and it is the substrate opposite face and the die pad 404 of positive cartridge chip 200 is bonding by adhesive phase 405, has signal pad 202 on the described positive cartridge chip 200, positive cartridge chip 200 surfaces that wherein have signal pad 202 are the substrate opposite face, and corresponding with the substrate opposite face is basal surface; Bonding line 408 passes the open through hole 407 (label among Fig. 6 is 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44) on the die pad 404, and the pad on the die pad 404 of the signal pad 202 on the positive cartridge chip 200 and lead frame 400 is carried out corresponding electrical connection.
Shown in Fig. 7 C, at first, positive cartridge chip 200 is positioned on the die pad 404 of lead frame 400 as shown in Figure 6, and it is the substrate opposite face and the die pad 404 of positive cartridge chip 200 is bonding by adhesive phase 405, has signal pad 202 on the described positive cartridge chip 200, positive cartridge chip 200 surfaces that wherein have signal pad 202 are the substrate opposite face, and corresponding with the substrate opposite face is basal surface; Bonding line 408 passes open through hole 407 on the die pad 404, and (label among Fig. 6 is 22,23,24,25,26,28,29,30,31,32,34,35,36,37,38,40,41,42,43 and 44), with the signal pad 202 on the positive cartridge chip 200 respectively with lead frame 400 on die pad 404 on pad and go between 402 (label be A among Fig. 4, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, A ' and B ') carry out the correspondence electrical connection, the function pads on the die pad 404 is connected with lead-in wire.
Except that embodiment, the stacked package that can also be used for the multicore sheet, for example just do not putting one second positive cartridge chip of assembling again on the lead frame 400 of homonymy with positive cartridge chip 200, and the second formal dress chip base face is bonding by adhesive phase and lead frame, radiator is installed on the basal surface of positive cartridge chip 200 then equally is used for heat radiation, and then improve electrical property; In addition can also be on positive cartridge chip 200 again with the substrate opposite face of tape welding dish and lead frame is bonding and bonding line passes sealing through hole on the lead frame, on positive cartridge chip 200, just putting one the 3rd positive cartridge chip of assembling, and the substrate opposite face of the tape welding dish of the 3rd positive cartridge chip is bonding with positive cartridge chip 200 basal surfaces by adhesive phase, at the basal surface of the 3rd positive cartridge chip radiator is installed then and is used for heat radiation, and then improve electrical property.
Continue with reference to figure 7A, Fig. 7 B and Fig. 7 C, lead frame 400 comprises die pad 404 and is positioned at the lead-in wire 402 of die pad 404 peripheries, wherein have open through hole 407 on the die pad 404, and open through hole 407 is positioned at die pad 404 edges; Positive cartridge chip 200 is positioned on the lead frame 400, and bonding by adhesive phase 405 and die pad 404, wherein with die pad 404 bonding be the substrate opposite face; Signal pad 202 is positioned at the substrate opposite face of positive cartridge chip 200; Bonding line 408 passes open through hole 407 with the pad on signal pad 202 and lead-in wire 402 or the die pad 404 or be electrically connected with pad on lead-in wire 402 and the die pad 404 simultaneously.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. semiconductor chip package, comprise: lead frame and positive cartridge chip, described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery, it is characterized in that, have with the corresponding through hole of lead-in wire on the die pad and be positioned at the die pad edge, just the substrate opposite face of cartridge chip is bonding with die pad and pass through hole by bonding line the signal pad on the positive cartridge chip is electrically connected with lead frame.
2. semiconductor chip package according to claim 1 is characterized in that: described signal pad is I/O signal pad or ground signalling pad or reference voltage signal pad.
3. semiconductor chip package according to claim 1 is characterized in that: it is to be connected with the lead-in wire of lead frame or to be connected or to be connected with lead-in wire with the die pad of lead frame simultaneously with the die pad of lead frame that described signal pad is connected with lead frame.
4. semiconductor chip package according to claim 1 is characterized in that: the through hole edge is not being communicated with lead-in wire of sealing, or open being communicated with lead-in wire.
5. semiconductor chip package according to claim 1 is characterized in that: the material of described bonding line is gold, copper, aluminium or albronze.
6. semiconductor chip package according to claim 1 is characterized in that: positive cartridge chip is bonded on the die pad by film-insulated isolated substance.
7. semiconductor chip package according to claim 6 is characterized in that: described film-insulated isolated substance is an organic compound, is epoxy resin or polyimides.
8. a semiconductor die package method is characterized in that, comprises the following steps:
Lead frame and positive cartridge chip are provided, and described lead frame comprises die pad and is positioned at the lead-in wire of die pad periphery, through hole wherein arranged on the die pad and be positioned at the die pad edge;
The substrate opposite face of positive cartridge chip is bonded on the die pad;
Bonding line passes through hole the signal pad on the positive cartridge chip is electrically connected with lead frame; With positive cartridge chip, lead-frame packages moulding.
9. semiconductor die package method according to claim 8 is characterized in that: described signal pad is I/O signal pad or ground signalling pad or reference voltage signal pad.
10. semiconductor die package method according to claim 8 is characterized in that: it is to be connected with the lead-in wire of lead frame or to be connected or to be connected with lead-in wire with the die pad of lead frame simultaneously with the die pad of lead frame that described signal pad is connected with lead frame.
11. semiconductor die package method according to claim 8 is characterized in that: described through hole edge can be not being communicated with lead-in wire of sealing, also can be open being communicated with lead-in wire.
12. semiconductor die package method according to claim 8 is characterized in that: the material of described bonding line is gold, copper, aluminium or albronze.
13. semiconductor die package method according to claim 8 is characterized in that: positive cartridge chip is bonded on the die pad by film-insulated isolated substance.
14. semiconductor die package method according to claim 13 is characterized in that: described film-insulated isolated substance is an organic compound, is epoxy resin or polyimides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910195984.2A CN102024777A (en) | 2009-09-18 | 2009-09-18 | Semiconductor chip encapsulation structure and encapsulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910195984.2A CN102024777A (en) | 2009-09-18 | 2009-09-18 | Semiconductor chip encapsulation structure and encapsulation method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102024777A true CN102024777A (en) | 2011-04-20 |
Family
ID=43865901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910195984.2A Pending CN102024777A (en) | 2009-09-18 | 2009-09-18 | Semiconductor chip encapsulation structure and encapsulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102024777A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315192A (en) * | 2011-09-20 | 2012-01-11 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging part |
| CN111987069A (en) * | 2020-08-28 | 2020-11-24 | 西安微电子技术研究所 | Glue locking array lead frame and application thereof in chip packaging part |
-
2009
- 2009-09-18 CN CN200910195984.2A patent/CN102024777A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315192A (en) * | 2011-09-20 | 2012-01-11 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging part |
| CN111987069A (en) * | 2020-08-28 | 2020-11-24 | 西安微电子技术研究所 | Glue locking array lead frame and application thereof in chip packaging part |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102420217B (en) | Multi-chip semiconductor packages and assembling thereof | |
| US7557454B2 (en) | Assemblies with bond pads of two or more semiconductor devices electrically connected to the same surface of a plurality of leads | |
| CN100499104C (en) | Flip chip contact(PCC) power package and package method | |
| US9263375B2 (en) | System, method and apparatus for leadless surface mounted semiconductor package | |
| CN101211897B (en) | Multi-chip semiconductor packaging structure and encapsulation method | |
| US8058720B2 (en) | Semiconductor package | |
| TWI520240B (en) | Power lead-on-chip ball grid array package | |
| US20100270667A1 (en) | Semiconductor package with multiple chips and substrate in metal cap | |
| CN102610583B (en) | Package carrier and method for manufacturing the same | |
| CN102903693A (en) | Power device package module and manufacturing method thereof | |
| US9466588B2 (en) | Method and apparatus for multi-chip structure semiconductor package | |
| CN102024770A (en) | Semiconductor chip package structure and package method | |
| CN103915405A (en) | Semiconductor device and method of making a semiconductor device | |
| KR102228945B1 (en) | Semiconductor package and method of fabricating the same | |
| US7737551B2 (en) | Semiconductor power module with SiC power diodes and method for its production | |
| CN101183673A (en) | Stacked multi-chip semiconductor package structure and package method | |
| TW200425456A (en) | Multi-chip package with electrical interconnection | |
| CN102024777A (en) | Semiconductor chip encapsulation structure and encapsulation method | |
| CN102222627A (en) | Packaging method possessing wafer dimension paster | |
| US20080179726A1 (en) | Multi-chip semiconductor package and method for fabricating the same | |
| CN103354228A (en) | Semiconductor packaging part and manufacturing method thereof | |
| CN100468728C (en) | Multiple chip semi-conductor packaging structure and encapsulation method | |
| CN100561724C (en) | Semiconductor chip package and method for packing | |
| CN101894811A (en) | Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof | |
| CN217691140U (en) | Flip-chip gallium nitride power device capable of improving heat dissipation performance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110420 |