CN1020028C - Method of fabricating implanted wells and islands of cmos integrated circuits - Google Patents

Abstract

A method is disclosed for forming implanted wells and islands of CMOS integrated circuits with a retrograde profile, i.e., with wells and islands having a smaller penetration depth, shallower doping profile, and less lateral diffusion than in conventional CMOS circuits.

Description

Method of fabricating implanted wells and islands of cmos integrated circuits

What the present invention relates to is: in the CMOS silicon integrated circuit, be in the complementary type isolated-gate field effect transistor (IGFET) circuit, make the injection trap of CMOS integrated circuit and the method on island, wherein in a kind of substrate of conduction type, a trap that has another kind of conduction type at least, and having an island identical near it at least with the substrate conduction type, its doping content is denseer than substrate, carries out several secondary ions with the silicon dioxide/silicon nitride mask structure with photoresist and injects and form.

Usually, the CMOS technology of standard, trap has occupied bigger space.If increase integrated level, the degree of depth of trap must reduce.Yet, so, will increase the vertical current gain of parasitic bipolar transistor, thereby increased the danger (risk of latch up) of pinning.

A kind of method that addresses this problem is, as the IEEE Trans.Electron Dev.(1981.10 month, and 115 pages-119 pages) described unusual trap technology.Unusual trap technology is, makes the trap and the island of shallow dopant profiles, and reduces horizontal proliferation, and wherein doping content at first increases along with the increase of the degree of depth, and then descends along with the increase of the degree of depth.Unlike the situation in the habitual trap, in habitual trap, doping content is along with the increase of the degree of depth constantly descends.Use the method, surface doping concentration can be reduced to the required the sort of low concentration of MOS transistor.But, still can reach sufficiently high total concentration, so can make the current gain of parasitic bipolar transistor enough little.

When making unusual trap, unlike conventional cmos technology, at first carry out the field oxidation on the trap fringe region, and then do ion and inject, remake common short time annealing in process subsequently, so that the ion that injects spreads inwards.

Make two traps if use common manufacture craft, so-called two trap is exactly the trap and the island of arranging one by one, and wherein has a P trench transistor and a n trench transistor at least, in the second step photoetching process, it is necessary using an opposite trap reticle.Therefore, the doping content of marginal zone depends on the thickness of field oxide, the injection doping content of the gradient at field oxide edge and trap.If the doping content of fringe region can Be Controlled and don't depended on these parameters, carry out injecting also essential two additional reticle.Because alignment tolerance is arranged, this just leads the increase that has changed spacing.

The objective of the invention is to improve the technology of being narrated in the document above-mentioned, make it when making two trap, do not need the reticle of adding, and the performance of the device of producing still keeps the advantage of original technology.Particularly integration density does not increase, and has kept preventing the ability of pinning.

Description illustrates the present invention:

Fig. 1-Fig. 3 makes to have n trap and P ⁺In a kind of embodiment of the cmos circuit on island, the schematic sectional view of expression processing step.

Fig. 4-Fig. 9 makes to have n trap and P ⁺In a kind of improved embodiment of the cmos circuit on island, the schematic sectional view of expression processing step.

As shown in Figure 1, (for clarity sake, not drawing in proportion) makes cmos circuit, begins with P type substrate 1, and it can be a material (not shown) with epitaxial loayer.At substrate 1 or on epitaxial loayer, the most handy thermal oxidation method forms a thin silicon dioxide layer 21 in step a.The connotation that " approaches " is meant that layer 21 has common grid one thickness of oxide layer.Silicon nitride layer 22 of deposit on layer 21 then.This two- layer 21 and 22 formation double-deck 2.

Among the step b, with silicon nitride layer 22 or whole double-deck 2, with common photoetching process etching, just be coated with one deck photoresist,, wash the photoresist of unexposed portion off by the reticle exposure, (or the glue after the exposure), figure is with photoresist made mask, corrosion double-deck 2 or layer 22.In this way, the whole fringe region of the trap that form 71 and will form the whole fringe region 72 on island, and the substrate surface (perhaps only silicon dioxide layer 21) that is in the mid portion 73 between trap and the island fringe region has just removed covering.The interior zone on trap and island wherein, just in the ring that forms with separately fringe region, stay two-layer 21 and 22(see Fig. 1 and Fig. 2), if fringe region 71 and 72 contacts or has overlappingly each other slightly, just do not have zone line 73.

Among the step c, coat photoresist layer 41, then photoetching and the corrosion so that limit formed n trap 61 whole regional 5 in bilayer 2 parts, yet cover the P that will form ⁺Double-deck part in 62 zones 8, island.

In the steps d, when the first step is injected, the high-energy phosphonium ion, for example, just the ion of trap conduction type is about 300KV with accelerating voltage and injects.The effect such as the same mask of photoresist layer 41 inject thereby injected trap 61(trap at this moment).

Among the step e, be the second low-yield injection of step, use be phosphonium ion or arsenic ion, for example, the accelerating voltage of injection is about 40KV, the layer in photoresist layer 41 and the n well area 5 is 21 and 22 as mask, thereby mixed fringe region 71, fringe region 71 is n ⁺Type.(being that the edge injects I).

The result of described processing step so far as shown in Figure 1.

Among the step f, remove photoresist layer 41.

In the step g, under suitable temperature, the injection ion is spread inwards, form trap 61 and edge 71 thereof.

Step h makes another photoresist layer 42, photoetching and corrosion, and photoresist covers trap 61, but stays P ⁺The zone 8 on island forms the non-area of coverage, referring to Fig. 2 (island photoetching process).

Repeating step d-g as steps d '-g ', under other conditions, use other doping impurity.

Steps d ', be to inject in the 3rd step, inject island 62, with the ion of substrate conduction type, for example, use high-energy boron ion, the accelerating voltage of injection is about 180KV, and 42 play mask effect (island injection) with photoresist.

Step e ' is to inject in the 4th step, and its energy is lower than the island and injects energy, for example, use be boron or BF ₂Ion, the accelerating voltage of injection be 10KV to 40KV, wherein the layer 21,22 on photoresist layer 42 and the zone, island 62 works the mask effect of injecting of preventing again, fringe region 72 is injected into P ⁺⁺Type zone (edge injection II).

The result of described processing step so far as shown in Figure 2.

Step f ' removes photoresist layer 42, step g ' in, the ion of injection is under proper temperature, diffusion inwards forms P ⁺The P on type island 62 and island ⁺⁺Type marginal zone 72.

At last,, thermal oxidation is carried out in marginal zone 71,72 and zone line 73, form field oxide layer 9, still keep double-deck 2 parts simultaneously, just remove with etch at trap 61 and the part above 62 interior zones of island at step j.

In technical process subsequently, the first step, gate oxide layers 11,12 normally forms with thermal oxidation method at above-mentioned interior zone, and its result is as shown in Figure 3.After this needed cmos circuit is made with method commonly used.

To above-mentioned processing step, promptly remove after the photoresist mask 42, spread the ion of the substrate conduction type that injects inwards, as the boron ion, form the technology of oxide skin(coating) subsequently, can adopt preferable embodiment of the present invention: above-mentioned two processing steps are combined, just step g ' and step j finish simultaneously.

In another embodiment of the invention, the ion of substrate and trap conduction type, just boron and phosphonium ion, no longer be to spread respectively, the method that replaces is to spread simultaneously in a step and carry out an oxidation,, can obtain near identical diffusion depth in trap and island with the method.Thereby step g and g ' in step j, have been finished.

As Figure 1-3, the substrate surface that obtains with described method is quite uneven, and this may disturb processing step subsequently.

Explain development of the present invention by Fig. 4-Fig. 9 now.Here in a substrate, there are trap and island and one to come down to even curface.In fact the present invention is included in after the step f and reaches step k before the step h among n.

Step k, oxidized during step g with two- layer 21 and 22 substrate surfaces that cover, form thick oxide layer 10, its thickness and oxide layer 9 are comparable.And approximately be half of its thickness.Among the step k, thick oxide layers 10 forms simultaneously with trap.Its result as shown in Figure 4.

Step l under mask situation of no use, erodes thick oxide layers 10, and its result as shown in Figure 5.

Step m with the part that substrate surface exposes, carries out thermal oxidation, forms thin layer of silicon dioxide 23, silicon nitride layer 24 of deposit on thin layer 23, and its result is as shown in Figure 6.

Step n, on perpendicular to the substrate surface direction, silicon nitride layer 24 is anisotropically corroded.Obtain structure as shown in Figure 7 like this, wherein, horizontal nitride layer 22 be inclined upwardly the part (this inclination is that the formation of thick oxide layers causes) below, stay some nitride layers 24, this layer has a wall that is basically perpendicular to substrate.

After the step n, be step h, i(=d '), e ', f ', g ' and j.Fig. 8 is illustrated in step f ' structure afterwards.Fig. 9 is after step j, and the structure after forming gate oxide layers 11,12 with method similar to the above.

According to method of the present invention, not only be suitable for making the trap and the island of pure cmos circuit, can also be used to making the trap and the island of ambipolar-CMOS combinational circuit.

Fig. 4-improvement structure shown in Figure 9 can be used for making pure n-ditch circuit similarly.

Claims (5)

1, a kind of trap of ion injection and method on island of in CMOS silicon integrated circuit (complementary type isolated-gate field effect transistor (IGFET) circuit), making, wherein in the substrate (1) of a kind of conduction type (substrate conduction type), a trap (61) (trap conduction type) that has another kind of conduction type at least, and has an island identical near it at least with the substrate conduction type, its doping content is denseer than substrate (1), be to carry out several secondary ions with the silicon dioxide/silicon nitride mask arrangement with photoresist to inject formation, it is characterized in that the following step:

A) go up formation skim silicon dioxide layer (21) at substrate (1), and form one deck silicon nitride layer (22) thereon;

B) photoetching process of usefulness mask and corrosion, at least silicon nitride layer (22) is processed with the method, whole fringe region (71) with silicon dioxide layer (21) or substrate surface formation trap, form the whole fringe region (72) on island, and the zone line (73) between the fringe region on the fringe region of trap and island all is uncovered, wherein stay two-layer (21) in the interior zone on trap and island respectively, (22);

C) be coated with one deck photoresist (41), and carry out photoetching and corrosion so that determine the whole zone (5) (trap photoetching process) of trap (61);

D) there is photoresist layer (41) to make mask, injects the ion of high-octane trap conduction type;

E) there are photoresist layer (41) silicon dioxide (21) and silicon nitride layer (22) to make mask, inject the ion of low-yield trap conduction type;

F) remove photoresist layer (41);

G) spread the ion that injects inwards, to form trap (61) and fringe region (71), the doping content of fringe region is greater than the doping content of trap (61); The substrate surface part that simultaneous oxidation is not covered by silicon dioxide (21) and silicon nitride layer (22) is to form a thick-layer oxide skin(coating).

H) do not use mask etch to fall thick oxide layers (10);

I) the substrate surface part exposed of oxidation forming other one deck thin silicon dioxide layer (23), and forms other one deck silicon nitride layer (24) thereon;

J) anisotropically erode above-mentioned silicon nitride layer (24).

K) be coated with other one deck photoresist (42) and carry out photoetching and corrosion, make its Zone Full of stipulating out island (62) (8) (island photoetching process)

I) repeating step d-g as steps d '-g ', have the ion of substrate conduction type to form island (62) and fringe region (72), its doping content is greater than the concentration of island (62);

M) fringe region (71,72) that exposes of oxidation is if necessary gone up at zone line (73) and is formed a field oxide (9), then removes silicon dioxide and silicon nitride (21,22).

2, the method for claim 1 is characterized in that, spreads the step g of the ion of substrate conduction type ' finish simultaneously with step j inwards.

3, the method for claim 1 is characterized in that, inwards the step g of the formation trap (61) of diffusion ion and form the step g on island (62) ' finish simultaneously with step j.

4, as method as described in arbitrary among the claim 1-3, it is characterized in that, form a p trap or a p ⁺The method on island (62) forms with injecting high-energy boron ion, and coupled zone (72) are with injecting low-energy boron ion or BF ₂Ion forms.

5, as method as described in arbitrary among the claim 1-3, it is characterized in that, wherein n trap or n ⁺The island preferably forms with the high-energy phosphonium ion that injects the two positive charges of band, and adjacent fringe region (71) is to form with injecting low-energy phosphonium ion or arsenic ion.

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