CN101998772B - 加工芯板的空腔的方法和电子器件埋入式印刷电路板 - Google Patents

加工芯板的空腔的方法和电子器件埋入式印刷电路板 Download PDF

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CN101998772B
CN101998772B CN2010102632578A CN201010263257A CN101998772B CN 101998772 B CN101998772 B CN 101998772B CN 2010102632578 A CN2010102632578 A CN 2010102632578A CN 201010263257 A CN201010263257 A CN 201010263257A CN 101998772 B CN101998772 B CN 101998772B
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central layer
cavity
machining area
electronic device
thickness
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CN101998772A (zh
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郑珍守
李斗焕
朴华仙
李在杰
郑栗教
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明公开了一种加工芯板的空腔的方法。根据本发明实施方式的加工芯板的空腔的方法可以包括：在芯板的一个表面上形成第一加工区域，第一加工区域以电路图案为界；在芯板的另一表面上形成第二加工区域，第二加工区域以电路图案为界；以及通过将整个第一加工区域从芯板的一个表面上去除来加工空腔。

Description

加工芯板的空腔的方法和电子器件埋入式印刷电路板
相关申请交叉参考 
本申请要求分别于2009年10月27日和2009年8月25日向韩国知识产权局提交的韩国专利申请第10-2009-0102504号和第10-2009-0078738号的权益，其公开的全部内容结合于此作为参考。 
技术领域
本发明涉及一种加工芯板的空腔的方法。 
背景技术
为了制造电子器件埋入基板中的埋入式基板，需要在基板中加工作为用于装配电子器件的空间的空腔。可以通过冲孔方法(其是使用CNC钻孔机或模具的机械法)和使用激光(CO2激光或YAG激光)的钻孔方法等来在基板中加工空腔。 
当使用机械法加工空腔时，空腔的尺寸是不精确的，并且与基板的机械摩擦会潜在地在空腔的内壁上引起诸如毛头、裂纹和增白的缺陷。为此，通常使用激光钻机来加工空腔。 
在传统的方法中，在芯板上形成电路，然后通过对所暴露的绝缘层进行直接激光钻孔来形成空腔。在这种情况下，激光束去除一部分暴露的绝缘层来形成空腔，但是绝缘层的除空腔本身之外的区域也会被激光束损坏(变形)。此外，激光钻机的射束掩模的形状被转印到绝缘层的表面，从而降低了空腔尺寸的精度。 
发明内容
本发明提供了一种加工芯板的空腔的方法，该方法可以实现精确的空腔形状。 
本发明的一个方面公开了一种加工芯板的空腔的方法。根据本发明实施方式的加工芯板的空腔的方法可以包括：在芯板的一个表面上形成第一加工区域，第一加工区域以电路图案为界；在芯板的另一表面上形成第二加工区域，第二加工区域以电路图案为界；以及通过将整个第一加工区域从芯板的一个表面上去除来加工空腔。 
第二加工区域可以比第一加工区域宽，并且可以将第一加工区域的中心和第二加工区域的中心设置在同一垂直线上。第一加工区域和第二加工区域可以具有相似的形状。 
本发明的另外的方面和优点一部分将在随后的描述中进行阐述，而一部分从描述中是显而易见的，或者可以通过实践本发明来获知。 
附图说明
图1至图3示出了根据本发明实施方式的加工芯板的空腔的方法。 
图4至图5示出了根据本发明另一实施方式的加工芯板的空腔的方法。 
图6示出了具有层间偏心的空腔。 
图7示出了根据本发明另一实施方式的埋入在其中加工有空腔的芯板中的电子器件。 
图8A和图8B示出了根据本发明另一实施方式的第一加工区域和第二加工区域。 
图9是当电子器件和绝缘层彼此堆叠时的应力测试的模型图。 
图10是示出了不同厚度的绝缘层的应力的曲线图。 
图11是示出了不同厚度的绝缘层的翘曲的曲线图。 
图12是示出了根据本发明实施方式的电子器件埋入式印刷电路板的概念图。 
图13至图19示出了根据本发明实施方式的制造电子器件埋入式印刷电路板的过程。 
具体实施方式
由于可以存在本发明的多种变换和多个实施方式，因此，将参考附图来说明和描述特定的实施方式。然而，这绝不是将本发明限制于特定的实施方式，而应解释为包括被本发明的构思和范围覆盖的所有变换、等价物和替换。贯穿于本发明的说明书，当将特定技术的描述确定为脱离本发明的发明点时，将省略相关的详细描述。 
下文中，将参考附图详细地描述加工芯板的空腔的方法的特定实施方式。相同或相应的元件将赋予相同的参考标号而与图号无关，并且将不重复相同或相应元件的任何多余描述。 
图1至图3示出了根据本发明实施方式的加工芯板的空腔的方法。在图1至图3中示出芯板10、第一加工区域A1、第二加工区域A2、电路图案12、通孔14、绝缘层16、激光束L。 
首先，如图1所示，在芯板10的一个表面上(更具体地，在绝缘层16的一个表面上)形成以电路图案12为界的第一加工区域A1。这里，第一加工区域A1指的是绝缘层16被激光束直接照射的一侧上的表面。该第一加工区域A1以形成在绝缘层16的表面上的电路图案12为界。换而言之，没有被电路图案12覆盖而暴露的区域为第一加工区域A1。 
可以通过减成处理(subtractive process)、加成处理(additiveprocess)、喷墨处理以及其他各种处理来在绝缘层16的一个表面上形成电路图案12。 
在绝缘层16的另一个表面上形成以电路图案12为界的第二加工区域A2。与第一加工区域A1相同，第二加工区域A2以形成在绝缘层16的下表面上的电路图案12为界，并指的是没有被形成在芯板10的下表面上的电路图案12覆盖而暴露的区域。在本实施方式的情况下，第二加工区域A2被形成为与第一加工区域A1对称。即，第一加工区域A1和第二加工区域A2关于绝缘层16以相同的尺寸和形状形成在对称位置处。 
形成在绝缘层16的上表面和下表面上的电路图案12可以通过贯通绝缘层16的通孔14而彼此电连接。 
在如上所述形成第一加工区域A1和第二加工区域A2之后，通过利用激光束L将整个第一加工区域A1从芯板10的一个表面去除来形成空腔，如图2所示。通过如上所述的加工空腔，可以稳定地保证空腔的原始设计形状和尺寸W，这是因为空腔的形状以电路图案12为界，如图3所示。换而言之，空腔的尺寸由电路图案12确定。因此，可以提高空腔尺寸的精度，并可以改善空腔的内壁和表面的加工质量。图3示出了矩形加工区域以电路图案12为界，并且形成了矩形柱状的空腔。 
图4至图6示出了根据本发明另一实施方式的加工芯板10的空腔的方法。该实施方式与之前描述的实施方式的不同之处在于，形成的第二加工区域A2比第一加工区域A1宽。下文中，将主要描述之前所述的实施方式与本实施方式的差异。 
根据本实施方式，如图4所示，第二加工区A2被形成为比第一加工区域A1宽。图4示出了第一加工区域A1具有尺寸W1，而第二加工区域A2具有尺寸W2。 
通过设计和形成比第一加工区域A1大的第二加工区域A2，即使在将电路图案12a、12b形成在芯板10的上表面和下表面上时存在一定的层间偏心，也能够防止空腔的尺寸由于偏心而减小，并能够精确地加工具有期望尺寸的空腔。图5示出了使用激光束L加工空腔的方式。 
图6示出了由于层间偏心导致的尺寸减小的空腔的情况。如图6所示，当在芯板10的上下电路图案12之间存在偏心时，由形成在空腔中的斜面导致空腔具有比原始设计的空腔尺寸W1小的尺寸W3是不可避免的。即，减小了用于埋入电子器件20的空间。 
如图7所示，通过将第二加工区域A2形成为比第一加工区域A1大，第一加工区域A1与第二加工区域A2之间的尺寸差可以补偿偏心，并且可以获得原始设计的空腔尺寸。 
由于电路图案12a、12b的偏心可出现在x轴方向和y轴方向上，因此可以将第一加工区域A1的中心和第二加工区域A2的中心设置在同一垂直线上，以补偿电路图案12a、12b的偏心。图8A示出了第一加工区域A1的中心与第二加工区域A2的中心相重叠。 
此外，通过使第一加工区域A1和第二加工区域A2具有相似的形状，可以更充分地补偿电路图案12a、12b在每个方向上的偏心。图8A和图8B示出了第一加工区域A1和第二加工区域A2均具有正方形形状。 
下文中，将描述根据本发明另一方面的电子器件埋入式印刷电路板。 
图9是当电子器件和绝缘层彼此堆叠时的应力测试的模型图。图10是示出了应力随着绝缘层厚度的曲线图。图11是示出了翘曲随着绝缘层厚度的曲线图。图12是示出了根据本发明实施方式的电子器件埋入式印刷电路板的概念图。 
本实施方式公开了几何对称的电子器件埋入式结构和用于这种结构的电子器件埋入方法，以实现在重复热应力环境下将翘曲最小化的超薄、高可靠性的电子器件埋入式印刷电路板。基板在热应力下的翘曲由诸如热膨胀系数(CTE)、杨氏模量和泊松比的物理性质值以及所应用的材料的几何因素来确定。对于图9中所示的印刷电路板，中线可由下面的表达式来表示。 
y ‾ = E I t 2 + t d 2 ( E d - E I ) 2 ( E d t d + E I t I ) - - - ( 1 )
这里，EI为电子器件的杨氏模量，tI为电子器件的厚度(m)，Ed为绝缘层的杨氏模量(Pa)，td为绝缘层的厚度，以及t为基板的整个厚度(＝td+tI)。 
根据以上表达式计算的基板的挠矩M(由Nm表示)和法向力N(由N表示)由下面的表达式来表示。 
M 1 = M 2 = E I α I ΔTt I w ( t d + t I 2 - y ‾ ) + E d α d ΔTt d w ( t d 2 - y ‾ ) , M 6 = 0
N1＝N2＝EIαIΔTtIw+EdαdΔTtdw，N6＝0    (2) 
这里，EI为电子器件的杨氏模量，tI为电子器件的厚度，αI为电子器件的CTE，Ed为绝缘层的杨氏模量(Pa)，td为绝缘层的厚度，αd为绝缘层的CTE(m/K)，ΔT为温度(K)的变化，以及w为基板的宽度。 
根据以上表达式所计算的柔度矩阵可由下面的表达式来表示。 
S = 1 E x - v xy E x 0 - v yx E y 1 E y 0 0 0 1 G xy - - - ( 3 )
根据以上表达式所计算的刚度矩阵如下。 
Q＝S-1    (4) 
ABD矩阵可以由下面的表达式来表示。 
N 1 N 2 N 6 M 1 M 2 M 6 = A 11 A 12 A 16 B 11 B 12 B 16 A 21 A 22 A 26 B 21 B 22 B 26 A 61 A 62 A 66 B 61 B 62 B 66 B 11 B 12 B 16 D 11 D 12 D 16 B 21 B 22 B 26 D 21 D 22 D 26 B 61 B 62 B 66 D 61 D 62 D 66 ϵ 1 ϵ 2 ϵ 6 κ 1 κ 2 κ 6
Aij＝∫Qijdz 
Bij＝∫Qijzdz 
Dij＝∫Qijz2dz    (5) 
基板的应变和曲率可以通过下面的表达式来获得。 
ϵ κ = [ ABD ] - 1 N M - - - ( 6 )
从以上计算中获得的应力估计如下。 
机械应力 
Figure BSA00000244355300082
总应变 
Figure BSA00000244355300083
应力σ＝Q11εx
(7) 
图10是以曲线图表示的应力估计。即，图10示出了假设电子器件具有100μm的固定厚度时基板的顶侧和底侧上的应力随着绝缘层的厚度的变化。 
图11示出了电子器件的厚度对基于翘曲计算得到的绝缘层的厚度的依赖性。换而言之，图11示出了在电子器件具有50μm和100μm的固定厚度时基板的翘曲随着绝缘层的厚度的变化。 
在图11中，假设绝缘层的厚度为50μm，此时具有50μm厚度的IC具有0.26mm的翘曲，当将IC的厚度加倍至100μm时，翘曲减少至1/3为0.09mm。据此，可以推断，与绝缘层的厚度相比，基板的翘曲更依赖于电子器件的厚度。因此，可以预期的是，在几何不对称的印刷电路板中，随着电子器件变得更薄，基板的厚度的减小将使翘曲增加至难以承受的水平。 
为了解决该问题，需要通过将电子元件调整为关于基板的绝缘层设置在中心而使电子器件几何对称，来将翘曲最小化。在本实施方式中，通过向电子器件埋入式印刷电路板提供几何对称性，来实现在重复热应力下将翘曲最小化的超薄、高可靠性的电子器件埋入式印刷电路板。 
图12是根据本发明实施方式的电子器件埋入式印刷电路板100的截面图。如图12所示，根据本实施方式的电子器件埋入式印刷电路板100包括：芯板110，其中形成有空腔116；电子器件120，以面朝上的方式埋入在空腔116中并具有形成于其表面上的电极122；第一绝缘层130a，堆叠在芯板110的上表面上；以及第二绝缘层130b，堆叠在芯板110的下表面上并具有与第一绝缘层130a相同的厚度。这里，包括电极122的厚度的电子器件的厚度(由“b”表示)与芯板110的厚度相同。 
这里，术语“相同”并不一定指数学上数值精确相同的厚度，而是指其中考虑了设计误差、制造误差和测量误差的基本相同的厚度。下文中，本说明书中所使用的“相同”的意思指的是上述的基本相同。 
根据本实施方式的电子器件埋入式印刷电路板100通过将埋入的电子器件120设计和制造成对称结构，来将基板的翘曲最小化。此外，通过将包括电极122的厚度的电子器件的厚度(“b”)设计为与芯板110的厚度相同，可以提供芯板110本身的对称性，并因此可以将电子器件120埋入其中的芯板110本身的翘曲最小化。换言之，在实现芯板110的垂直对称时，还考虑形成在电子器件120的表面上的电极122的厚度，从而将芯板110本身的对称最佳化。当印刷电路板和埋入在印刷电路板中的电子器件120变得更薄时，这种对称结构用于降低翘曲增大的风险。 
此外，通过以面朝上的方式装配埋入在芯板110中的电子器件，可以更好地匹配电路。在实际印刷电路板中，上表面和下表面失配(off-match)约20μm至50μm，但如在本实施方式的情况下，可以通过使用面朝上的方式埋入电子器件120并将电极122朝上设置来改善电子器件的电极与电路板上的电路之间的匹配。 
在内部电路114a、114b形成在芯板110的表面上的情况下，可以将包括电极厚度的电子器件120的厚度(“b”)设计为与包括内层114a、114b厚度的芯板110的厚度(“a”)相同。 
优选的是，电子器件120的任一端上的纵向侧与空腔116的内壁之间的距离和至少为60μm。由于通过使用冲孔机或激光来加工空腔116，并且在切割加工期间可能会切到电子器件120，所以该距离是以每个粗糙界面的外图廓线为基础的。 
尽管电子器件120与内壁之间的距离被设计为最小30μm，但由于设备偏差电子器件120在一侧与内壁相接触是可能的。因此，优选的是，“c”和“d”的范围均在0μm到60μm之间，并且“c”和“d”的和至少为60μm。 
当一侧被设计为小于50μm时，可以观察到，电子器件120不恰当地***空腔116中，仅放置在空腔116的一侧。此外，根据仿真和真实数据，翘曲随着空腔116变大而减小。然而，如果空腔116变得太薄，则难以保证用于电路的空间，因此“c+d”的最大值为160μm以下是优选的。 
至此，已描述了根据本发明实施方式的电子器件埋入式印刷电路板的结构。下文中，将参考图13至图19来描述制造该电子器件埋入式印刷电路板的方法。由于根据本实施方式的电子器件埋入式印刷电路板的结构与以上描述的结构相同，所以将不再描述结构特征，而主要描述制造过程。 
首先，制备芯板110(参见图13)。可以在芯板110的表面上形成内部电路114a、114b，在这种情况下，芯板的上表面和下表面通过通孔112而彼此相连接。 
接下来，在芯板110中穿孔形成空腔116(参见图14)。空腔116是随后埋入电子器件120的位置，并且可以通过考虑所埋入的电子器件的尺寸和形状来以合适的尺寸和形状加工空腔。机械钻孔机或激光钻孔机可以用于在芯板110中加工空腔116。 
然后，将粘合层140粘附至芯板110的下表面(参见图15)。通过在其中穿透有空腔116的芯板的下表面粘附粘合层140，空腔的下侧被粘合层140密封。 
接下来，以面朝上的方式将电子器件120粘附至通过空腔116暴露的粘合层140的表面(参见图16)，然后通过在芯板110的上表面上堆叠第一绝缘层130a，来覆盖电子器件120(参见图17)。堆叠在芯板110的上表面上的第一绝缘层130a还填充其中埋入有电子器件120的空腔116的内部。 
然后，去除粘附至芯板110的下表面的粘合层140，并且在芯板110的下表面上堆叠第二绝缘层130b(参见图18)。 
此后，在第一绝缘层130a和第二绝缘层130b上形成电路图案132a、132b和通孔134a、134b(参见图19)。 
至此，已描述了本发明的一些实施方式。然而，本发明所属领域中的普通技术人员应当理解，在不背离以下所附权利要求中公开的本发明的技术构思和范围的前提下，可以存在本发明的各种变换和修改。 
在本发明的权利要求范围内存在除上述实施方式之外的多个实施方式。 

Claims (7)

1.一种加工芯板的空腔的方法，包括：
在芯板的一个表面上形成第一加工区域，所述第一加工区域以所述芯板的一个表面上的电路图案为界；
在所述芯板的另一表面上形成第二加工区域，所述第二加工区域以所述芯板的另一个表面上的电路图案为界；以及
通过将整个所述第一加工区域从所述芯板的所述一个表面上去除来加工空腔。
2.根据权利要求1所述的方法，其中，所述第二加工区域比所述第一加工区域宽。
3.根据权利要求2所述的方法，其中，将所述第一加工区域的中心和所述第二加工区域的中心设置在同一垂直线上。
4.根据权利要求3所述的方法，其中，所述第一加工区域和所述第二加工区域具有相似的形状。
5.一种电子器件埋入式印刷电路板，包括：
芯板；
形成在所述芯板的一个表面上的第一内部电路；
形成在所述芯板的另一表面上的第二内部电路；
贯通所述芯板的空腔，所述空腔的形状以所述第一内部电路为界；
电子器件，以面朝上的方式埋入在所述空腔中，在所述电子器件的表面上形成有电极； 
第一绝缘层，堆叠在所述芯板的形成有所述第一内部电路的所述一个表面上，以及
第二绝缘层，堆叠在所述芯板的形成有所述第二内部电路的所述另一表面上，所述第二绝缘层具有与所述第一绝缘层相同的厚度，
其中，所述第二内部电路与所述空腔的内壁分离。
6.根据权利要求5所述的电子器件埋入式印刷电路板，其中：
包括所述电极的厚度的所述电子器件的厚度与包括所述第一内部电路和所述第二内部电路的厚度的所述芯板的厚度相同。
7.根据权利要求5所述的电子器件埋入式印刷电路板，其中，从所述电子器件的任一纵向侧到所述空腔的所述内壁的距离和为60μm以上160μm以下。 
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