CN101997745A - FPGA-based E1 insertion time slot and E1_IP data aggregation hybrid access device and method - Google Patents
FPGA-based E1 insertion time slot and E1_IP data aggregation hybrid access device and method Download PDFInfo
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Abstract
The invention discloses a field programmable gate array (FPGA)-based E1 insertion time slot and E1_IP data aggregation hybrid access device and an FPGA-based E1 insertion time slot and E1_IP data aggregation hybrid access method. An FPGA-based integrated hardware platform system and a framing E1 time slot distribution strategy are provided to ensure that a central terminal is compatible with an E1 insertion time slot scheme and an IP access scheme of E1 so as to allow the device to mix for networking. The device consists of an embedded processing module which takes an FPGA as a core, and plug-in synchronous dynamic random access memory (SDRAM) and FLASH memory chips, and performs simple data processing and protocol conversion by taking a first path of Ethernet and a second path of E1 application interface as outputs and taking the accessed central terminal as a network bridge between an E1 looped network and the Ethernet. Due to the high integration level of the FPGA, equipment capacity is improved and equipment volume is reduced so as to realize low cost of the scheme. The FPGA-based E1 insertion time slot and E1_IP data aggregation hybrid access device and the FPGA-based E1 insertion time slot and E1_IP data aggregation hybrid access method of the invention are widely used in the technical field of communication.
Description
Technical field
The present invention relates to the dynamic environment monitoring system and the communication means of communication technique field, particularly a kind of E1 based on FPGA inserts time slot and E1_IP convergence mixing access device and method.
Background technology
Along with the progressively expansion of modern communication networks, communication equipment constantly increases.The rapid dilatation of communication size, to Room Power environmental unit and main frame and network system carry out the automation real time monitoring and effectively management be very important.For helping the long-term stability operation of communication network, the dispersing maintenance of must step-down imitating is centralized maintenance efficiently, realizes the unified maintenance of the whole network and the unattended operation of telecommunications room.In dynamic environment monitoring system, the E1 that is based on commonly used inserts time slot and inserts two kinds of common scheme based on the IP of E1.
In traditional scheme based on slotting time slot, the data multiplex that remote monitoring equipment collects serial ports inserts in the time slot of E1, center-side equipment is demultiplexed into serial ports with data from this time slot, the equipment by serial server and so on is converted to the Ethernet data bag with data again.Local area network (LAN) by the center is linked into the monitoring business system platform.
In the IP access scheme based on E1, remote monitoring equipment directly is converted to the Ethernet data bag with the data that serial ports collects, and passes through a plurality of slot transmission of E1 again to center-side.Center-side equipment takes out the data in the corresponding time slot of E1, sends to local area network (LAN) after changing according to Ethernet protocol (IEEE 802.3), and is linked into the monitoring business system platform.Ethernet to the E1 transducer that inserts center-side is that the frame format that direct packet with Ethernet is transformed into E1 is transmitted, at remote equipment the frame format of E1 is reduced into the frame format of Ethernet then, realize inserting center-side to the Ethernet of far-end based on the transparent transmission on the E1 telecommunications network.
Two schemes are compared, and based on the IP access scheme of E1 many advantages are arranged: IP time slot Bandwidth Dynamic is shared, and can satisfy the quantity that surpasses 31 websites; Standard ICP/IP protocol package, system compatibility is better; Can directly insert IP network, need not change base station equipment, save customer investment; 2M Loop Protection mechanism, failover recovers self-healing; Driffractive ring, and the ring need not be provided with, easy to maintenance, simple to operate.Along with its advantage is more and more outstanding; the market demand is drawn close to it gradually, also is substituted based on the scheme of inserting time slot thereupon, considers that the remote equipment quantity based on inserting time slot of present existence is huge; be the up-front investment of protection operator, new access center-side needs compatible these two kinds of schemes.
Summary of the invention
In order to solve above-mentioned technical problem, the purpose of this invention is to provide a kind of E1 and insert time slot and E1_IP convergence mixing access device based on FPGA.This device utilizes the FPGA embedded technology, and the SOC hardware platform system of a high integration is provided, and makes this center-side hardware compatibility E1 insert the IP access scheme of time slot scheme and E1.
Another object of the present invention provides a kind of E1 based on FPGA and inserts time slot and E1_IP convergence hybrid access method.This method is the embedded processing module of core and plug-in SDRAM and FLASH storage chip with FPGA, and with 1 road Ethernet and output of 2 road E1 application interfaces and hardware core, insert center-side as the bridge between E1 looped network and Ethernet, do data processing and protocol conversion.
The technical solution adopted for the present invention to solve the technical problems is:
E1 based on FPGA inserts time slot and E1_IP convergence mixing access device, comprise fpga chip, described fpga chip is connected with to be used to connect the slotting time slot convergence of E1 and to be used to be connected the E1_IP convergence and mixes the E1 interface circuit that inserts, and described fpga chip also is connected with SDRAM chip, FLASH chip and Ethernet PHY chip respectively.
Be further used as preferred embodiment, described fpga chip comprises following functional module:
Cpu system comprises soft nucleus CPU, sdram controller, FLASH controller, its minimum system for independently carrying out;
MAC Ethernet media module, its access controller by the MII interface, is done the data access controller of Ethernet PHY chip;
The E1 framing is separated frame module, the data after multiplexing is made the E1 framing handle, and insert the E1 physical circuit with the HDB3 coding;
The HDLC module, the webmaster order will be transmitted in the E1 circuit with the HDLC frame data format;
10 road Uart modules are resolved the serial data that the time slot end is uploaded, 10 tunnel corresponding 10 passages;
The Ethernet layer 2 switching module, with terminal inside IP FPDP, Ethernet interface and the cpu system interface of communicate by letter of IP between, the IP data are done the processing of data route;
MUX timeslot multiplex module is the service channel distribution time slot of serial data, IP data and HDLC network management data, thereby multiplexing on the E1 link;
HDLC module, Uart module and Ethernet layer 2 switching module are directly visited by cpu system, and it is carried out read-write operation; Simultaneously, they link to each other with two-way MUX Multiplexing module with serial data form respectively, can select wherein one the tunnel, and Data-carrying is separated on the time slot passage of frame module in selected E1 framing.
E1 based on FPGA inserts time slot and E1_IP convergence hybrid access method, E1 is defined as framing E1 type, and carries out time slot dividing, and a part of time slot allocation is given the end-equipment of inserting time slot; Another part time slot allocation is to the end-equipment of IPization; Also need fix a time slot and be used for network management path.
Be further used as preferred embodiment, described time slot end-equipment data processing may further comprise the steps:
X1, time slot end are uploaded serial data at E1 time slot passage;
X2, center-side E1 module receive the E1 track data, separate frame;
Serial data in X3, the MUX module demultiplexing time slot passage is to Uart1～10 modules;
X4, Uart module reduction serial data are also used the FIFO buffer memory;
X5, cpu system read FIFO serial data are buffered among the SDRAM;
X6, serial data read and seal the IP bag and be given to ethernet switching module from internal memory;
X7, IP bag is routed to ethernet port;
X8, be uploaded to the communication server of central machine room.
Be further used as preferred embodiment, described IP end-equipment data processing may further comprise the steps:
Y1, IP end seal the IP bag with monitor data, and upload data in the IP tunnels of E1;
Y2, center-side E1 module receive the E1 track data, separate frame;
IP data in Y3, the MUX module demultiplexing IP tunnel are to ethernet switching module;
Y4, ethernet switching module reduction IP data also route to ethernet port;
Y5, be uploaded to the communication server of central machine room.
Be further used as preferred embodiment, described equipment webmaster handling process may further comprise the steps:
The communication server of A, central machine room is initiated the webmaster operation;
B, webmaster instruction IP bag enter the center-side ethernet port;
C, ethernet switching module route are handled;
D, to center-side? be execution in step E then, otherwise execution in step M;
E, cpu system receive and resolve command;
F, network management center's end? be execution in step G then, otherwise execution in step H;
G, center-side system parameter setting finish;
H, issue webmaster order, execution in step L by the HDLC network management path;
L, time slot end system parameter are provided with, and finish;
M, IP bag is forwarded to IP tunnel and issues webmaster order, execution in step N;
N, IP end system parameter are provided with, and finish.
The invention has the beneficial effects as follows: apparatus of the present invention are compatible for realizing, integratedly on a slice fpga chip insert the center-side of time slot scheme and based on the center-side of the IP access scheme of E1 based on E1.Soon data multiplex intersection equipment, serial server and Ethernet are assisted to change to block to E1 and are integrated in one, and realization principle slave plate level replication has arrived chip-scale, and original system configuration all realizes in FPGA and builds with the form of realization function with functional module.
Another beneficial effect of the present invention is: the inventive method can compatiblely insert two kinds of terminal watch-dogs; Utilize the high integration of FPGA, improve place capacity and reduce equipment volume; Reduce cost, this method can realize effectively that E1 inserts the mixing access and the equipment network management function of time slot convergence, E1_IP convergence.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples.
Fig. 1 is the hardware configuration block diagram of Access Network center-side of the present invention;
Fig. 2 is the inner implementation structure block diagram of FPGA of the present invention;
Fig. 3 is the terminal flow chart of data processing figure of time slot of the present invention;
Fig. 4 is the terminal flow chart of data processing figure of IP of the present invention;
Fig. 5 is a present device webmaster process chart.
Embodiment
Insert the center-side of time slot scheme is made up of two parts based on E1: data multiplex intersection equipment and serial server.Data multiplex intersection equipment is responsible for inserting and timeslot multiplex with E1, and serial server is responsible for access network based on ethernet.Data from E1 are by taking out time slot method, and data multiplex intersection equipment at first extracts serial data, delivers to serial server, and serial server is packed it then, gives the communication server of central machine room with the IP data upload.
Center-side based on the IP access scheme of E1 is a protocol converter, inserts E1 and Ethernet respectively.The IP end with monitor data with the IP packet reach center-side in form, center-side is routed directly to the communication server of central machine room with the IP reduction of data on the E1 circuit then.
Consider from compatible angle, E1 be defined as framing E1 type, and carry out time slot dividing that a part of time slot allocation is given the end-equipment of inserting time slot; Another part time slot allocation is to the end-equipment of IPization; Also need fix a time slot and be used for network management path.
In the FPGA design, with the hardware system structure of above-mentioned two kinds of schemes with realize function, all in FPGA, realize and build with the form of module.
Should use center-side on a slice FPGA, to realize with the dynamic environment monitoring Access Network, integrated insert the center-side of time slot scheme and based on the center-side of the IP scenario of E1 based on E1, not only realized the compatibility of two kinds of schemes, equipment, serial server and Ethernet to the E1 association commentaries on classics card that also data multiplex intersected simultaneously is integrated in one, and has saved equipment cost greatly and has safeguarded operation cost.
With reference to Fig. 1, E1 based on FPGA inserts time slot and E1_IP convergence mixing access device, comprise fpga chip 1, described fpga chip 1 is connected with to be used to connect the slotting time slot convergence of E1 and to be used to be connected the E1_IP convergence and mixes the E1 interface circuit 2 that inserts, and described fpga chip 1 also is connected with SDRAM chip 4, FLASH chip 5 and Ethernet PHY chip 6 respectively.
With further reference to Fig. 2, as preferred embodiment, described fpga chip 1 comprises following functional module:
Cpu system 7 comprises soft nucleus CPU, sdram controller, FLASH controller, its minimum system for independently carrying out;
MAC Ethernet media module 8, its access controller by the MII interface, is done the data access controller of Ethernet PHY chip;
The E1 framing is separated frame module 9, the data after multiplexing is made the E1 framing handle, and insert the E1 physical circuit with the HDB3 coding;
HDLC module 10, the webmaster order will be transmitted in the E1 circuit with the HDLC frame data format;
10 road Uart modules 11 are resolved the serial data that the time slot end is uploaded, 10 tunnel corresponding 10 passages;
MUX timeslot multiplex module 13 is the service channel distribution time slot of serial data, IP data and HDLC network management data, thereby multiplexing on the E1 link;
HDLC module 10, Uart module 11 and Ethernet layer 2 switching module 12 are directly visited by cpu system 7, and it is carried out read-write operation; Simultaneously, they link to each other with two-way MUX Multiplexing module 13 with serial data form respectively, can select wherein one the tunnel, and Data-carrying is separated on the time slot passage of frame module 9 in selected E1 framing.
E1 based on FPGA inserts time slot and E1_IP convergence hybrid access method, E1 is defined as framing E1 type, and carries out time slot dividing, and a part of time slot allocation is given the end-equipment of inserting time slot; Another part time slot allocation is to the end-equipment of IPization; Also need fix a time slot and be used for network management path.
With further reference to Fig. 3, as preferred embodiment, described time slot end-equipment data processing may further comprise the steps:
X1, time slot end are uploaded serial data at E1 time slot passage;
X2, center-side E1 module receive the E1 track data, separate frame;
Serial data in X3, the MUX module demultiplexing time slot passage is to Uart1～10 modules;
X4, Uart module reduction serial data are also used the FIFO buffer memory;
X5, cpu system read FIFO serial data are buffered among the SDRAM;
X6, serial data read and seal the IP bag and be given to ethernet switching module from internal memory;
X7, IP bag is routed to ethernet port;
X8, be uploaded to the communication server of central machine room.
With further reference to Fig. 4, as preferred embodiment, described IP end-equipment data processing may further comprise the steps:
Y1, IP end seal the IP bag with monitor data, and upload data in the IP tunnels of E1;
Y2, center-side E1 module receive the E1 track data, separate frame;
IP data in Y3, the MUX module demultiplexing IP tunnel are to ethernet switching module;
Y4, ethernet switching module reduction IP data also route to ethernet port;
Y5, be uploaded to the communication server of central machine room.
With further reference to Fig. 5, as preferred embodiment, described equipment webmaster handling process may further comprise the steps:
The communication server of A, central machine room is initiated the webmaster operation;
B, webmaster instruction IP bag enter the center-side ethernet port;
C, ethernet switching module route are handled;
D, to center-side? be execution in step E then, otherwise execution in step M;
E, cpu system receive and resolve command;
F, network management center's end? be execution in step G then, otherwise execution in step H;
G, center-side system parameter setting finish;
H, issue webmaster order, execution in step L by the HDLC network management path;
L, time slot end system parameter are provided with, and finish;
M, IP bag is forwarded to IP tunnel and issues webmaster order, execution in step N;
N, IP end system parameter are provided with, and finish.
1, hardware configuration
The hardware configuration that inserts center-side mainly is to be the embedded processing module of core with FPGA, and plug-in SDRAM and FLASH storage chip formation, and with 1 road Ethernet and the output of 2 road E1 application interfaces.
For realizing this system, select the cycloneIII family chip 3C25 of ALTERA company, proper present resource requirement.
2, overall plan planning
The IP access scheme that compatible E1 inserts time slot scheme and E1 is the problem that the present invention mainly solves, and realizes that time slot end and IP end can both insert based on 2M (E1) dynamic environment monitoring looped network.
As previously mentioned, the time slot of framing E1 is cut apart, can be established the time slot end and take 10 time slots, the IP end takies 20 time slots, and webmaster HDLC passage takies 1 time slot.Inserting center-side, include 10 Uart serial port module, corresponding 10 paths allow the terminal access of 10 time slots (general 1 paths distributes 1 time slot) respectively; The IP bandwidth of 20 time slots is shared because of Bandwidth Dynamic, can insert to surpass 20 IP end.
Insert the last behavior Ethernet of center-side, following behavior two independent framing E1 supports into the ring networking.
3, FPGA integrated form hardware platform system
Divide by time slot, several data can be transmitted on 1 E1 link, does not disturb mutually.The Uart serial port module inserts the MUX module, and in the E1 time slot of setting, the serial data that the receiving slot end is uploaded is realized the access of time slot end to serial data with multiplexing, and 10 Uart serial port module allow 10 time slots ends to insert; The Ethernet layer 2 switching module inserts the MUX module, and the IP data in the E1 time slot of setting, receive the IP data that the IP end is uploaded with multiplexing, realize the access of IP end, and this IP time slot Bandwidth Dynamic is shared, and the terminal access amount of IP can surpass the quantity of IP time slot; The HDLC module inserts the MUX module, and network management data will be multiplexing in the E1 time slot of setting, and sends webmaster order any one node device to the link, the webmaster of realization end-equipment.
The Ethernet layer 2 switching module is the data link layer that is in OSI network protocol stack seven layer model, makes route according to the destination address of IP packet and handles, and selects the route path, has conventional layer 2-switched MAC address learning, searches and aging function.This module has 4 data ports: the IP FPDP ETH_MAC of the IP FPDP ETH_E1 (1) of E11 link, the IP FPDP ETH_E1 (2) of E1_2 link, Ethernet, the IP FPDP ETH_CPU of cpu system.This module not only helps the IP end and uploads data, also helps the terminal webmaster of IP.The IP data that the IP end comes up directly from ETH_E1 port routing forwarding to the ETH_MAC port, be uploaded to the communication server of central machine room, this process and cpu system are irrelevant, can not reduce the handling property of cpu system; Center-side can be passed through the ETH_CPU port, receives and respond the webmaster order of the IP end or the central machine room communication server.
4, system works detailed annotation
The monitor data of time slot end is carried to center-side in E1 time slot passage with the serial data form; The E1 of center-side separates frame module the E1 circuit is separated frame, and the serial data in the MUX module demultiplexing time slot passage is to corresponding serial port module, and serial port module is reduced into monitor data with it again, and buffering is got up in FIFO; CPU with the data read in the serial ports FIFO, sends into buffer memory in the internal memory with polling mode work; After CPU is polled to serial data IPization process, this road serial data is read, seals the IP bag and is given to ethernet switching module from internal memory; Ethernet switching module is made route to these IP data and is handled, and is forwarded to ethernet port, thereby is uploaded to the communication server of central machine room, finishes the convergence and the forwarding of time slot end are handled, as Fig. 3.
The monitor data of IP end is carried to center-side in the E1 passage with the form of IP packet; The E1 of center-side separates frame module the E1 circuit is carried out after E1 separates frame, and the data in the MUX module demultiplexing IP time slot passage are to ethernet switching module; Ethernet switching module is reduced into the IP data with it, and these IP data is made route handle, and directly is forwarded to ethernet port, is uploaded to the communication server of central machine room, finishes the data forwarding of IP end is handled, as Fig. 4.
When the end-equipment on the dynamic environment monitoring looped network was carried out webmaster, the communication server of central machine room was at first initiated the webmaster order, and webmaster instruction IP bag enters the center-side ethernet port.Ethernet switching module is made route to this IP bag and is handled, if the destination is the IP end, then the IP bag is forwarded to IP time slot passage and issues the webmaster order; Otherwise cpu system receives and resolves.If webmaster time slot end, cpu system issues the webmaster order by the HDLC network management path.The webmaster order can be arrived at any one node device by the E1 circuit, finishes the terminal and telemanagement of IP end on looped network of time slot, as Fig. 5.
More than be that preferable enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of spirit of the present invention, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.
Claims (6)
1. the E1 based on FPGA inserts time slot and E1_IP convergence mixing access device, it is characterized in that: comprise fpga chip (1), described fpga chip (1) is connected with to be used to connect the slotting time slot convergence of E1 and to be used to be connected the E1_IP convergence and mixes the E1 interface circuit (2) that inserts, and described fpga chip (1) also is connected with SDRAM chip (4), FLASH chip (5) and Ethernet PHY chip (6) respectively.
2. the E1 based on FPGA according to claim 1 inserts time slot and E1_IP convergence mixing access device, and it is characterized in that: described fpga chip (1) comprises following functional module:
Cpu system (7) comprises soft nucleus CPU, sdram controller, FLASH controller, its minimum system for independently carrying out;
MAC Ethernet media module (8), its access controller by the MII interface, is done the data access controller of Ethernet PHY chip;
The E1 framing is separated frame module (9), the data after multiplexing is made the E1 framing handle, and insert the E1 physical circuit with the HDB3 coding;
HDLC module (10), the webmaster order will be transmitted in the E1 circuit with the HDLC frame data format;
10 road Uart modules (11) are resolved the serial data that the time slot end is uploaded, 10 tunnel corresponding 10 passages;
Ethernet layer 2 switching module (12), with terminal inside IP FPDP, Ethernet interface and the cpu system interface of communicate by letter of IP between, the IP data are done the processing of data route;
MUX timeslot multiplex module (13) is the service channel distribution time slot of serial data, IP data and HDLC network management data, thereby multiplexing on the E1 link;
HDLC module (10), Uart module (11) and Ethernet layer 2 switching module (12) are directly visited by cpu system (7), and it is carried out read-write operation; Simultaneously, they link to each other with two-way MUX Multiplexing module (13) with serial data form respectively, can select wherein one the tunnel, and Data-carrying is separated on the time slot passage of frame module (9) in selected E1 framing.
3. the E1 based on FPGA inserts time slot and E1_IP convergence hybrid access method, it is characterized in that: E1 is defined as framing E1 type, and carries out time slot dividing, a part of time slot allocation is given the end-equipment of inserting time slot; Another part time slot allocation is to the end-equipment of IPization; Also need fix a time slot and be used for network management path.
4. the E1 based on FPGA according to claim 3 inserts time slot and E1_IP convergence hybrid access method, and it is characterized in that: described time slot end-equipment data processing may further comprise the steps:
X1, time slot end are uploaded serial data at E1 time slot passage;
X2, center-side E1 module receive the E1 track data, separate frame;
Serial data in X3, the MUX module demultiplexing time slot passage is to Uart1～10 modules;
X4, Uart module reduction serial data are also used the FIFO buffer memory;
X5, cpu system read FIFO serial data are buffered among the SDRAM;
X6, serial data read and seal the IP bag and be given to ethernet switching module from internal memory;
X7, IP bag is routed to ethernet port;
X8, be uploaded to the communication server of central machine room.
5. the E1 based on FPGA according to claim 3 inserts time slot and E1_IP convergence hybrid access method, and it is characterized in that: described IP end-equipment data processing may further comprise the steps:
Y1, IP end seal the IP bag with monitor data, and upload data in the IP tunnels of E1;
Y2, center-side E1 module receive the E1 track data, separate frame;
IP data in Y3, the MUX module demultiplexing IP tunnel are to ethernet switching module;
Y4, ethernet switching module reduction IP data also route to ethernet port;
Y5, be uploaded to the communication server of central machine room.
6. the E1 based on FPGA according to claim 3 inserts time slot and E1_IP convergence hybrid access method, and it is characterized in that: described equipment webmaster handling process may further comprise the steps:
The communication server of A, central machine room is initiated the webmaster operation;
B, webmaster instruction IP bag enter the center-side ethernet port;
C, ethernet switching module route are handled;
D, to center-side? be execution in step E then, otherwise execution in step M;
E, cpu system receive and resolve command;
F, network management center's end? be execution in step G then, otherwise execution in step H;
G, center-side system parameter setting finish;
H, issue webmaster order, execution in step L by the HDLC network management path;
L, time slot end system parameter are provided with, and finish;
M, IP bag is forwarded to IP tunnel and issues webmaster order, execution in step N;
N, IP end system parameter are provided with, and finish.
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| CN101707544A (en) * | 2009-11-20 | 2010-05-12 | 中国人民解放军第二炮兵装备研究院第四研究所 | E1 channel multidirectional network bridge transmission device and method |
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| CN112565028A (en) * | 2020-11-16 | 2021-03-26 | 国网浙江宁波市鄞州区供电有限公司 | Multi-point to multi-point multi-service access system based on IP transmission network |
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| CN113949718A (en) * | 2021-10-13 | 2022-01-18 | 国网福建省电力有限公司 | E1 and IP hybrid bearing-based power private network dispatching and number allocation system and method |
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