CN101989400B - Frame rate-scalable image processing system and method - Google Patents
Frame rate-scalable image processing system and method Download PDFInfo
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- CN101989400B CN101989400B CN 200910160262 CN200910160262A CN101989400B CN 101989400 B CN101989400 B CN 101989400B CN 200910160262 CN200910160262 CN 200910160262 CN 200910160262 A CN200910160262 A CN 200910160262A CN 101989400 B CN101989400 B CN 101989400B
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Abstract
The invention provides fame rate-scalable image processing system and method. A master image processor processes part of image data and transmits the processed part of image data to a time schedule controller; in addition, at least one slave image processor processes the rest of image data and transmits the processed rest of image data to the time schedule controller, wherein the master image processor and the slave image processors respectively produce part of results, and the master image processor generates an integral adjustment value according to the part of results to provide the integral adjustment value to a display panel.
Description
Technical field
The present invention relates to image processor, particularly the image processing system of a kind of frame rate (frame rate) extendible (scalable).
Background technology
Along with the increase of the resolution of image display, image frame rate (frame rate) increases to per second 120 frames (that is 120Hz) or higher gradually from traditional per second 60 frames (that is 60Hz).Take the image display (for example televisor) of frame rate 120Hz as example, be responsible for processing and transferring data to the image processor (video processor) of display panel or the ability that time schedule controller (timingcontroller, TCON) must have processing and transmission 120Hz data volume.By processing two times data volume at this kind image processor (or time schedule controller) more traditional 60Hz image processor within the same time, so, the signal rate of image import and export end will increase to two times, inner circuit area also need increase in order to process two times data volume, and the size of chip package and number of pins thereof also will increase and increase.Therefore, when image frame rate increased, until the rear end processing procedure all must be designed again, equipment also may need to change integrated circuit, thereby causes the increase of cost, the also Time To Market of delay product from the front end processing procedure.
Given this, therefore need the image processing system framework that proposes a kind of novelty badly, make it have extendibility (scalability), can expand along with the increase of frame rate easily, even can support traditional frame rate.
Summary of the invention
In above-mentioned prior art, the traditional images disposal system only can be processed single frame rate, when frame rate increases, namely need redesign and make corresponding image processor; One of purpose of the embodiment of the invention namely is to propose the image processing system of a kind of frame rate extendible (scalable), in order to process and to transmit the view data of various frame rate, in order to image is shown on the display panel.
According to the embodiment of the invention, the picture image data of master control (master) image processor processing section also transfer to time schedule controller.In addition, at least one subordinate (slave) image processor is processed remaining part picture image data and is transferred to time schedule controller.Wherein, master control image processor and subordinate image processor be the generating portion result respectively, and the master control image processor namely according to these partial results to produce a whole adjusted value (for example brightness control signal or gamma adjust signal), to offer display panel.According to an embodiment, also comprise a setting value memory block, in order to store the related setting value of different frame rates.When detecting the frame rate change, master control image processor, subordinate image processor are namely downloaded the respective settings value from the setting value memory block.When frame rate diminished, at least one subordinate image processor can be closed; When frame rate became large, at least one subordinate image processor can be opened.
Description of drawings
Figure 1A shows the calcspar of the extendible image processing system of the embodiment of the invention.
Figure 1B shows the calcspar of the extendible image processing system of another embodiment of the present invention.
Fig. 2 shows that master control image processor and the coordination of subordinate image processor produce the sequential synoptic diagram of better adjusted value.
Fig. 3 shows the calcspar of the extendible image processing system of further embodiment of this invention.
[main element symbol description]
10 master control image processors
12 subordinate image processors
12A the first subordinate image processor
12B the second subordinate image processor
12C the 3rd subordinate image processor
14 time schedule controllers
16 display panels
18 setting value memory blocks
20 horizontal scanning periods
22 vertical-scan periods
100 (master control image processor) input bus
102 (master control image processor) output bus
104 (brightness control signal) wire
106 (gamma adjustment signal) wire
108 (manually brightness control signal) wire
120 (subordinate image processor) input bus
120A (the first subordinate image processor) input bus
120B (the second subordinate image processor) input bus
120C (the 3rd subordinate image processor) input bus
122 (subordinate image processor) output bus
122A (the first subordinate image processor) output bus
122B (the second subordinate image processor) output bus
122C (the 3rd subordinate image processor) output bus
140 (time schedule controller) output bus
220 vertical blanking periods
1012 master bus
1210 subordinate bus
1210A the first subordinate bus
1210B the second subordinate bus
1210C the 3rd subordinate bus
The PWM brightness control signal
The manual brightness control signal of PWM_I
The GM gamma is adjusted signal
Embodiment
Figure 1A shows the calcspar of extendible (scalable) image processing system of the embodiment of the invention.Although present embodiment with digital television as illustration, yet the embodiment of the invention is applicable to the display of other forms, size, resolution.Moreover although the image processing system of present embodiment has frame rate (frame rate) capable of extending function, yet the image processing system that also can be used as fixed frame rate uses.
In the present embodiment, image processing system mainly comprises master control (master) image processor (also can be described as analog image processor, analog video processor or AVP) 10 and subordinate (slave) image processor 12.The master control image processor 10 of present embodiment and subordinate image processor 12 respectively have processing and transmit the ability of 60Hz frame rate.Yet in other embodiments, the frame rate of master control image processor 10 and subordinate image processor 12 is not limited to 60Hz, and both frame rate are also not necessarily identical.
Continue to consult Figure 1A, transmit signal with master bus 1012 and subordinate bus 1210 between master control image processor 10 and the subordinate image processor 12.In the present embodiment, master bus 1012 is (120Hz) unidirectional serial (serial) communication port that master control image processor 10 is coupled to subordinate image processor 12, and it comprises the clock bit of two-sampling usefulness and the data bit of the transmission of data.In addition, subordinate bus 1210 is (120Hz) unidirectional serial communication passage that subordinate image processor 12 is coupled to master control image processor 10, and it also comprises the clock bit of two-sampling usefulness and the data bit of the transmission of data.In other embodiments, master bus 1012, subordinate bus 1210 are not defined as unidirectional, serial, and figure place is not defined as two, even two buses also can merge.
According to the image processing system framework of the 120Hz frame rate of present embodiment, master control image processor 10 and subordinate image processor 12 receive and process respectively the picture image data of half from input bus 100 and 120.After treatment, more respectively via output bus 102 and 122, send view data the time schedule controller (TCON) 14 of 120HZ to, and be shown in display panel 16.In the present embodiment, input bus 100/120 and output bus 102/122 use (but being not limited to) binary channels low-voltage differential signal (dual LVDS) transformat, and the output bus 140 of time schedule controller (TCON) 14 then can use (but being not limited to) small capacity double passage low-voltage differential signal (mini-LVDS) or reduction to swing differential signal (RSDS) transformat.
As previously mentioned, master control image processor 10 and subordinate image processor 12 are crossed output bus 102/122 with its handled half picture image data communication device and are sent respectively time schedule controller (TCON) 14 to.Yet for some controls, the adjustment of image, for example backlight illumination control or gamma (gamma) are adjusted, and must just can draw better adjusted value according to the view data of whole picture.Be control, the adjustment of considering this kind image, the picture image data that the master control image processor 10 of present embodiment and subordinate image processor 12 are received with oneself respectively calculate other partial results, and subordinate image processor 12 then sends its partial results to master control image processor 10 by subordinate bus 1210.Master control image processor 10 is namely coordinated, is integrated and draw better whole adjusted value according to oneself partial results and the partial results that provides of subordinate image processor 12.In addition, this integral body adjusted value also can transmit notice subordinate image processor 12 by master bus 1012.Then, master control image processor 10 can send display panel 16 to by the whole adjusted value that this is better.For example, transmit backlight illumination control signal PWM by wire 104, and transmit gamma by wire 106 and adjust signal GM.In the present embodiment, the control of backlight illumination can be the automatic control of doing according to image itself, also can be according to the manual brightness control signal PWM_I of wire 108 inputs.In addition, wire 106 also can transmit common electrode voltage (Vcom) in passing when transmitting gamma adjustment signal GM.Though present embodiment is adjusted into example with brilliance control, gamma, however present embodiment also applicable to other parameters of image, for example contrast adjustment of image.
Fig. 2 shows that master control image processor 10 and 12 coordinations of subordinate image processor produce the sequential synoptic diagram of better adjusted value.In 20 times, 12 half picture image data of not receiving with oneself of master control image processor 10 and subordinate image processor calculate other partial results at horizontal scanning period.During last vertical blanking (blanking) of vertical-scan period 22 220,12 of master control image processor 10 and subordinate image processors be carry out aforementioned coordination integration work-that is, subordinate image processor 12 sends its partial results to master control image processor 10, and master control image processor 10 is coordinated according to this, integrated and draws better whole adjusted value.In the present embodiment, because the data volume of the partial results of subordinate image processor 12 can be very not large, therefore can utilize vertical blanking period 220 fully to transmit and coordinate and integrate.The transmission frequency of master bus 1012 and subordinate bus 1210 can be adjusted according to the practical application situation.
Embodiment shown in Figure 1A is except can expand to the 120Hz frame rate, and is also changeable to support basic 60Hz frame rate.In the present embodiment, whether the input data of (when perhaps starting shooting each time) detection input bus 100 switch to basic 60Hz between 10 meetings in due course of master control image processor; Switch to new frame rate (for example 60Hz) if detect frame rate, then master control image processor 10, subordinate image processor 12 can be from setting value memory block 18, and (but the electronics program read-only memory of can erasing for example EEPROM) is downloaded new frame rate (for example 60Hz) related setting value (for example overdrive (overdrive) data form or sequential related setting); And subordinate image processor 12 can be closed (disable) voluntarily, and the image that allows image processing system carry out 60Hz is processed.Return back to 120Hz if detect again frame rate, subordinate image processor 12 again row starts (enable), master control image processor 10, subordinate image processor 12 can be downloaded frame rate 120Hz related setting value again from setting value memory block 18, and the image that allows image processing system carry out 120Hz is processed.
According to the framework of the embodiment of the invention, can use the image processor of single 60HZ frame rate to extend to the image processing system of 120Hz.By this, need not change processing procedure and the equipment of integrated circuit, thereby be saved cost.Moreover image processing system also can be supported basic 60Hz frame rate except can expand to 120Hz.
Figure 1B shows the calcspar of extendible (scalable) image processing system of another embodiment of the present invention, and the element identical with Figure 1A then continued to use identical component symbol.Different with Figure 1A framework is that the time schedule controller of present embodiment (TCON) 14 is made in respectively in master control image processor 10 and the subordinate image processor 12.In the present embodiment, output bus 102/122 uses (but being not limited to) small capacity double passage low-voltage differential signal (mini-LVDS) or reduction to swing differential signal (RSDS) transformat, in order to data are transmitted, are shown in display panel 16.
Fig. 3 shows the calcspar of extendible (scalable) image processing system of further embodiment of this invention, and the element identical with Figure 1A then continued to use identical component symbol.Except master control image processor 10, present embodiment uses three subordinate image processor-first subordinate image processor 12A, the second subordinate image processor 12B, the 3rd subordinate image processor 12C.Master control image processor 10 is coupled to the first/the second/the 3rd subordinate image processor 12A/12B/12C with (sharing) master bus 1012; The the first/the second/the 3rd subordinate image processor 12A/12B/12C then is coupled to respectively master control image processor 10 with (independence) the first/the second/the 3rd subordinate bus 1210A/1210B/1210C.
According to framework shown in Figure 3, master control image processor 10 and the first/the second/the 3rd subordinate image processor 12A/12B/12C receives and processes 1/4th picture image data from input bus 100 and 120A, 120B, 120C respectively.After treatment, respectively via output bus 102 and 122A, 122B, 122C, send view data the time schedule controller (TCON) 14 of 240HZ to, and be shown in display panel 16 again.Wherein, time schedule controller (TCON) 14 also can be made in respectively in master control image processor 10 and the first/the second/the 3rd subordinate image processor 12A/12B/12C.Then, the picture image data that master control image processor 10 and the first/the second/the 3rd subordinate image processor 12A/12B/12C receives with oneself respectively calculate other partial results, and the first/the second/the 3rd subordinate image processor 12A/12B/12C then sends respectively its partial results to master control image processor 10 by subordinate bus 1210A/1210B/1210C.Master control image processor 10 is namely coordinated, is integrated and draw better whole adjusted value according to the partial results that partial results and the first/the second/the 3rd subordinate image processor 12A/12B/12C provides of oneself.In addition, this integral body adjusted value also can transmit by master bus 1012 and notify the first/the second/the 3rd subordinate image processor 12A/12B/12C.Then, master control image processor 10 can send display panel 16 to by the whole adjusted value that this is better.
According to framework embodiment illustrated in fig. 3, can use the image processor of single 60HZ frame rate to extend to the image processing system of 240Hz.By this, need not change processing procedure and the equipment of integrated circuit, thereby be saved cost.Moreover image processing system also can be supported basic 60Hz frame rate (closing three subordinate image processors) or 120Hz frame rate (closing two subordinate image processors) except can expand to 240Hz.Moreover the present embodiment framework also can further extend to more than the 240Hz frame rate.
The above is the preferred embodiments of the present invention only, is not to limit claimed scope of the present invention; All other do not break away from the equivalence of finishing under the spirit that invention discloses and changes or modify, and all should be included in the claimed scope of claims.
Claims (28)
1. open-ended image processing system of frame rate comprises:
One master control image processor, the picture image data of its processing section also transfer to time schedule controller; And
At least one subordinate image processor, it is processed remaining part picture image data and transfers to this time schedule controller;
Wherein this master control image processor and this subordinate image processor generating portion result respectively, and this master control image processor producing a whole adjusted value, and offers a display panel according to these partial results.
2. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned time schedule controller is positioned at this master control image processor, this subordinate image processor is inner.
3. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned time schedule controller is positioned at this master control image processor, this subordinate image processor is outside.
4. the open-ended image processing system of frame rate as claimed in claim 1, wherein the frame rate of above-mentioned master control image processor and subordinate image processor is 60Hz.
5. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned whole adjusted value comprises brightness control signal.
6. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned whole adjusted value comprises gamma and adjusts signal.
7. the open-ended image processing system of frame rate as claimed in claim 1, also comprise a master bus, be coupled to this subordinate image processor by this master control image processor, be sent to this subordinate image processor in order to the whole adjusted value that this master control image processor is produced.
8. the open-ended image processing system of frame rate as claimed in claim 7, wherein above-mentioned master bus is unidirectional serial communication passage.
9. the open-ended image processing system of frame rate as claimed in claim 1 also comprises a subordinate bus, is coupled to this master control image processor by this subordinate image processor, is sent to this master control image processor in order to the partial results with this subordinate image processor.
10. the open-ended image processing system of frame rate as claimed in claim 9, wherein above-mentioned subordinate bus is unidirectional serial communication passage.
11. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned master control image processor produces this integral body adjusted value in vertical blanking period.
12. the open-ended image processing system of frame rate also comprises a setting value memory block as claimed in claim 1, in order to store the related setting value of different frame rates.
13. the open-ended image processing system of frame rate as claimed in claim 12, when above-mentioned master control image processor detects frame rate when change from input end, this master control image processor and this subordinate image processor are namely downloaded the respective settings value from this setting value memory block.
14. the open-ended image processing system of frame rate as claimed in claim 13, when frame rate diminished, at least one this subordinate image processor can be closed; When frame rate became large, at least one this subordinate image processor can be opened.
15. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned at least one subordinate image processor comprises a subordinate image processor altogether, and itself and this master control image processor are processed respectively half picture image data and transferred to respectively this time schedule controller.
16. the open-ended image processing system of frame rate as claimed in claim 1, wherein above-mentioned at least one subordinate image processor comprises three subordinate image processors altogether, and itself and this master control image processor are processed respectively 1/4th picture image data and transferred to respectively this time schedule controller.
17. the open-ended image processing method of frame rate comprises:
Carry out a master chart picture and process, with the picture image data of processing section, and produce a part of result;
Carry out a subordinate image and process, processing remaining part picture image data, and produce another part result; And
By carry out master control image processor that described master chart picture processes according to these partial results to produce a whole adjusted value, to offer a display panel.
18. the open-ended image processing method of frame rate as claimed in claim 17, the frame rate that wherein above-mentioned master chart picture is processed and the subordinate image is processed is 60Hz.
19. the open-ended image processing method of frame rate as claimed in claim 17, wherein above-mentioned whole adjusted value comprises brightness control signal.
20. the open-ended image processing method of frame rate as claimed in claim 17, wherein above-mentioned whole adjusted value comprises gamma and adjusts signal.
21. the open-ended image processing method of frame rate as claimed in claim 17, also comprising provides a master bus, carries out the subordinate image processor that described subordinate image is processed in order to should the integral body adjusted value to be sent to.
22. the open-ended image processing method of frame rate as claimed in claim 21, wherein above-mentioned master bus is unidirectional serial communication passage.
23. the open-ended image processing method of frame rate also comprises a subordinate bus as claimed in claim 17, in order to this another part result is sent to described master control image processor.
24. the open-ended image processing method of frame rate as claimed in claim 23, wherein above-mentioned subordinate bus is unidirectional serial communication passage.
25. the open-ended image processing method of frame rate as claimed in claim 17, wherein above-mentioned whole adjusted value produces in vertical blanking period.
26. the open-ended image processing method of frame rate also comprises according to these picture image data of inputting described master control image processor to detect frame rate as claimed in claim 17.
27. the open-ended image processing method of frame rate when detecting the frame rate change, also comprises and downloads the respective settings value as claimed in claim 26.
28. the open-ended image processing method of frame rate as claimed in claim 27, when frame rate diminished, then this subordinate image of closed portion was processed; When frame rate became large, then this subordinate image of opening section was processed.
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| CN 200910160262 CN101989400B (en) | 2009-07-31 | 2009-07-31 | Frame rate-scalable image processing system and method |
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| JP6432767B2 (en) * | 2014-09-22 | 2018-12-05 | カシオ計算機株式会社 | Electronic device, control method therefor, and control program |
| CN107680554B (en) * | 2017-11-22 | 2020-04-28 | 深圳市华星光电技术有限公司 | Display device driving system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1299197A (en) * | 1999-12-08 | 2001-06-13 | 日本电气株式会社 | radio communication equipoment and method for pre-testing frame rate in code multiplex communication system |
| EP1931141A1 (en) * | 2005-09-30 | 2008-06-11 | Sharp Kabushiki Kaisha | Image display device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1299197A (en) * | 1999-12-08 | 2001-06-13 | 日本电气株式会社 | radio communication equipoment and method for pre-testing frame rate in code multiplex communication system |
| EP1931141A1 (en) * | 2005-09-30 | 2008-06-11 | Sharp Kabushiki Kaisha | Image display device and method |
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Effective date of registration: 20221027 Address after: Taiwan Tainan new urban Chinese Fenghua in purple Melia Road No. 26 Patentee after: Himax Technologies, Inc. Address before: Tainan County, Taiwan, China Patentee before: Himax Media Solutions, Inc. |
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