CN101982881A - ESD protection integrated power MOSFET or IGBT and preparation method thereof - Google Patents
ESD protection integrated power MOSFET or IGBT and preparation method thereof Download PDFInfo
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- CN101982881A CN101982881A CN 201010502011 CN201010502011A CN101982881A CN 101982881 A CN101982881 A CN 101982881A CN 201010502011 CN201010502011 CN 201010502011 CN 201010502011 A CN201010502011 A CN 201010502011A CN 101982881 A CN101982881 A CN 101982881A
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Abstract
The invention improves the ESD protection integrated power MOSFET or IGBT. The invention is characterized in that the concentration of all P type areas in a poly-crystal diode set in an ESD protection unit is as same as the P type concentration of the power MOSFET or IGBT; the concentration of the N type area is as same as the N+ source of the power MOSFET or IGBT; the poly-crystal diode set is semi-circled around a grid bonding area between the grid bonding area and a structure cell area. If being a grid inserting structure, the middle of the semi-circled poly-crystal diode set is separated by the grid inserting structure so as to form left and right L-shaped parts which are disconnected, wherein all the P type areas and the N type areas in the poly-crystal diode are respectively formed by injecting and spreading the P well and N+ source of the power MOSFET or IGBT. The leakage between the grid and source electrodes of the acquired ESD protection integrated power MOSFET or IGBT is small. When preparing, a breakdown voltage between the grid and source electrodes is adjustable, the ESD discharging capability is high, the reliability is high and the manufacture is simple.
Description
Technical field
The present invention improves the power MOSFET of integrated esd protection or IGBT; it is little to be particularly related between a kind of grid and source electrode electric leakage; during preparation between grid, source electrode puncture voltage adjustable, ESD relieving capacity height, good reliability are made power MOSFET or the IGBT and the preparation method of simple integrated esd protection.
Background technology
Development along with power semiconductor; people have higher requirement to power MOSFET or IGBT performance; static (ESD) phenomenon for example usually appears in device package, transportation, assembling and use easily; it can produce a high electric field at their grid; make gate medium under high electric field, insulation breakdown take place; thereby make component failure, so static (ESD) defencive function is exactly important indicator wherein.Static (ESD) protection; it is meant when having the object or person body-contacted device of static; can eliminate the big voltage and the big electric current of generation of static electricity rapidly; reduce or avoid the device that the static discharge phenomenon caused and destroy, make device can bear the impact of the big voltage of generation of static electricity and big electric current and be not damaged.
In the prior art, for the voltage that power MOSFET or IGBT is avoided be higher than oxide breakdown value destroys, method commonly used is to insert the polycrystalline Zener diode at grid and source electrode, with MOSFET be example as shown in Figure 1, 2.The formation of Zener diode is by the ion injection of high concentration polysilicon to be mixed, thereby forms the Zener diode group of a series connection between grid and source electrode, realizes the ESD between grid and the source electrode is protected.Existing common power MOSFET, and for improving the power MOSFET that its cellular conducting homogeneity adopts the slotting finger of grid structure, its Zener diode group all is positioned at two sides of power MOSFET grid pressure welding area, to realize the esd protection in grid region, shown in Fig. 3,4.The power MOSFET or the IGBT of the integrated esd protection of this kind have the following disadvantages:
At first, polycrystalline Zener diode group 6 adopts high concentration impurities to form required PN junction, not only it forms needs extra reticle, complexity and cost that device is made have been increased, and make that the leakage current of grid and source electrode is bigger, the PN junction that this mode of while forms, after in case device is made required mask formulation, puncture voltage is that (puncture voltage of a Zener diode is generally at 5-6V for definite value just between grid and source electrode, total breakdown voltage value is the product of the puncture voltage and the diode series connection number of a Zener diode), can not be regulated by follow-up technological process, process technology limit is big; Secondly, ESD is a transient process, no matter for example be that common power MOSFET or grid are inserted the power MOSFET that refers to structure, is the sensitizing range (Fig. 3,4) that ESD takes place around their the grid pressure welding area 5, easily electrostatic damage takes place and device is wrecked; Zener diode group 6 layouts are arranged on the left and right sides of grid pressure welding area 5; though can play the esd protection effect; but owing to there is not Zener diode group 6 to separate (as the A district among Fig. 3 and the B district among Fig. 4) between gate metal 2 and the source metal 3; easily lost efficacy when under harsh conditions, being easy to generate stronger static; and this diode group layout set-up mode; do not make full use of grid pressure welding area 5 surrounding areas; make under grid pressure welding area area the same terms; the width of releasing of diode group is less, causes the ESD relieving capacity strong inadequately.
Chinese patent CN101517743 is used for the ramp voltage polysilicon diode electrostatic discharge circuit of power metal oxide semiconductor field-effect transistor and integrated circuit; by forming protecting network with polycrystalline diode and device; be used to form esd protection, to reduce leakage current between the grid source.But it adopts primary branch and the secondary branch structure that combines, and makes the circuit complexity; And the esd protection area occupied is bigger, increases manufacturing cost.
Above-mentioned deficiency still has is worth improved place.
Summary of the invention
The object of the invention is to overcome above-mentioned the deficiencies in the prior art; provide between a kind of grid, source electrode leakage current little; during preparation between grid, source puncture voltage adjustable, ESD relieving capacity height, good reliability, and make the power MOSFET or the IGBT of the integrated esd protection simple, that cost is low.
Another purpose of the present invention is to provide the preparation method of a kind of power MOSFET or IGBT of above-mentioned integrated esd protection.
The present invention's first purpose realizes that mainly improving one is by high concentration P with each P district in the polycrystalline diode group
+Become low concentration P
-The 2nd, with each N district in the diode group by high concentration N
+Become the N of power MOSFET or IGBT
+The source; The 3rd, with the grid pressure welding area left and right sides opposed polycrystalline Zener diode group, change between grid pressure welding area and cellular region semi-ring into around the setting of grid pressure welding area, if for grid are inserted the finger structure, semi-ring is inserted the finger structure around the centre by grid separate the disconnected left and right sides L type that forms, i.e. symmetry " L " type setting, thereby overcome above-mentioned the deficiencies in the prior art, realized the object of the invention.Specifically; the power MOSFET of the integrated esd protection of the present invention or IGBT; comprise the esd protection unit that is connected across between power MOSFET or IGBT grid, source electrode; it is characterized in that each p type island region concentration is identical with the P trap concentration of power MOSFET or IGBT in the polycrystalline diode group of esd protection unit, the N of each N type district's concentration and power MOSFET or IGBT
+The source is identical; Polycrystalline diode group semi-ring between grid pressure welding area and cellular region is provided with around the grid pressure welding area, refers to structures if insert for grid, with semi-ring around polycrystalline diode group in the middle of insert the finger structure by grid and separate, form disconnected left and right sides L type.
Before the detailed description, make a presentation by the basic function and the effect that can reach earlier, so that those skilled in the art have one clearly to understand to the art of this patent scheme invention.Below be example explanation with N type power MOSFET:
The present invention passes through each P district in the diode group by high concentration P
+Become identical (the low concentration P of P trap concentration with power MOSFET
-), make the leakage current of polysilicon diode group significantly reduce, thereby feasible grid source electrode electric leakage with power MOSFET of esd protection reduce; Simultaneously, each p type island region in the diode group is identical with the P trap concentration of power MOSFET, and each N district is by high concentration N
+Become the N of power MOSFET
+The source is identical, and making p type island region and N type district in the diode group all becomes P trap and N with power MOSFET
+The source is a same manufacturing layer, can not need additional process by finishing with ion injecting process, makes simplified manufacturing process, the cost reduction.And the power MOSFET with esd protection that forms in view of the above, after device was made required mask formulation, puncture voltage still can be regulated by follow-up technological process between its grid and source electrode, and flexibility is strong, and universality is better.Diode group layout employing semi-ring is around the setting of grid pressure welding area or be the setting of symmetry " L " type, makes full use of grid pressure welding area surrounding area, makes the width of releasing of diode group increase, thereby has promoted the ESD relieving capacity of power MOSFET.Adopt the formed polysilicon diode structure of the present invention, can be regarded as the NPN pipe cascaded structure of a plurality of bases open circuit, its NPN pipe is by as shown in phantom in Figure 8 N
+/ P
-/ N
+Form.The puncture voltage of base open circuit NPN pipe is relevant with base width, and along with reducing of base width, its puncture voltage reduces, and therefore can change P in the polysilicon diode by the adjustment of subsequent technique
-The width in district, thus reach the purpose that changes diode breakdown voltage.For example by increasing the N of power MOSFET
+The source advances the time, increases the N of power MOSFET
+The horizontal proliferation amount of source in polysilicon, thus P made
-Sector width reduces, and reaches the purpose that reduces puncture voltage.
More than said source electrode, be also referred to as emitter for IGBT.
Said among the present invention:
Each p type island region concentration is identical with the P trap concentration of power MOSFET or IGBT in the polycrystalline diode group, the N of each N type district's concentration and power MOSFET or IGBT
+Source concentration is identical, is meant to adopt with ion injecting process and diffuse to form, and it and non-exponential are learned fully accurately identical on the meaning, should comprise the permissible variation that causes owing to technical process.
Polycrystalline diode group two ends, a kind of two ends that are preferably are respectively N type or P type, help the consistency of the forward and reverse puncture voltage of polycrystalline diode group, and the technology manufacturing is simple.Wherein the P type at two ends is preferably P
-/ P
+, help reducing the leakage current of polycrystalline diode; Said P
-/ P
+Two kinds of structures can be arranged, and a kind of is left right model (Fig. 6), and a kind of is last mo(u)ld bottom half (Fig. 7).
In addition, for making the power MOSFET of integrated esd protection or the esd protection unit of IGBT have littler area, can adopt As (arsenic) to inject the N that forms power MOSFET or IGBT
+Each N district in source and the polysilicon diode group.As (arsenic) has bigger atomic radius, and the horizontal proliferation amount in polysilicon is less relatively, and each N sector width can reduce in the polysilicon diode group of formation, and the gross area of required polysilicon diode group reduces.
The power MOSFET of integrated esd protection of the present invention or the preparation method of IGBT; be included between the grid of MOSFET or IGBT and source electrode and inject by ion and diffuse to form polycrystalline diode group esd protection unit; it is characterized in that polycrystalline diode group between grid pressure welding area and cellular region semi-ring around the setting of grid pressure welding area; if for grid are inserted the finger structure; with semi-ring around polycrystalline diode group in the middle of insert to refer to that by grid structure separates; form disconnected left and right sides L type; its each p type island region and each N type district are injected by the P trap of power MOSFET or IGBT and N+ source respectively and diffuse to form.
In the inventive method, can also change the N of power MOSFET or IGBT by inverse ratio
+The source advances temperature or time, changes the puncture voltage of polycrystalline diode between grid, source, for example advances temperature height, time long, and its puncture voltage is just little, promptly changes trend and puncture voltage is inverse ratio.
The N of power MOSFET or IGBT wherein
+Each N district in source and the polysilicon diode group better adopts As (arsenic) to inject and forms.
Except that forming the polycrystalline diode, other manufacture method and power MOSFET or IGBT are basic identical in the inventive method, therefore are not specifically noted.
The inventive method both can be used to prepare N type power MOSFET or IGBT, also can be used for P type power MOSFET or IGBT, and just both impurity inject type opposite.
The power MOSFET of the integrated esd protection of the present invention or IGBT with respect to prior art, owing to adopt the aforementioned techniques scheme, inject the p type island region that forms the polycrystalline diode with the P trap, tradition high dose P
+It is much lower to inject the polycrystalline Zener diode p type island region phase specific concentration that forms, not only reduced leakage current between grid and the source electrode (emitter), the grid source-drain current has only original below 1/10, and the polysilicon diode group is semi-circular or symmetrical " L " type layout, under grid pressure welding area area the same terms, increased the release effective width of ESD electric current of polysilicon diode group, and make effectively to separate by the polysilicon diode group between the gate metal of power MOSFET or IGBT and the source metal, improved the ESD protection effect greatly.In addition, because the puncture voltage of the NPN pipe of base open circuit is relevant with base width, along with reducing of base width, its puncture voltage reduces, therefore can pass through the subsequent technique flexible in manufacture process grid source puncture voltage, realize grid source puncture voltage in the adjustability that does not change under the reticle condition, to satisfy the demand that is fit to the different application occasion.Polysilicon diode P district and N district respectively with P trap concentration and N
+Source concentration is basic identical, makes the formation of polycrystalline diode group need not additional light and cuts blocks for printing, and makes simply, and cost is lower.The technological process of the inventive method and existing power MOSFET or IGBT is compatible fully, and just the P trap with power MOSFET or IGBT injects and spread each p type island region that forms the polycrystalline diode; N with power MOSFET or IGBT
+The injection in source and diffuse to form each N type district of diode group, thereby need not to increase any reticle and additional technical steps.Adopt As (arsenic) to inject the N that forms power MOSFET or IGBT
+Each N district in source and the polysilicon diode group makes the gross area of polysilicon diode group reduce.
Below be example with N type band ESD power MOSFET; essence of the present invention is further understood in exemplary illustration and help; but the embodiment detail only is for the present invention is described; do not represent the present invention to conceive whole technical schemes down; therefore should not be construed as the total technical scheme of the present invention is limited; some are In the view of the technical staff; the unsubstantiality that does not depart from the present invention's design increases and/or change; for example simple the change or replacement of technical characterictic to have same or similar technique effect all belongs to protection range of the present invention.
Description of drawings
Fig. 1 has the power MOSFET equivalent electric circuit that the protection of polycrystalline Zener diode is arranged now between grid and source electrode.
Fig. 2 is a polycrystalline Zener diode cross-sectional view among Fig. 1.
Fig. 3 has the Zener diode protection for having now between grid and source electrode, no grid are inserted and referred to power MOSFET polycrystalline Zener diode schematic layout pattern.
Fig. 4 has the Zener diode protection for having now, has grid to insert finger power MOSFET polycrystalline Zener diode schematic layout pattern between grid and source electrode.
Fig. 5 is a kind of structural profile schematic diagram in esd protection unit of the power MOSFET of the integrated esd protection of the present invention.
Fig. 6 is the another kind of structural profile schematic diagram in the esd protection unit of the power MOSFET of the integrated esd protection of the present invention.
Fig. 7 is another structural profile schematic diagram of esd protection unit of the power MOSFET of the integrated esd protection of the present invention.
Fig. 8 is an ESD polycrystalline diode structure schematic diagram of the present invention.
Fig. 9 inserts the esd protection cell layout schematic diagram that refers to power MOSFET for the no grid of the integrated esd protection of the present invention.
Figure 10 inserts the esd protection cell layout schematic diagram that refers to power MOSFET for the grid that have of the integrated esd protection of the present invention.
Figure 11 is for having Zener diode protection power MOSFET grid source breakdown characteristics (abscissa is the 10V/ lattice, and ordinate is 20 μ A/ lattice) between existing grid and source electrode.
Figure 12 is for having polycrystalline diode protection power MOSFET grid source breakdown characteristic (abscissa is the 10V/ lattice, and ordinate is 20 μ A/ lattice) between grid of the present invention and source electrode.
Figure 13 is the grid source breakdown characteristic (abscissa is the 10V/ lattice, and ordinate is 20 μ A/ lattice) behind example 2 adjusting processes of the present invention.
Embodiment
Embodiment 1: referring to accompanying drawing 5,9, the esd protection unit of the integrated esd protection power MOSFET of the present invention is followed successively by from bottom to top: substrate 100, epitaxial loayer 101, oxide layer 1, polysilicon diode group 7, dielectric layer 4, gate metal 2 and source metal 3.The N of gate metal 2 and polysilicon diode group 7 one ends
+Doped region and power MOSFET grid connect, source metal 3 and polysilicon diode group 7 other end N
+Doped region and power MOSFET source electrode connect.On gate metal 2 and former utmost point metal 3, one deck passivation layer (not drawing among the figure) can be arranged.The esd protection unit is arranged at that semi-ring is provided with around grid pressure welding area 5 between the grid pressure welding area of power MOSFET and cellular region.
Preparation: by preparing power MOSFET technology usually, for example:, carry out the photoetching and the etching of end ring then with pre-oxygen about 920 ℃ of wet-oxygen oxidations growth 500A; Use energy 80KeV, dosage 5E14cm
-2Carry out the injection of end ring, advance under 1100 ℃, generating thickness of oxide layer when advancing is 10000A-15000A; Carry out the photoetching of active area, carry out the etching of active area again with wet etching; With wet-oxygen oxidation growth 900A left and right sides grid oxygen, LPCVD deposit polysilicon layer then, thickness is 6000A-10000A; After carrying out etching polysilicon, by the injection and the propelling of P trap layer, form the p type island region of polycrystalline diode simultaneously, for example use energy 80KeV, dosage 6E13cm
-2Carry out the injection of P trap layer, advance under 1150 ℃ then, the time is 100-150 minute; At power MOSFET source electrode N
+In the time of injection and propelling, form the N of polysilicon diode
+The district for example uses energy 100KeV, dosage 1.2E16cm
-2Carry out power MOSFET source electrode N
+With polysilicon diode N
+Injection, under 950 ℃, advance then, the time is 150 minutes, finishes the preparation of polycrystalline diode.All the other are by the common technology of preparation power MOSFET, for example LPCVD deposit TEOS and BPSG, and thickness is respectively 2000A and 8000A, refluxes under 950 ℃ and finishes the photoetching and the etching in hole, uses energy 120KeV, dosage 2E15cm
-2Carry out the P of power MOSFET
+Injection, under 950 ℃, advance, the time is 90 minutes, splash-proofing sputtering metal aluminium after thickness is the 4-5 micron, carries out the photoetching and the etching of metal, PECVD deposit Si
3N
4, photoetching and etching Si
3N
4, attenuate and back face metalization are finished manufacturing.
Embodiment 2: as embodiment 1, wherein power MOSFET source electrode N
+The propelling temperature change 970 ℃ into from 950 ℃, the time was changed to 180 minutes from 150 minutes, made grid source puncture voltage reduce.
Embodiment 3: referring to Fig. 6, and as embodiment 1 or 2, the P of polycrystalline diode group 7 one ends wherein
+Doped region and power MOSFET grid connect, source metal 3 and polysilicon diode group 7 other end P
+Doped region and power MOSFET source electrode connect.Wherein the polycrystalline diode group two ends of esd protection unit are p type island region, and the two ends p type island region is by P
-/ P
+Structure is formed, and P
+In the outermost end of diode group, all the other P district and P of polycrystalline diode group
-/ P
+P in the structure
-Identical, N
+The dosage in district is 5E15cm
-2-1.5E16cm
-2, P
+Dosage be 5E14cm
-2-8E15cm
-2P
+The propelling time be 90 minutes.
Embodiment 4: referring to Fig. 7, as embodiment 3, wherein power MOSFET source electrode P
+The propelling time become 30 minutes, P
+Do not permeate polysilicon layer, make P
+Be positioned at P
-In and at P
-The top, and make P
+Less than P
-
Embodiment 5: referring to Figure 10, as above-mentioned, grid insert to refer to the power MOSFET of structure, with semi-ring around polycrystalline diode group 7 in the middle of insert by grid and to refer to that structure separates, form disconnected left and right sides L type.
Integrated esd protection power MOSFET with routine, with the integrated esd protection power MOSFET of example 1 gained of the present invention, 2 kinds of devices that adopt 7 series connection polysilicon diode structures are carried out puncture voltage contrast test between the grid source, result such as Figure 11-13, by resolution chart as can be known, adopting the diode breakdown voltage of the power MOSFET of polysilicon Zener diode is 40V, and when gate source voltage is between 30V-40V, it is bigger to leak electricity, and is 20 μ A-120 μ A; And the power MOSFET of the integrated esd protection of the present invention, the puncture voltage of its diode group is 52V, and breakdown characteristics is better, grid source-drain current little (＜1 μ A).When the power MOSFET that adopts the preparation of embodiment 2 methods, its grid source puncture voltage is reduced to 42V (Figure 13) from 52V, thereby reaches flexible change polysilicon diode puncture voltage.
Structure of the present invention and preparation method can prepare the IGBT with esd protection equally.Adopt opposite doping type, can prepare the P type power MOSFET or the IGBT that are with ESD respectively.
To those skilled in the art, under this patent design and specific embodiment enlightenment, some distortion that can directly derive or associate from this patent disclosure and general knowledge, those of ordinary skills will recognize also can adopt additive method, or the substituting of known technology commonly used in the prior art, and the equivalence of feature changes or modification, the mutual various combination between feature, for example N of power MOSFET
+The N of source and polysilicon diode
+Inject to adopt arsenic and twice injection of phosphorus to form, or the like unsubstantiality change, can be employed equally, can both realize this patent representation function and effect, launch for example no longer one by one to describe in detail, all belong to this patent protection range.
Claims (10)
1. the power MOSFET of integrated esd protection or IGBT; comprise the esd protection unit that is connected across between power MOSFET or IGBT grid, source electrode; it is characterized in that each p type island region concentration is identical with the P trap concentration of power MOSFET or IGBT in the polycrystalline diode group of esd protection unit, the N of each N type district's concentration and power MOSFET or IGBT
+The source is identical; Polycrystalline diode group semi-ring between grid pressure welding area and cellular region is provided with around the grid pressure welding area, refers to structures if insert for grid, with semi-ring around polycrystalline diode group in the middle of insert the finger structure by grid and separate, form disconnected left and right sides L type.
2. according to the power MOSFET or the IGBT of the described integrated esd protection of claim 1, it is characterized in that forming the N in each N district and power MOSFET or IGBT in the polycrystalline diode group
+The source adopts As (arsenic) to inject.
3. according to the power MOSFET or the IGBT of claim 1 or 2 described integrated esd protections, it is characterized in that polycrystalline diode group two ends are the N type.
4. according to the power MOSFET or the IGBT of claim 1 or 2 described integrated esd protections, it is characterized in that polycrystalline diode group two ends are the P type.
5. according to the power MOSFET or the IGBT of the described integrated esd protection of claim 4, it is characterized in that two ends P type is P
-/ P
+
6. according to the power MOSFET or the IGBT of the described integrated esd protection of claim 5, it is characterized in that the P of two ends p type island region
-/ P
+Structure can be a left right model, and P
+Outermost end in the diode group; Also can be to go up mo(u)ld bottom half, and P
+Be positioned at P
-In and at P
-The top.
7. according to the power MOSFET or the IGBT of the described integrated esd protection of claim 6, it is characterized in that P
-/ P
+P in the last mo(u)ld bottom half structure
+Less than P
-
8. the preparation method of the power MOSFET of integrated esd protection or IGBT; be included between the grid of MOSFET or IGBT and source electrode and inject by ion and diffuse to form polycrystalline diode group esd protection unit; it is characterized in that polycrystalline diode group between grid pressure welding area and cellular region semi-ring around the setting of grid pressure welding area; if for grid are inserted the finger structure; with semi-ring around polycrystalline diode group in the middle of insert to refer to that by grid structure separates; form disconnected left and right sides L type; its each p type island region and each N type district are respectively by P trap and the N of power MOSFET or IGBT
+The source is injected and is diffuseed to form.
9. the preparation method of the power MOSFET of described integrated esd protection or IGBT according to Claim 8 is characterized in that after the polycrystalline diode forms, by changing the N of power MOSFET or IGBT
+The source advances temperature and/or time, changes the puncture voltage of polycrystalline diode between grid, source.
10. according to Claim 8 or the preparation method of the power MOSFET of 9 described integrated esd protections or IGBT, it is characterized in that forming the N of power MOSFET or IGBT
+Each N district adopts As (arsenic) to inject in source and the polycrystalline diode group.
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| CN102280382A (en) * | 2011-09-07 | 2011-12-14 | 杭州士兰集成电路有限公司 | Electrostatic discharge protecting structure integrated in insulated gate bipolar transistor (IGBT) apparatus and manufacturing method of electrostatic discharge protecting structure |
| CN103050442A (en) * | 2012-12-20 | 2013-04-17 | 杭州士兰微电子股份有限公司 | Power semiconductor device with antistatic discharge capacity and manufacturing method |
| CN103633071A (en) * | 2013-11-15 | 2014-03-12 | 四川长虹电器股份有限公司 | ESD (Electro-Static Discharge) protection circuit |
| CN106558580A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润上华半导体有限公司 | Semiconductor device with electrostatic discharge protection structure |
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| CN110911495A (en) * | 2019-10-30 | 2020-03-24 | 珠海迈巨微电子有限责任公司 | Trench VDMOS device integrated with ESD protection and manufacturing method |
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| CN112652618A (en) * | 2019-10-09 | 2021-04-13 | 半导体元件工业有限责任公司 | Electrostatic discharge processing of sense IGBTs using Zener diodes |
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| CN102280382A (en) * | 2011-09-07 | 2011-12-14 | 杭州士兰集成电路有限公司 | Electrostatic discharge protecting structure integrated in insulated gate bipolar transistor (IGBT) apparatus and manufacturing method of electrostatic discharge protecting structure |
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| CN103633071A (en) * | 2013-11-15 | 2014-03-12 | 四川长虹电器股份有限公司 | ESD (Electro-Static Discharge) protection circuit |
| US10373945B2 (en) | 2015-09-30 | 2019-08-06 | Csmc Technologies Fab2 Co., Ltd. | Semiconductor device having electro-static discharge protection structure |
| WO2017054595A1 (en) * | 2015-09-30 | 2017-04-06 | 无锡华润上华半导体有限公司 | Semiconductor device having electro-static discharge protection structure |
| CN106558580A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润上华半导体有限公司 | Semiconductor device with electrostatic discharge protection structure |
| CN106558580B (en) * | 2015-09-30 | 2019-12-10 | 无锡华润上华科技有限公司 | Semiconductor device with electrostatic discharge protection structure |
| CN108369968A (en) * | 2015-12-01 | 2018-08-03 | 夏普株式会社 | Avalanche photodide |
| CN108369968B (en) * | 2015-12-01 | 2021-07-27 | 夏普株式会社 | Avalanche photodiode |
| US10741541B2 (en) | 2016-10-04 | 2020-08-11 | Infineon Technologies Dresden Gmbh | Method of manufacturing a semiconductor device |
| CN109713036A (en) * | 2017-10-26 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of IGBT device and its manufacturing method |
| CN112652618A (en) * | 2019-10-09 | 2021-04-13 | 半导体元件工业有限责任公司 | Electrostatic discharge processing of sense IGBTs using Zener diodes |
| CN112652618B (en) * | 2019-10-09 | 2024-07-19 | 半导体元件工业有限责任公司 | Electrostatic discharge processing of sense IGBTs using zener diodes |
| CN110911495A (en) * | 2019-10-30 | 2020-03-24 | 珠海迈巨微电子有限责任公司 | Trench VDMOS device integrated with ESD protection and manufacturing method |
| CN117219621A (en) * | 2023-11-07 | 2023-12-12 | 上海功成半导体科技有限公司 | IGBT device structure |
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