CN101980339A - Error correction encoding method for dynamic random access memory (DRAM) buffer - Google Patents
Error correction encoding method for dynamic random access memory (DRAM) buffer Download PDFInfo
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Abstract
The invention discloses an error corrosion encoding method for a dynamic random access memory (DRAM) buffer, which comprises the following steps of: (1) prolonging a refresh cycle of the DRAM buffer and reducing refresh frequency; and (2) encoding and decoding data in the buffer. In the method, refresh time is set according to the most error-prone bits, some error data is compensated by error correction technology which is powerful enough to correct a plurality of bits, which means the refresh time can be prolonged, thereby reducing power consumption.
Description
Technical field
Embedded hardware design field of the present invention, storage energy-saving design field, particularly a kind of error correction/encoding method that is used for the DRAM buffer memory.
Background technology
At present, advanced technology makes big embedded DRAM buffer memory be integrated in becomes possibility on the sheet, more intensive than traditional SRAM, but in time refresh circuit is to guarantee data integrity, and DRAM is subject to the influence of equipment and materials, refresh cycle is played a decisive role, refresh the overwhelming majority that needed power consumption is put whole system energy consumption, so integrated having brought of big DRAM refreshed the problem that power consumption increases.
Embedded DRAM buffer memory integrated level height need refresh continually, otherwise owing to lose the as easy as rolling off a log information dropout that causes on some storage unit of situation such as electricity, make data unavailable, and high-frequency refreshing can increase power consumption greatly, and this has just violated green calculating, energy-conservation design philosophy.
In order to reach energy-conservation, processor has some idle conditions and supports low-power consumption mode, because the processor most of the time is in idle condition, so it is very important to reduce power consumption in idle condition, a kind of method commonly used is to use the power consumption threshold values for big memory block.But along with buffer memory density increases, the performance of this method and power consumption cost also increase, and therefore are not suitable for the DRAM of highly dense.
DRAM flush mechanism design in the embedded system also is the shortest time of storage unit retention data normally according to the refresh cycle under the worst condition.Along with the capacity increase of DRAM, the power consumption during idle state, refresh needed power consumption also increases thereupon.Before also the someone proposed some hardware mechanisms, when detecting different refreshing frequency and the data retention time of storage unit.Wherein a kind of software approach is, allowing among the DRAM the long page of data retention time to be distributed in the short page of retention time is distributed into and finishes, select a refresh cycle then, this cycle is to determine according to some pages or leaves commonly used, with respect to determining that according to whole DRAM the refresh cycle can reduce a lot of operations, also can reduce certain power consumption.But this method needs extra storage space to follow the trail of the data retention time of each page and the test that will depend on internal memory could identify those unessential bit memory cell.Another method based on test is a fixed bit position algorithm, has solved the problem of the high error rate in the refresh process.Because along with internal memory and buffer memory capacity increase, it realizes that difficulty also can increase based on the method for testing, cost is also very big.
The intelligence refresh technique skips over nearest row of visiting by increasing timer to each row when refreshing, so just can refresh some storage unit less, reaches purpose of energy saving.But intelligent method for refreshing poor efficiency very under idle condition because it is accessed not have cache lines under the idle condition, does not therefore just reach the purpose that reduces power consumption.The another kind of method that improves the refresh cycle is to use error-correcting code technique dynamically to discern and correct the bit of makeing mistakes.This method is provided with refresh time according to the bit of the most easily makeing mistakes, uses error correcting technique to remedy some misdatas, and powerful error correcting technique energy correcting multi-bit position means and can improve refresh time, thereby reduces power consumption.
Summary of the invention
In order to improve the refresh cycle, reduce refreshing frequency, finally reduce power consumption, the invention provides a kind of error correction/encoding method of the DRAM of being used for buffer memory.
The technical scheme that technical solution problem of the present invention is adopted is:
A kind of error correction/encoding method that is used for the DRAM buffer memory comprises the steps:
1) refresh cycle of raising DRAM buffer memory, reduces refreshing frequency;
2) data in the buffer memory are carried out Code And Decode, comprise the steps:
A) coding utilizes BCH code to encode for data in the buffer memory, and the data d of input is the K bit, and input data d and matrix G multiply each other and obtain a data coded message u, thereby save the data in the coding, and has increased inspection position, r position;
B) decoding comes the misjudgment classification by the symptom S that encodes, and uses error correction method according to error category
If S is 0, then data do not have mistake, if among the S who is non-zero then this position is a mistake;
If have only a bit-errors, then use the single-bit error correction method, if wrong figure place is more than two, then use many bits error correction method;
Wherein: S=v*H
T=(u+e) * H
T=(d*G+e) * H
T=e*H
T,
v＝u+e，G*H
T＝0，
E is meant the error message figure place, and v represents to have the coded message of mistake e.
The refresh cycle of described DRAM buffer memory is 150 μ s～500 μ s.
Described wrong figure place is that error correction procedure is as follows more than two: seek the wrong figure place among the S earlier, determine errors present then, the mistake with this position corrects again;
Suppose that the i position is 1,
σ(x)＝1+σ
1x+...+σ
tx
t＝(1-α
j1x)(1-α
j2x)...(1-α
jtx)，
J represents the bug check position in the formula, and t represents the bug check figure place, solves this equation root x, just obtains the position of error bit, and the dislocation of corresponding positions is corrected.
The line number of described H is t*m+1, and wherein t represents the maximum wrong number that can correct, and m then represents the length of data v.
Described many bits error correction method is 5EC6ED.
The beneficial effect that the present invention has is: at first, reduce the storage unit refreshing frequency, for system saves much electricity, reach green and calculate, the purpose of protection environment; Secondly, though the refresh cycle is long, make that the information in the storage unit is easily lost, powerful many bits Error Correction of Coding has guaranteed the correctness of data; Once more, though many bits error correction is strong, with respect to traditional Error Correction of Coding, the low price that it spent is very low, and the exceptional space that accounts for is little, postpones for a short time, and energy consumption is also low.Last exploitativeness of the present invention is strong, meets the current processor designing requirement, can be applied to rapidly on the various processors, has the wide range of commercial purposes.
Description of drawings
Fig. 1 is the process flow diagram of an embodiment of the present invention.
Specific implementation method
Be described in further detail below in conjunction with the error correction/encoding method of accompanying drawing the DRAM of being used for buffer memory provided by the invention:
Fig. 1 is the process flow diagram of an embodiment of the present invention, and this method comprises the steps:
(1) improve the refresh cycle, reduce refreshing frequency:
DRAM in the embedded hardware distributes and compares comparatively dense, number of bits depends critically upon equipment and materials according to the possibility of makeing mistakes, in the power consumption of total system, the needed energy consumption that refreshes of DRAM and buffer memory accounts for greatly, and higher refreshing frequency can increase power consumption greatly.In order to reduce energy consumption, consider the setting in cache flush cycle during the processor design, too frequently can increase power consumption, and the oversize data that make easily of cycle are made mistakes.Usually all will select a best refresh cycle according to the hardware material, the feasible number of memory cells of makeing mistakes is few as far as possible, and error correction also realizes easily like this.The refresh cycle of buffer memory is generally 30us, and it is 150us that the two false retrievals surveys of single error correcting (SECDED) can make the refresh cycle, and the error correcting coding (Hi-ECC) that proposes among the present invention can make the refresh cycle be set to 440us.Refresh cycle is short, be that circuit refreshes frequently, then power consumption is bigger, the raising refresh cycle can significantly reduce power consumption, but can improve data cached probability of errors, the ability that error bit detects and corrects also is limited, when data cached position error probability is big (multidigit is made mistakes simultaneously), may be just can't the correction of data position.
(2) data in the buffer memory are carried out Code And Decode
Before refreshing this, some electric currents can run off, and may have some data messages and lose, thus need carry out error correction, wherein:
When 1. encoding, performing step
I. Shu Ru data d is the K bit, and with a matrix G who pre-defines, input data d and matrix G multiply each other and obtain a data coded message u, and (u=d*G), raw data just is stored in coding and has suffered like this, and has increased r position inspection;
2. decoding, performing step
Decoding and coding are corresponding, when CPU will propose data in the buffer memory, and will be to the data decoding whether to check wrong position.
The decode logic unit detects and repairs any mistake that is stored among the coding u, returns to original data, and this decoding unit can be divided into three parts;
I. mistake is searched, a coded message v (v=u+e) who has mistake e, the first symptom S (S=v*HT (transposition)) that the transposition of a v and a matrix H that pre-defines is multiplied each other and obtains encoding of decoding unit; The e here is meant debugging false information figure place, the debugging position, r position that the back of just encoding increases, and the value that the transposition of matrix G and H multiplies each other is 0.The line number of H is t*m+1, and wherein t represents the maximum wrong number that can correct, and t is 5 in 5EC6ED, and m then represents the length of data v,
S＝v*HT＝(u+e)*HT＝(d*G+e)*HT＝e*HT
Because the data when G*HT=0, the d here are exactly coding, e is exactly the debugging position, r position that the coding back increases.The S that obtains is exactly a string 01 data, if promising 1, represent that then this bit data is wrong, just this position among the data u is wrong, and correct and come just, or 0, or 1, the too many 5EC6ED of mistake also can't handle.First row in matrix H are that 1, the first row also is 1 entirely entirely, and other elements are the i power of a, and i be (2*r-1) * (c-1), and r is row number, and since 0, c be to be listed as number, and since 1, and a is determined by a polynomial expression.
II. wrong the classification,, if S is 0, then data do not have mistake, otherwise can find the mistake of specific bit for non-zero according among the S who.
III. error correcting corrects to get final product according to the error bit of S appointment; If have only 1 bit-errors, so only just with the single-bit error correction method because realize simple, when the mistake figure place is more, will be with many bits error correction scheme, time complexity height.Suppose that the i position among the S is 1, according to the front matrix multiple
J represents the bug check position, and t represents the bug check figure place, has only 6 here, will determine dislocation at first exactly, and the value of S can only be checked wrong figure place, but where can not determine mistake.Next the position that will locate errors is exactly corrected data then.Provide a polynomial expression σ (x)=1+ σ
1X+...+ σ
tx
t=(1-α
J1X) (1-α
J2X) ... (1-α
JtX), solve this equation root x, just obtain the position of error bit, the resulting x of separating makes that the value of equation equation is 0, and it is very simple that data are corrected, and data are exactly nothing but 0 and 1, make into opposite just.
The present invention adopts the error correction of many bits, can carry out debugging and correction to multidigit, but required extra cost but is equivalent to single bit Error Correction of Coding.The present invention proposes the refresh cycle of improving buffer memory, use existing coded system then and combine.The cache flush cycle originally is short, so the data bit probability of errors is lower, utilizes single bit error correction dibit position debugging (SECDED) method just can deal with.In the bigger data bit of error probability, need with many bits error correction debugging mechanism, 56 debuggings of error correction (5EC6ED) are exactly a kind of, this method cost is higher, needed extraneous information is many, and is bigger as the inspection figure place r in the increase of coding stage of front, is its Code And Decode process complexity on the other hand, the needed time is also more, has a strong impact on systematicness.And emphasis of the present invention is wrong classification, if data there are not mistake or have only 1 bit-errors, so just just much of that with SECDED, its speed is fast relatively, and when wrong figure place is more, will use 5EC6ED, here usefulness is the 5EC6ED BCH code, many bits probability of errors is very low usually, if wrong figure place surpasses 5, that also cannot have been corrected.The possibility that many bits are made mistakes simultaneously is very little, so in the time of most of still is that an error unit is corrected, principal feature is first debugging, mis-classification then, adopt corresponding correction technology according to error category again, wherein part all is that one or zero bit are made mistakes.The principle of single bit error correction dibit position debugging is similar, and its Code And Decode matrix is simple relatively, so complexity is not high.
According to above analysis, of the present invention have a following effect:
1) with reduce refreshing frequency and combine:
DRAM in the embedded hardware distributes and compares comparatively dense, the possibility that the bit data are made mistakes depends critically upon equipment and materials, in the power consumption of whole system, the needed energy consumption that refreshes of DRAM and buffer memory accounts for greatly, and higher refreshing frequency can increase power consumption greatly. What present processor design at first will be considered is exactly energy-conservation, refreshes number of times by minimizing and just can reduce a lot of power consumptions. Refresh cycle, the long problem of bringing was easily so that DRAM causes data to be made mistakes because losing electricity, thereby needed a kind of good error correction scheme.
2) required exceptional space is little
For many bits Error Correction of Coding, needed memory space is very big, and for example 56 debuggings of error correction (5EC6ED) are the excessive data information that 64 bytes need 51 bits for the capable size of buffer memory, have approximately increased by 10% exceptional space. This has caused general many bits error correction scheme to be difficult to realize that the present invention has then overcome this point, and two debugging (SECDED) schemes of needed exceptional space and single error correction are similar, 11 bits, about 2%, similar on the effect of the present invention before all, institute takes up space then identical with the latter.
3) little delay
The Error Correction of Coding hardware of 56 debuggings of error correction (5EC6ED) is realized very complicated and can be increased very long decoding delay, postpones size with needing the bit figure place of error correction and the capable data figure place of buffer memory to be directly proportional. If when each cache access, all need complete encoding and decoding, can greatly increase so cache access and postpone. The present invention then utilizes the buffer memory part of easily makeing mistakes can allow its invalid such fact, has avoided the high latency decoding in some typical operation processes. When reading delegation from buffer memory, for this journey produces a synthetic determination, the information of this judgement only comprises 0,1, or a higher wrong number, iff being 0 or 1, then only needs a simple decode procedure to carry out error correction, clock cycle of these needs. When less for wrong figure place, only need simple error correction, postpone very little, for the many situations of wrong figure place, then the error correction procedure complexity postpones bigger, but the possibility that this situation occurs is very little, so general needs very little delay just can finish the error correction function.
4) low-power consumption
The present invention adopts the capable space cost that reduces powerful many bit error-correcting codes of very big buffer memory, yet big buffer memory guild brings other problems, the capable size of tradition buffer memory is 64 bytes, and the present invention's employing is 1024 bytes, when from rudimentary internal memory, reading and writing data, can go out existing size does not mate, when the 64 byte sub-block revised during 1024 byte buffer memorys are capable, need to carry out error correction, if full line (1024 byte) is carried out error correction, complexity is bigger so, power consumption is also very big, only the sub-block of this 64 byte is carried out error correction, so just reduced a lot of operations, greatly reduced power consumption. For the capable access of buffer memory, can not carry out debugging and error correction to whole row, because the figure place of Code And Decode operation processing is too many like that, delay is big and energy resource consumption is also big, can only carry out the purpose that error correction just can reach low energy consumption for the part sub-block of row.
Claims (5)
1. an error correction/encoding method that is used for the DRAM buffer memory is characterized in that comprising the steps:
1) refresh cycle of raising DRAM buffer memory, reduces refreshing frequency;
2) data in the buffer memory are carried out Code And Decode, comprise the steps:
A) coding utilizes BCH code to encode for data in the buffer memory, and the data d of input is the K bit, and input data d and matrix G multiply each other and obtain a data coded message u, thereby save the data in the coding, and has increased inspection position, r position;
B) decoding comes the misjudgment classification by the symptom S that encodes, and uses error correction method according to error category
If S is 0, then data do not have mistake, if among the S who is non-zero then this position is a mistake;
If have only a bit-errors, then use the single-bit error correction method, if wrong figure place is more than two, then use many bits error correction method;
Wherein: S=v*H
T=(u+e) * H
T=(d*G+e) * H
T=e*H
T,
v＝u+e，G*H
T＝0，
E is meant the error message figure place, and v represents to have the coded message of mistake e.
2. error correction/encoding method according to claim 1 is characterized in that: the refresh cycle of described DRAM buffer memory is 150 μ s～500 μ s.
3. error correction/encoding method according to claim 1 is characterized in that: described wrong figure place is that error correction procedure is as follows more than two: seek the wrong figure place among the S earlier, determine errors present then, the mistake with this position corrects again;
Suppose that the i position is 1,
σ(x)＝1+σ
1x+...+σ
tx
t＝(1-α
j1x)(1-α
j2x)...(1-α
jtx)，
J represents the bug check position in the formula, and t represents the bug check figure place, solves this equation root x, just obtains the position of error bit, and the dislocation of corresponding positions is corrected.
4. error correction/encoding method according to claim 1 is characterized in that: the line number of described H is t*m+1, and wherein t represents the maximum wrong number that can correct, and m then represents the length of data v.
5. according to any one described error correction/encoding method of claim 1-4, it is characterized in that: described many bits error correction method is 5EC6ED.
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| CN110660422A (en) * | 2018-06-29 | 2020-01-07 | 上海磁宇信息科技有限公司 | Cache system used in cooperation with error correction magnetic random access memory |
| CN112652341A (en) * | 2020-12-22 | 2021-04-13 | 深圳市国微电子有限公司 | Dynamic memory refresh control method and device based on error rate |
| WO2022151730A1 (en) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | Memory system |
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| US11935616B2 (en) | 2021-01-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Comparison system |
| US11990201B2 (en) | 2021-01-14 | 2024-05-21 | Changxin Memory Technologies, Inc. | Storage system |
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| CN102915769A (en) * | 2012-09-29 | 2013-02-06 | 北京时代民芯科技有限公司 | Implementation and optimization method for processor EDAC (error detection and correction) circuit |
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| CN104239220A (en) * | 2013-06-13 | 2014-12-24 | 华为技术有限公司 | Memorizer refreshing method and device |
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| CN105022675A (en) * | 2015-08-19 | 2015-11-04 | 首都师范大学 | Correcting device and method for caching 4-bit data flipping errors of embedded microprocessor |
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| CN105607726A (en) * | 2015-12-24 | 2016-05-25 | 浪潮(北京)电子信息产业有限公司 | Method and device for lowering internal storage power consumption of high-performance computing cluster |
| CN105607726B (en) * | 2015-12-24 | 2018-11-23 | 浪潮(北京)电子信息产业有限公司 | A kind of method and device reducing High Performance Computing Cluster power consumption of internal memory |
| CN110660422A (en) * | 2018-06-29 | 2020-01-07 | 上海磁宇信息科技有限公司 | Cache system used in cooperation with error correction magnetic random access memory |
| CN112652341A (en) * | 2020-12-22 | 2021-04-13 | 深圳市国微电子有限公司 | Dynamic memory refresh control method and device based on error rate |
| CN112652341B (en) * | 2020-12-22 | 2023-12-29 | 深圳市国微电子有限公司 | Dynamic memory refresh control method and device based on error rate |
| WO2022151730A1 (en) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | Memory system |
| US11599417B2 (en) | 2021-01-14 | 2023-03-07 | Changxin Memory Technologies, Inc. | Error correction system |
| US11791009B2 (en) | 2021-01-14 | 2023-10-17 | Changxin Memory Technologies, Inc. | Error correction system |
| US11886292B2 (en) | 2021-01-14 | 2024-01-30 | Changxin Memory Technologies, Inc. | Memory system |
| US11935616B2 (en) | 2021-01-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Comparison system |
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Application publication date: 20110223 |