CN101976551A - Display driving circuit, liquid crystal display and display driving method - Google Patents
Display driving circuit, liquid crystal display and display driving method Download PDFInfo
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- CN101976551A CN101976551A CN 201010527269 CN201010527269A CN101976551A CN 101976551 A CN101976551 A CN 101976551A CN 201010527269 CN201010527269 CN 201010527269 CN 201010527269 A CN201010527269 A CN 201010527269A CN 101976551 A CN101976551 A CN 101976551A
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Abstract
The invention discloses a display driving circuit, a liquid crystal display and a display driving method. The display driving circuit comprises a time schedule controller, a grid driving circuit, a control unit, a boost converter and a voltage level shifter, wherein the time schedule controller is used for supplying a first start signal, and the voltage level shifter increases the level of the first start signal to obtain a second start signal; the grid driving circuit comprises a plurality of shifting buffer units which are connected in series and are driven by the second start signal and the voltage level shifter to generate grid signals; and the second start signal and the grid signal generated by the kth shifting buffer unit are used by the control unit to switch the high working voltage which is supplied to the voltage level shifter by the boost converter to the range suitable for driving the grid driving circuit.
Description
Technical field
The present invention is relevant to a kind of circuit of display driving, LCD and display drive method, refers to a kind of circuit of display driving, LCD and display drive method that low temperature opens the beginning problem that solve especially.
Background technology
(Liquid Crystal Display LCD) has that external form is frivolous, power saving and an advantage such as radiationless to LCD, has become one of present widely used flat-panel screens.Its principle of work applies electric field to liquid crystal layer, makes the liquid crystal molecule in the liquid crystal layer change ordered state to adjust the penetration of liquid crystal layer, and light source and colored filter that cooperating backlight module is again provided come color display.Fig. 1 is the synoptic diagram of available liquid crystal display 100.As shown in Figure 1, LCD 100 comprises display panel 110, time schedule controller (Timing Controller) 120, gate driver circuit (Gate Driver) 130, source electrode drive circuit (Source Driver) 140.Display panel 110 comprises a plurality of pixel cells 150, many data line D
1～D
M, and many gate lines G
1～G
N Time schedule controller 120 provides gate driver circuit 130 and the required control signal of source electrode drive circuit 140 runnings; Gate driver circuit 130 can produce a plurality of signals according to this control signal.Gate lines G
1～G
NWith data line D
1～D
MThe data-signal that signal and source electrode drive circuit 140 are produced offers pixel cell 150 with display image respectively.
In order to reduce cost of goods manifactured, gate driver circuit 130 is integrated on the display panel 110 that comprises pixel cell 150, can replace script grid-driving integrated circuit (Gate Driver IC) and save the IC use amount, with minimizing signal lead number.This technology and traditional grid-driving integrated circuit framework all need shift cache unit (Shift Register) and voltage level shift unit (Level Shifter), and this voltage level shift unit is used for control signal originally is promoted to the accurate position of a high voltage with the driving grid driving circuit.But on the practice, this technology utilizes TFT NMOS processing procedure to synthesize shift cache unit, and the voltage level shifter circuit is incorporated in the pulse width modulation integrated circuit (PWM IC), and to use standard CMOS (CMOS) integrated circuit manufacture process shift cache unit and voltage quasi position shift unit to be incorporated on the practice of one chip different with traditional grid-driving integrated circuit.But because processing procedure and light shield quantitative relation, the characteristic of TFT NMOS is poor than CMOS, is therefore wishing to get under the condition of same current, must set higher TFT NMOS gate-source voltage (V
GS) and make bigger size of components, and the gate-source voltage when desiring assembly is closed set also must be very low.
In addition, because of the processing procedure factor causes the component characteristic drift, can make the shift cache unit circuit that is synthesized when low temperature opens the beginning (Cold-Start), misoperation can take place.Fig. 2 is the circuit diagram of shift cache unit 200 in the prior art, Fig. 3 A is the sequential chart of shift cache unit 200 under the normal running, when room temperature starts, opening beginning signal ST can send a pulse that node CP1 is risen to a voltage quasi position near ST earlier, when frequency signal CLK sends, the current potential that node CP1 will store originally via the mode of coupling (Coupling) can be added and change up via the Cgd electric capacity of transistor M2, promote the current potential of node CP1 once more, this moment, transistor M2 can be unlocked, the CLK signal is sent to output terminal SR_OUT, reaches the signal output of the first order.But when cold-starting, because the magnitude of current of transistor M2 contribution itself can reduce, that is the degree of assembly conducting a little less than, under the fixing situation of gate-source voltage and size of components, add the electric leakage of transistor M4, can make output terminal SR_OUT current potential to draw high, cause the signal output abnormality, shown in Fig. 3 B.
The control signal interlock circuit that is used for producing driving grid driving circuit 140 as shown in Figure 4.When at room temperature starting, use two-stage charge pump (Charge Pump) circuit 410 can reach (not comprising charge pump circuit 430) the signal output of all shift cache units.But when starting at low temperatures, as mentioned above, at assembly gate-source voltage (V
GS) with the condition of fixed size under, main switch conducting fully makes signal output produce unusually.At present to the solution of this problem for increasing one-level charge pump circuit 430 again, with the high working voltage V of gate driver circuit 130
GHPromote one-level again, also be about to gate-source voltage and promote one-level, make main switch conduction ability strengthen, also promoted the ability of current drives simultaneously, keep the signal output of each grade shift cache unit.Open beginning circuit that problem is used at solution low temperature at present and mainly contain following shortcoming:
1. owing to increased one-level charge pump circuit 430, increased the usable floor area of printed circuit board (PCB) (PCB) more.
2. owing to increased one-level charge pump circuit 430, power attenuation increases more.
3. the output voltage of charge pump is a fixed value, can't freely adjust.In addition, because component characteristic has variability, therefore the specification of required power supply can be different thereupon.If will meet the power supply of gate driver circuit 130 required specifications, must increase zener diode (Zener Diode), not setting except voltage also can increase cost the elasticity.
Therefore but need a kind of low-power consumption Flexible Design, and can solve gate driver circuit is integrated in circuit and the driving method that the low temperature that is taken place in the display panel process technique opens the beginning problem.
Summary of the invention
One embodiment of the invention provide a kind of circuit of display driving, comprise time schedule controller, open the beginning signal in order to produce one first; One gate driver circuit comprises the shift cache unit of a plurality of serial connections, and wherein the shift cache unit of these a plurality of serial connections opens the beginning signal according to one second and a pre-driver signal produces a plurality of signals in regular turn; One control module is electrically connected on a k shift cache unit of this gate driver circuit, in order to second to open the beginning signal and this k signal that shift cache unit produced produces an output voltage according to this; One boost converter is electrically connected on this control module, in order to produce a high working voltage according to this output voltage; An and voltage level shift unit, be electrically connected on this time schedule controller, this boost converter and this gate driver circuit, open the beginning signal to produce this pre-driver signal of driving this gate driver circuit and this second in order to open the beginning signal according to this high working voltage and this first.
Another embodiment of the present invention provides a kind of display drive method, be executed in circuit of display driving as the aforementioned, this method comprises: input one is opened beginning signal and a pre-driver signal to this gate driver circuit, makes that a plurality of shift cache units in this gate driver circuit produce a plurality of signals in regular turn; Import this and open beginning signal and this k signal that shift cache unit produced to this control module; This control module opens the beginning signal according to this and this k signal that shift cache unit produced produces an output voltage; This boost converter produces a high working voltage according to this output voltage; And this voltage level shift unit drives this pre-driver signal of this gate driver circuit with generation according to this high working voltage.
Another embodiment of the present invention provides a kind of LCD, comprises one first substrate; One second substrate; One liquid crystal layer, this liquid crystal layer is between this first substrate and this second substrate; One pel array is formed on this first substrate; An and circuit of display driving.This circuit of display driving comprises time schedule controller, opens the beginning signal in order to produce one first; One gate driver circuit, be formed on this first substrate, and be electrically connected on this pel array, this gate driver circuit comprises the shift cache unit of a plurality of serial connections, and wherein the shift cache unit of these a plurality of serial connections produces a plurality of signals in regular turn according to a pre-driver signal; One control module is electrically connected on a k shift cache unit of this gate driver circuit, in order to open the beginning signal and this k signal that shift cache unit produced produces an output voltage according to one second; One boost converter is electrically connected on this control module, in order to produce a high working voltage according to this output voltage; And a voltage level shift unit is electrically connected on this time schedule controller, this boost converter and this gate driver circuit, in order to first to open the beginning signal and open the beginning signal with this pre-driver signal of producing this gate driver circuit of driving and this second according to this high working voltage and this.
Compared to prior art, the present invention proposes a kind of circuit of display driving, LCD and display drive method, solution is integrated in gate driver circuit in the technology on the display panel, opens the low temperature that can take place under the beginning at low temperature and opens beginning (Cold-Start) problem.Under the consideration of low-power consumption, make each grade shift cache unit of gate driver circuit can normally export signal to drive the pel array on the display panel.
Description of drawings
Fig. 1 is the synoptic diagram of LCD in the prior art;
Fig. 2 is the circuit diagram of shift cache unit in the prior art;
Fig. 3 A is the sequential chart under the shift cache unit normal running among Fig. 2;
Fig. 3 B opens the sequential chart of beginning during problem for shift cache unit generation low temperature among Fig. 2;
Fig. 4 is existing interlock circuit in order to the driving grid driving circuit;
Fig. 5 is the display and the associated driver circuitry figure thereof of the embodiment of the invention;
Fig. 6 is the gate driver circuit figure of the embodiment of the invention;
Fig. 7 is the circuit diagram of the operating voltage commutation circuit of the embodiment of the invention;
Fig. 8 A is one of several unlike signal correlation timings figure of the circuit of display driving of the embodiment of the invention;
Fig. 8 B be the embodiment of the invention circuit of display driving several unlike signal correlation timings figure two.
Wherein, Reference numeral:
100,500: LCD
110: display panel
120,510: time schedule controller
130,530: gate driver circuit
140,570: source electrode drive circuit
150: pixel cell
200,531～537: shift cache unit
410,430: charge pump circuit
CP1: node
STi, ST: open the beginning signal
G
1～G
N: signal
M2, M4, MN1, MP4, MP5, MP6: transistor
CKi, XCKi, CK, XCK: frequency signal
SR_OUT: output terminal
520: the voltage level shift unit
540: boost converter
541: the first voltage up converting circuit
543: the second voltage up converting circuit
550: control module
551: the operating voltage commutation circuit
553: bias generating circuit
555: multiplexer
560: negative charge pump circuit
580: pel array
590: infrabasal plate
The 5510:SR bolt lock device
The 5512:D D-flip flop
V
DD1, V
DD2, V
SS: voltage source
V
GH, V
GH1, V
GH2: high working voltage
V
GL: low-work voltage
Ref_SEL: voltage is selected signal
Ref_H: high reference voltage
Ref_L: low reference voltage
PX: pixel cell
Embodiment
The present invention proposes a kind of circuit of display driving, solves gate driver circuit is integrated in the technology on the display panel, opens the low temperature that can take place under the beginning at low temperature and opens the beginning problem.Under the consideration of low-power consumption, make each grade shift cache unit of gate driver circuit can normally export signal to drive the pel array on the display panel.
Fig. 5 is the structural representation of the LCD 500 of the embodiment of the invention.As shown in Figure 5, LCD 500 comprises: upper substrate (not shown), infrabasal plate 590, circuit of display driving and pel array 580.Circuit of display driving comprises time schedule controller 510, voltage level shift unit 520, gate driver circuit 530, boost converter 540 (Boost Converter), control module 550, negative charge pump circuit 560 (Negative Charge Pump Circuit) and source electrode drive circuit 570.Liquid crystal layer is between upper substrate and infrabasal plate 590, and the brilliant molecule of liquid crystal layer internal memory sealing liquid, and pel array 580 comprises a plurality of pixel cell PX, via multidata line D
1～D
MBe electrically connected on source electrode drive circuit 570, in addition via multiple-grid polar curve G
1～G
NBe electrically connected on gate driver circuit 530.Wherein gate driver circuit 530 can be integrated in infrabasal plate 590 with pel array 580.
The sequential action of the whole LCD 500 of time schedule controller 510 controls, the time that cooperates each picture frame to show, set sweep start and provide gate driver circuit 530 to operate the required signal STi that begins that opens, make gate driver circuit 530 produce signal and set the switch of pixel cell PX, and provide associated control signal to make it produce view data to source electrode drive circuit 570.Boost converter 540 is used for voltage source V
DD1See through and boost to obtain the higher voltage value.In the present embodiment, with two voltage up converting circuit serial connections, the voltage source V that produced of first voltage up converting circuit 541 wherein
DD2To supply with source electrode drive circuit 570 and other driving circuit such as coffee sign indicating number and proofread and correct (Gamma Correlation) circuit and use, and the voltage source V that first voltage up converting circuit 541 is produced
DD2Inputing to second voltage up converting circuit 543 does and boosts for the second time.Boost converter 540 inner employing switched topology frameworks also utilize inductance, electric capacity, reach needed voltage quasi position output via adjusting resistance, the switched topology utilizes the change of switch work period (duty) to adjust the I/O ratio, that is electric current is not always toward load end stream, but utilizes the switch one open-one close that inductance, electric capacity charging and discharging are reached; And adopt charge pump circuit in the prior art, if will reach identical voltage quasi position, just necessary many string one-level charge pumps (two diodes), each diode all can have the conduction impedance and forward voltage forward of equivalence, therefore every many string one-levels will cause the loss on the efficient, and for load end, do not have a burning voltage function (load consumption directly is provided), therefore as desiring to reach jointly a voltage quasi position, the efficient of boost converter 540 can be better than charge pump, and the printed circuit board (PCB) usable floor area also can be saved many.Voltage level shift unit 520 is electrically connected on time schedule controller 510 and boost converter 540, is opened the high working voltage V that beginning signal STi and boost converter 540 are provided according to what time schedule controller 510 exported
GHWith begin signal ST and the pre-driver signal (as Vss, CK, the XCK of Fig. 5) of opening after the voltage level displacement that produces driving grid driving circuit 530.Negative charge pump circuit 560 is connected in voltage level shift unit 520, and provides voltage level shift unit 520 required low-work voltage V
GL
Gate driver circuit 530 internal circuit blocks as shown in Figure 6.Gate driver circuit 530 comprises the shift cache unit 531～537 of a plurality of serial connections, and each shift cache unit 531～537 has a signal output terminal with output signal G
1～G
N, first order shift cache unit 531 receives the signal G that opens beginning signal ST and back one-level shift cache unit 533 outputs
2Drive with output signal G
1, the signal that other grade shift cache unit 533～537 receives shift cache unit 535～537 outputs of back one-level drives, and receives the signal G of shift cache unit 537 outputs of N level as N-1 level shift cache unit 535
N, to produce a plurality of signal G in regular turn
1～G
NInput to pel array 580 on the display panel via many gate lines, come display image.Each shift cache unit 531～537 receives a pre-driver signal in addition, and it comprises as first frequency signal CK, second frequency signal XCK and voltage source V
SSDeng signal, voltage source V wherein
SSAs each shift cache unit 531～537 output signal G
1～G
NPotential reference.In the present embodiment, shift cache unit 531～537 serial connection modes pre-driver signal Vss, CK, the XCK required with it is used to limit spirit of the present invention, and the present invention also can otherwise be connected in series shift cache unit 531～537.
Please continue with reference to figure 5, control module 550 is electrically connected on gate driver circuit 530, and beginning signal ST and k the signal G that shift cache unit produced are opened in reception
k, utilize received signal ST and G
kThe high working voltage V that boost converter 540 is provided
GHDynamically switch to the scope that is fit to driving grid driving circuit 530.When cold-starting took place, boost converter 540 was automatically with V
GHSwitch to higher high working voltage V
GH1, when the gate driver circuit enabling, boost converter 540 also can be automatically with V
GHSwitch to lower high working voltage V
GH2, to reduce the total system power attenuation.Because in the present embodiment, the signal that the shift cache unit of one-level was exported after each shift cache unit received drives, when wherein arbitrary grade of shift cache unit can't normally be exported signal because of the cold-starting problem, therefore all shift cache units all can break down, and control module 550 can be set at and receive the signal G that final stage shift cache unit 537 is produced in preferred embodiment
N, whether just can detect has shift cache unit 531～537 generation low temperature to open the beginning problem.
As shown in Figure 5, control module 550 comprises: operating voltage commutation circuit 551, and in order to receive the signal G that k level shift cache unit is produced
kWith open beginning signal ST, the signal G that produced of k level shift cache unit wherein
kCan be the signal G that final stage shift cache unit is produced
N, select signal Ref_SEL to produce a voltage; Bias generating circuit (Bias voltage generation circuit) 553 in order to produce the stable reference voltage of a plurality of different magnitudes of voltage, comprises high reference voltage Ref_H and low reference voltage Ref_L; Multiplexer 555 (MUX), be electrically connected on operating voltage commutation circuit 551 and bias generating circuit 553, the a plurality of reference voltage Ref_H, the Ref_L that are produced with bias generating circuit 553 are as input, and select signal Ref_SEL to select one among a plurality of reference voltage Ref_H, the Ref_L according to voltage and export, multiplexer 555 output terminals directly are electrically connected to second voltage up converting circuit 543, by selecting different reference voltages position standard to change the high working voltage V that second voltage up converting circuit 543 is exported
GHVoltage level.
Operating voltage commutation circuit 551 internal circuit diagrams as shown in Figure 7, its operating principle will cooperate Fig. 8 A and Fig. 8 B to explain with sequential.This circuit comprises three work phase places (phase), and wherein phase place 1 (phase1) is reset and initialization for circuit, latch circuit (Latch) and interdependent node (node) is done to reset and initialization, shown in Fig. 8 A.Receive when the time begins at each picture frame (Frame) and to open beginning signal ST, this moment final stage shift cache unit 537 signal G
NTherefore do not send as yet, opening beginning signal ST is the accurate position of high logic, the signal G of final stage shift cache unit
NBe the accurate position of low logic.The beginning signal ST that opens of high levle makes N transistor npn npn MN1 open, the replacement input end (R end) of SR bolt lock device (SR Latch) 5510 is pulled to the accurate position of low logic, and be provided with input end (S end) because of phase inverter is pulled to the accurate position of high logic, so output terminal Q is high logic accurate, Q ' end is accurate position of low logic and the input end D that is connected to D flip-flop (D flip-flop) 5512, such output can cause P transistor npn npn MP4, MP5, MP6 is a closing state, the pulse input of opening beginning signal ST simultaneously can make the accurate position of low logic of D flip-flop output, and promptly voltage selects signal Ref_SEL to be the accurate position of low logic.
Next, in phase place 2 (phase 2), when gate driver circuit 530 was finished replacement and initialization and normal the no low temperature of operation and opened the beginning problem and take place, MN1 remained closed condition, wait G
NSignal is come in.Work as G
NWhen signal was exported a pulse, MP6 was because of the bias voltage conducting, changed the R end of SR bolt lock device 5510 into high logic accurate position, and the S end is the accurate position of low logic.And the output Q of SR bolt lock device 5510 causes all conductings of transistor MP4 and MP5 for the accurate position of low logic, Q ' is the accurate position of high logic.Work as G
NWhen signal transfers the accurate position of low logic to by the accurate position of high logic, the frequency CLK of D flip-flop 5512 is imported in the pulse of opening beginning signal ST simultaneously, and the voltage that the output terminal Q that makes D flip-flop 5512 is exported selects signal Ref_SEL to rise to the accurate position of high logic by the accurate position of low logic, make multiplexer 555 select low reference voltage REF_L to export second voltage up converting circuit 543 to, make high working voltage V
GHAutomatically by V
GH1Switch to V
GH2, and continue to keep.
The function that opens beginning signal ST signal is except being to be to reset and initializing circuit, also is to be used to upgrade the voltage that operating voltage commutation circuit 551 exported select the position of signal Ref_SEL accurate.When beginning to enter picture frame 3, G
NSignal by the accurate potential drop of high logic to the accurate position of low logic, so transistor MP6 closes, and opens the beginning problem if low temperature take place gate driver circuit 530, and makes the G of picture frame 3
NWhen should exporting, signal pulse but fails normally to export, cause transistor MP6 to continue to close, open beginning signal ST this moment and rise to the accurate position of high logic by the accurate position of low logic once more, because the Q ' of SR latch unit 5510 end is the accurate position of low logic, cause P transistor npn npn MP5 for closing, and opening the frequency that beginning signal ST can trigger D flip-flop 5512 makes the voltage of the output terminal Q output of D flip-flop 5512 select signal Ref_SEL to change to the accurate position of low logic, make multiplexer 555 select high reference voltage REF_H to export second voltage up converting circuit 543 to, make high working voltage V
GHAutomatically by V
GH2Switch to V
GH1
The sequential chart that low temperature opens the beginning problem then promptly takes place for gate driver circuit 530 in Fig. 8 B at the beginning.Phase place 1 through oversampling circuit reset with initialization after, at picture frame 1 inner grid signal G
NSignal pulse is normally output not, circuit operation is as described in Fig. 8 A, the voltage that D flip-flop 5512 is exported is selected signal Ref_SEL change or is maintained the accurate position of low logic, makes multiplexer 555 continue high reference voltage REF_H to the second voltage up converting circuit 543 of output, makes high working voltage V
GHBe maintained higher high working voltage V
GH1, promptly in the action of the phase place 3 described in Fig. 8 A.Utilize higher high working voltage V
GH1Come driving grid driving circuit 530, and make after gate driver circuit 530 enablings, after picture frame in 2 times, G
NSignal normally produces, and make the Q ' end of SR latch unit 5510 be the accurate position of high logic, after the pulse of opening beginning signal ST of picture frame 3 is come in, trigger the frequency CLK of D flip-flop 5512 so that voltage selects signal Ref_SEL to switch to the accurate position of high logic, make high working voltage V
GHAutomatically switch to lower high working voltage V
GH2, promptly in the action of the phase place 2 described in Fig. 8 A.
Circuit described in present embodiment adopts the high boost converter of conversion efficiency to replace the low charge pump circuit of conversion efficiency, can significantly reduce the circuit overall power dissipation.When each picture frame opens the beginning, seeing through detection feedback mechanism switches with the dynamic gate high working voltage, can detect in the last picture frame and whether normally not export because of the initial problem of low temperature causes signal, and switch to higher grid high working voltage repairing this gate driver circuit, but and can cooperate transistor component characteristic difference elasticity to adjust needed high working voltage V
GH1, V
GH2
The above only is preferred embodiment of the present invention, and all equalizations of being made according to the present patent application scope of patent protection change and revise, and all should belong to covering scope of the present invention.
Claims (18)
1. a circuit of display driving is characterized in that, comprising:
Time schedule controller opens the beginning signal in order to produce one first;
One gate driver circuit comprises the shift cache unit of a plurality of serial connections, and wherein the shift cache unit of these a plurality of serial connections opens the beginning signal according to one second and a pre-driver signal produces a plurality of signals in regular turn;
One control module is electrically connected on a k shift cache unit of this gate driver circuit, in order to second to open the beginning signal and this k signal that shift cache unit produced produces an output voltage according to this;
One boost converter is electrically connected on this control module, in order to produce a high working voltage according to this output voltage; And
One voltage level shift unit, be electrically connected on this time schedule controller, this boost converter and this gate driver circuit, open the beginning signal to produce this pre-driver signal of driving this gate driver circuit and this second in order to open the beginning signal according to this high working voltage and this first.
2. circuit of display driving as claimed in claim 1 is characterized in that, this control module comprises:
One reference voltage generator is in order to produce the reference voltage of a plurality of different magnitudes of voltage;
One operating voltage commutation circuit is electrically connected on this voltage level shift unit and this k shift cache unit, in order to second to open beginning signal and this k signal that shift cache unit produced and produce voltage selection signal according to this; And
One multiplexer is electrically connected on this operating voltage commutation circuit and this reference voltage generator, selects signal deciding to export one of the reference voltage of these a plurality of different magnitudes of voltage as this output voltage in order to the voltage that produced according to this operating voltage commutation circuit.
3. circuit of display driving as claimed in claim 2 is characterized in that, this operating voltage commutation circuit comprises:
One latch circuit is electrically connected on this voltage level shift unit and this k shift cache unit, in order to second to open beginning signal and this k signal that shift cache unit produced and produce a data-signal according to this; And
One data output circuit is electrically connected on this voltage level shift unit, this latch circuit and this multiplexer, in order to second to open beginning signal and this data-signal and produce this voltage selection signal according to this.
4. circuit of display driving as claimed in claim 1 is characterized in that, this k shift cache unit is one the most last shift cache unit of this gate driver circuit.
5. circuit of display driving as claimed in claim 1 is characterized in that, this boost converter comprises:
One first voltage up converting circuit is in order to promote a power supply signal to produce a boost signal; And
One second voltage up converting circuit is electrically connected on this first voltage up converting circuit and this control module, in order to produce this high working voltage according to this output voltage and this boost signal.
6. circuit of display driving as claimed in claim 1 is characterized in that other comprises a charge pump circuit, is electrically connected on this voltage level shift unit, in order to this voltage level shift unit is imported a low-work voltage.
7. a display drive method is executed in circuit of display driving as claimed in claim 1, it is characterized in that, this method comprises:
Input one is opened beginning signal and a pre-driver signal to this gate driver circuit, makes that a plurality of shift cache units in this gate driver circuit produce a plurality of signals in regular turn;
Import this and open beginning signal and this k signal that shift cache unit produced to this control module;
This control module opens the beginning signal according to this and this k signal that shift cache unit produced produces an output voltage;
This boost converter produces a high working voltage according to this output voltage; And
This voltage level shift unit drives this pre-driver signal of this gate driver circuit with generation according to this high working voltage.
8. method as claimed in claim 7 is characterized in that, this control module opens beginning signal and this k signal that shift cache unit produced according to this and produces this output voltage and comprise:
Produce the reference voltage of a plurality of different magnitudes of voltage;
Open beginning signal and this k signal that shift cache unit produced according to this and produce voltage selection signal; And
According to this voltage select signal deciding export these a plurality of different magnitudes of voltage reference voltage one be this output voltage.
9. method as claimed in claim 8 is characterized in that, opens beginning signal and this k signal that shift cache unit produced according to this and produces this voltage selection signal and comprise:
Open beginning signal and this k signal that shift cache unit produced to produce a data-signal according to this; And
Open beginning signal and this data-signal according to this and export this voltage selection signal.
10. method as claimed in claim 7 is characterized in that, this k shift cache unit is one the most last shift cache unit of this gate driver circuit.
11. method as claimed in claim 7 is characterized in that, this boost converter produces this high working voltage according to this output voltage and comprises:
One power supply signal is provided;
Produce a boost signal according to this power supply signal; And
Produce this high working voltage according to this output voltage and this boost signal.
12. method as claimed in claim 7 is characterized in that, other comprises that input one low-work voltage is to this voltage level shift unit.
13. a LCD is characterized in that, comprises:
One first substrate;
One second substrate;
One liquid crystal layer, this liquid crystal layer is between this first substrate and this second substrate;
One pel array is formed on this first substrate; And
One circuit of display driving comprises:
Time schedule controller opens the beginning signal in order to produce one first;
One gate driver circuit, be formed on this first substrate, and be electrically connected on this pel array, this gate driver circuit comprises the shift cache unit of a plurality of serial connections, and wherein the shift cache unit of these a plurality of serial connections produces a plurality of signals in regular turn according to a pre-driver signal;
One control module is electrically connected on a k shift cache unit of this gate driver circuit, in order to open the beginning signal and this k signal that shift cache unit produced produces an output voltage according to one second;
One boost converter is electrically connected on this control module, in order to produce a high working voltage according to this output voltage; And
One voltage level shift unit, be electrically connected on this time schedule controller, this boost converter and this gate driver circuit, open the beginning signal to produce this pre-driver signal of driving this gate driver circuit and this second in order to open the beginning signal according to this high working voltage and this first.
14. LCD as claimed in claim 13 is characterized in that, this control module comprises:
One reference voltage generator is in order to produce the reference voltage of a plurality of different magnitudes of voltage;
One operating voltage commutation circuit is electrically connected on this voltage level shift unit and this k shift cache unit, in order to second to open the beginning and produce voltage selection signal with this k signal that shift cache unit produced according to this; And
One multiplexer is electrically connected on this operating voltage commutation circuit and this reference voltage generator, is output voltage in order to select one of reference voltage that signal deciding exports these a plurality of different magnitudes of voltage according to voltage that this operating voltage commutation circuit produced.
15. LCD as claimed in claim 14 is characterized in that, this operating voltage commutation circuit comprises:
One latch circuit is electrically connected on this voltage level shift unit and this k shift cache unit, in order to second to open beginning signal and this k signal that shift cache unit produced and produce a data-signal according to this; And
One data output circuit is electrically connected on this voltage level shift unit, this latch circuit and this multiplexer, in order to second to open beginning signal and this data-signal and produce this voltage selection signal according to this.
16. LCD as claimed in claim 13 is characterized in that, this k shift cache unit is one the most last shift cache unit of this gate driver circuit.
17. LCD as claimed in claim 13 is characterized in that, this boost converter comprises:
One first voltage up converting circuit is in order to promote a power supply signal to produce a boost signal; And
One second voltage up converting circuit is electrically connected on this first voltage up converting circuit and this control module, in order to produce this high working voltage according to this output voltage and this boost signal.
18. LCD as claimed in claim 13 is characterized in that, this circuit of display driving comprises a charge pump in addition, is electrically connected on this voltage level shift unit, in order to this voltage level shift unit is imported a low-work voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010527269.7A CN101976551B (en) | 2010-10-19 | 2010-10-19 | Display driving circuit, liquid crystal display and display driving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN102629457A (en) * | 2011-09-26 | 2012-08-08 | 北京京东方光电科技有限公司 | Driving module of liquid crystal display |
| CN105096863A (en) * | 2015-08-05 | 2015-11-25 | 深圳市华星光电技术有限公司 | Liquid crystal display device and grid drive circuit thereof |
| CN105206225A (en) * | 2015-10-12 | 2015-12-30 | 深圳市华星光电技术有限公司 | QLED gate drive circuit structure |
| CN104104066B (en) * | 2013-04-15 | 2017-02-08 | 海洋王（东莞）照明科技有限公司 | Voltage stabilization control circuit for battery reverse connection protection |
| CN106814483A (en) * | 2016-10-14 | 2017-06-09 | 友达光电股份有限公司 | Peep-proof display device |
| CN107240373A (en) * | 2017-08-02 | 2017-10-10 | 京东方科技集团股份有限公司 | Drive signal generation circuit, display device |
| CN110580877A (en) * | 2019-03-28 | 2019-12-17 | 友达光电股份有限公司 | boost circuit, output buffer circuit and display panel |
| CN110634451A (en) * | 2018-06-25 | 2019-12-31 | 矽创电子股份有限公司 | Driving method and driving circuit thereof |
| CN111833792A (en) * | 2019-04-15 | 2020-10-27 | 矽创电子股份有限公司 | Quasi-position converter |
| CN112994436A (en) * | 2021-02-04 | 2021-06-18 | 重庆先进光电显示技术研究院 | Grid opening voltage generation circuit, display panel driving device and display device |
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| CN110634451A (en) * | 2018-06-25 | 2019-12-31 | 矽创电子股份有限公司 | Driving method and driving circuit thereof |
| CN110634451B (en) * | 2018-06-25 | 2023-04-11 | 矽创电子股份有限公司 | Driving method and driving circuit thereof |
| CN110580877A (en) * | 2019-03-28 | 2019-12-17 | 友达光电股份有限公司 | boost circuit, output buffer circuit and display panel |
| CN110580877B (en) * | 2019-03-28 | 2021-05-18 | 友达光电股份有限公司 | Boost circuit, output buffer circuit and display panel |
| CN111833792A (en) * | 2019-04-15 | 2020-10-27 | 矽创电子股份有限公司 | Quasi-position converter |
| CN111833792B (en) * | 2019-04-15 | 2023-08-08 | 矽创电子股份有限公司 | Level converter |
| CN112994436A (en) * | 2021-02-04 | 2021-06-18 | 重庆先进光电显示技术研究院 | Grid opening voltage generation circuit, display panel driving device and display device |
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| CN114187875A (en) * | 2021-11-25 | 2022-03-15 | 绵阳惠科光电科技有限公司 | Voltage adjusting circuit and method and display device |
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