CN101976542A - Pixel driving circuit - Google Patents

Pixel driving circuit Download PDF

Info

Publication number
CN101976542A
CN101976542A CN 201010546148 CN201010546148A CN101976542A CN 101976542 A CN101976542 A CN 101976542A CN 201010546148 CN201010546148 CN 201010546148 CN 201010546148 A CN201010546148 A CN 201010546148A CN 101976542 A CN101976542 A CN 101976542A
Authority
CN
China
Prior art keywords
input end
coupled
port multiplier
output terminal
gray scale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 201010546148
Other languages
Chinese (zh)
Other versions
CN101976542B (en
Inventor
吴孟儒
锺竣帆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Priority to CN2010105461487A priority Critical patent/CN101976542B/en
Publication of CN101976542A publication Critical patent/CN101976542A/en
Application granted granted Critical
Publication of CN101976542B publication Critical patent/CN101976542B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

The invention provides a pixel driving circuit, which comprises a first pixel, a second pixel and a data driving circuit. Each pixel comprises a main region and a sub region, wherein the main region and the sub region store mutually corresponding gray scale voltage when a picture is displayed. In the data driving circuit, a first digital data corresponding to the first pixel and a second digital data corresponding to the second pixel are input to a corresponding digital/analog converter by means of a first selection circuit so as to generate a first gray scale voltage, a second gray scale voltage, a third gray scale voltage and a fourth gray scale voltage; and the gray scale voltages are distributed to the main region and the sub region in the first pixel and the second pixel by means of a second selection circuit. Therefore, the number of the digital/analog converters needed by the data driving circuit can be reduced. The pixel driving circuit can reduce the number of the digital/analog converters needed by the data driving circuit, save the cost and reduce the power consumption.

Description

Pixel-driving circuit
Technical field
The present invention relates to a kind of pixel-driving circuit, more particularly, the present invention relates to a kind of pixel-driving circuit that reduces the number of the required digital analog converter of its data drive circuit.
Background technology
Please refer to Fig. 1.Fig. 1 is for reducing the synoptic diagram of the pixel-driving circuit 100 of colour cast (color washout) in the explanation correlation technique.Pixel-driving circuit 100 comprises a plurality of pixels, data line DL 1～DL M, sweep trace SL 1～SL N, data drive circuit 110 and scan drive circuit 120.The structure of these a plurality of pixels is with pixel PIX 1With PIX 2Illustrate.Pixel PIX 1Comprise transistor Q 1With Q 2, main areas MR 1With subregion SR 1Transistor Q 1Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 1First electrode be coupled to data line DL X, transistor Q 1Second electrode be coupled to main areas MR 1, transistor Q 1Grid be coupled to sweep trace SL YTransistor Q 2Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 2First electrode be coupled to data line DL (X+1), transistor Q 2Second electrode be coupled to subregion SR 1, transistor Q 2Grid be coupled to sweep trace SL YPixel PIX 2Comprise transistor Q 3With Q 4, main areas MR 2With subregion SR 2Transistor Q 3Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 3First electrode be coupled to data line DL (X+2), transistor Q 3Second electrode be coupled to subregion SR 2, transistor Q 3Grid be coupled to sweep trace SL YTransistor Q 4Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 4First electrode be coupled to data line DL (X+3), transistor Q 4Second electrode be coupled to main areas MR 2, transistor Q 4Grid be coupled to sweep trace SL YAs scan drive circuit 120 driven sweep line SL YThe time, transistor Q 1～Q 4Conducting, and make main areas MR 1See through transistor Q 1Be coupled to data line DL X, subregion SR 1See through transistor Q 2Be coupled to data line DL (X+1), subregion SR 2See through transistor Q 3Be coupled to data line DL (X+2), and main areas MR 2See through transistor Q 4Be coupled to data line DL (X+3)Suppose pixel PIX 1Desire shows corresponding to numerical data DA 1Picture, and pixel PIX 2Desire shows corresponding to numerical data DA 2Picture, then this moment at pixel PIX 1In, main areas MR 1With subregion SR 1See through data line D respectively XWith D (X+1)Receive and store from data drive circuit 110 corresponding to numerical data DA 1Gray scale voltage, and at pixel PIX 2In, main areas MR 2With subregion SR 2See through data line D respectively (X+3)With D (X+2)Receive and store from data drive circuit 110 corresponding to numerical data DA 2Gray scale voltage.In addition, main areas MR 1The storage gray scale voltage current potential with subregion SR 1The current potential of the gray scale voltage of storage in correspondence with each other, and main areas MR 2The current potential and the subregion SR of the gray scale voltage of storage 2The current potential of the gray scale voltage of storage also in correspondence with each other, the color offset phenomenon in the time of therefore can decreasing in different visual angles and watch pixel-driving circuit 100.
Yet, because in pixel-driving circuit 100, main areas MR 1With subregion SR 1Store different gray scale voltage, main areas MR 2With subregion SR 2Also store different gray scale voltages, and each zone (MR 1, MR 2, SR 1, SR 2) reversed polarity can be plus or minus, therefore at each data line DL X～DL (X+3), data drive circuit 110 all needs the digital analog converter negative polarity digital analog converter corresponding with of a correspondence, with the gray scale voltage of gray scale voltage that positive polarity is provided or negative polarity to main areas MR 1, MR 2With subregion SR 1, SR 2In other words, when pixel-driving circuit 100 had M bar data line, data drive circuit 110 needed 2M digital analog converter.The circuit area shared owing to digital analog converter is very big, therefore can cause the cost of data drive circuit 110 to rise significantly, in addition, also increases the power consumption of pixel-driving circuit 100, brings the user inconvenience greatly.
Summary of the invention
For overcoming the defective of above-mentioned prior art, the invention provides a kind of pixel-driving circuit.This pixel-driving circuit comprises one first pixel, one second pixel, and a data drive circuit.This first pixel comprises one first main areas and one first subregion.This first main areas is coupled to one first data line and one scan line.This first subregion is coupled to one second data line and this sweep trace.This first main areas and this first subregion are stored the gray scale voltage corresponding to one first numerical data respectively.This second pixel comprises one second main areas and one second subregion.This second subregion is coupled to one the 3rd data line and this sweep trace.This second main areas is coupled to one the 4th data line and this sweep trace.This second main areas and this second subregion are stored the gray scale voltage corresponding to one second numerical data respectively.This data drive circuit comprises one first digital analog converter, one second digital analog converter, one the 3rd digital analog converter, one the 4th digital analog converter, one first selection circuit, and one second selects circuit.This first digital analog converter is used for according to a positive polarity main areas gamma voltage, is one first gray scale voltage with this first numerical data or this second digital data conversion.This second digital analog converter is used for according to a positive polarity subregion gamma voltage, is one second gray scale voltage with this first numerical data or this second digital data conversion.The 3rd digital analog converter is used for according to a negative polarity subregion gamma voltage, is one the 3rd gray scale voltage with this first numerical data or this second digital data conversion.The 4th digital analog converter is used for according to a negative polarity main areas gamma voltage, is one the 4th gray scale voltage with this first numerical data or this second digital data conversion.This first selection circuit is used for selecting a signal and a polar signal according to a gamma voltage, select this first numerical data, input to wherein two digital analog converters of this first digital analog converter, this second digital analog converter, the 3rd digital analog converter and the 4th digital analog converter, and this second numerical data is inputed to two other digital analog converter.This second selection circuit is used for selecting signal and this polar signal that this first gray scale voltage, this second gray scale voltage, the 3rd gray scale voltage and the 4th gray scale voltage are seen through this first data line, this second data line, the 3rd data line, distribute to this first main areas, this first subregion, this second main areas and this second subregion with the 4th data line according to this gamma voltage.
The present invention can reduce the number of the required digital analog converter of data drive circuit, with the cost of saving pixel-driving circuit, and reduces power consumption.
Description of drawings
Fig. 1 is the synoptic diagram of the pixel-driving circuit in the explanation correlation technique.
Fig. 2 is the synoptic diagram of an embodiment of explanation pixel-driving circuit of the present invention.
Fig. 3 is the synoptic diagram of the part-structure of the data drive circuit in the key diagram 2.
Fig. 4 and Fig. 5 utilize the data drive circuit of Fig. 3 to distribute the synoptic diagram of correct gray scale voltage to the pixel of the pixel-driving circuit of Fig. 2 for explanation.
Fig. 6 is the synoptic diagram of another embodiment of explanation pixel-driving circuit of the present invention.
Fig. 7 and Fig. 8 utilize the data drive circuit of Fig. 3 to distribute the synoptic diagram of correct gray scale voltage to the pixel of the pixel-driving circuit of Fig. 6 for explanation.
Fig. 9 is the synoptic diagram of another embodiment of explanation pixel-driving circuit of the present invention.
Figure 10 is the synoptic diagram of the part-structure of the data drive circuit in the key diagram 9.
Wherein, description of reference numerals is as follows:
1,2 electrodes
100,200,600,900 pixel-driving circuits
120,220 gate driver circuits
210,110 data drive circuits
211,212 select circuit
2111 mutual exclusions or grid
2121,2122 polarity selecting circuits
BUF 1～BUF 4Impact damper
The C control end
DA 1, DA 2Numerical data
DAC 1～DAC 4Digital analog converter
DL 1～DL MData line
DH 1～DH 4Fasten the lock device
The G grid
I 1, 1 2Input end
LS 1～LS 4Level translator
MUX 1～MUX 8Port Multiplier
MR 1, MR 2Main areas
O, O 1, O 2Output terminal
PIX 1, PIX 2Pixel
Q 1～Q 4Transistor
S CControl signal
S G_SELGamma voltage is selected signal
S POLPolar signal
SL 1～SL NSweep trace
SR 1, SR 2Subregion
V G1～V G4Gray scale voltage
Embodiment
Please refer to Fig. 2 and Fig. 3.Fig. 2 is the synoptic diagram of an embodiment 200 of explanation pixel-driving circuit of the present invention.Fig. 3 is the synoptic diagram of the part-structure of the data drive circuit 210 in the key diagram 2.Pixel-driving circuit 200 comprises a plurality of pixels, data line DL 1～DL M, sweep trace SL 1～SL N, data drive circuit 210 and scan drive circuit 220.The structure of these a plurality of pixels is with pixel PIX 1With PIX 2Illustrate.Pixel PIX 1Comprise transistor Q 1With Q 2, main areas MR 1With subregion SR 1Transistor Q 1Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 1First electrode be coupled to data line DL X, transistor Q 1Second electrode be coupled to main areas MR 1, transistor Q 1Grid be coupled to sweep trace SL YTransistor Q 2Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 2First electrode be coupled to data line DL (X+1), transistor Q 2Second electrode be coupled to subregion SR 1, transistor Q 2Grid be coupled to sweep trace SL YPixel PIX 2Comprise transistor Q 3With Q 4, main areas MR 2With subregion SR 2Transistor Q 3Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 3First electrode be coupled to data line DL (X+2), transistor Q 3Second electrode be coupled to subregion SR 2, transistor Q 3Grid be coupled to sweep trace SL YTransistor Q 4Comprise first electrode (1), second electrode (2) and grid (G).Transistor Q 4First electrode be coupled to data line DL (X+3), transistor Q 4Second electrode be coupled to main areas MR 2, transistor Q 4Grid be coupled to sweep trace SL YAs scan drive circuit 220 driven sweep line SL YThe time, transistor Q 1～Q 4Conducting, and make main areas MR 1See through transistor Q 1Be coupled to data line DL X, subregion SR 1See through transistor Q 2Be coupled to data line DL (X+1), subregion SR 2See through transistor Q 3Be coupled to data line DL (X+2), and main areas MR 2See through transistor Q 4Be coupled to data line DL (X+3)Suppose pixel PIX 1Desire shows corresponding to numerical data DA 1Picture, and pixel PIX 2Desire shows corresponding to numerical data DA 2Picture, then this moment at pixel PIX 1In, main areas MR 1With subregion SR 1See through data line D respectively XWith D (X+1)Receive and store from data drive circuit 210 corresponding to numerical data DA 1Gray scale voltage, and at pixel PIX 2In, main areas MR 2With subregion SR 2See through data line D respectively (X+3)With D (X+2)Receive and store from data drive circuit 210 corresponding to numerical data DA 2Gray scale voltage, the color offset phenomenon when watching pixel-driving circuit 200 to decrease in different visual angles.
Figure 3 shows that data drive circuit 210 is used for driving data lines DL X～DL (X+3)Structure, the structure that is used for driving other data line as for data drive circuit 210 then can the rest may be inferred.Data drive circuit 210 comprises digital analog converter DAC 1～DAC 4, select circuit 211 and 212, data to fasten to lock device (data latch) DH 1～DH 4, and level translator (level shifter) LS 1～LS 4Select circuit 211 to select signal S according to gamma voltage G_SELWith polar signal S POL, select numerical data DA 1, input to digital analog converter DAC 1～DAC 4Wherein two digital analog converters, and with numerical data DA 2Input to two other digital analog converter.Data are fastened lock device DH 1～DH 4Be used for fastening the numerical data that lock selects circuit 211 to be exported.Level translator LS 1～LS 4Be used for promoting data and fasten lock device DH 1～DH 4The current potential of the numerical data of being exported.Digital analog converter DAC 1According to positive polarity main areas gamma voltage V PA, with level translator LS 1Numerical data (the DA that is exported 1Or DA 2) be converted to gray scale voltage V G1Digital analog converter DAC 2According to positive polarity subregion gamma voltage V PB, level is coupled to Port Multiplier MUX 4Output terminal O.In the present embodiment, as control signal S CDuring presentation logic " 0 ", Port Multiplier MUX 1～MUX 4Input end I 1Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O; As control signal S CDuring presentation logic " 1 ", Port Multiplier MUX 1～MUX 4Input end I 2Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O.
Data are fastened lock device DH 1～DH 4Be respectively coupled to and select circuit 211 and level translator LS 1～LS 4Between, data are fastened lock device DH 1～DH 4Being used for fastening lock respectively selects circuit 211 to input to digital analog converter DAC 1～DAC 4Numerical data.Level translator LS 1～LS 4See through data respectively and fasten lock device DH 1～DH 4Be coupled to and select circuit 211 and digital analog converter DAC 1～DAC 4Between, level translator LS 1～LS 4Be used for respectively promoting and select circuit 211 to input to digital analog converter DAC 1～DAC 4The current potential of numerical data.
Select circuit 212 to comprise Port Multiplier MUX 5～MUX 8, impact damper BUF 1～BUF 4, and polarity selecting circuit 2121 and 2122.Port Multiplier MUX 5Comprise input end I 1Be used for receiving gray scale voltage V G2, input end I 2Be used for receiving gray scale voltage V G1, control end C is used for receiving control signal S C, and output terminal O.Port Multiplier MUX 5According to control signal S CWith Port Multiplier MUX 5Input end I 1Or I 2Be coupled to Port Multiplier MUX 5Output terminal O.Port Multiplier MUX 6Comprise input end I 1Be used for receiving gray scale voltage V G4, input end I 2Be used for receiving gray scale voltage V G3, control end C is used for receiving control signal S C, and output terminal O.Port Multiplier MUX 6According to control signal S CWith Port Multiplier MUX 6Input end I 1Or I 2Be coupled to Port Multiplier MUX 6Output terminal O.Port Multiplier MUX 7Comprise input end I 1Be used for receiving gray scale voltage V G1, input end I 2Be used for receiving gray scale voltage V G2, control end C is used for receiving control signal S C, and output terminal O.Port Multiplier MUX 7According to control signal S CWith Port Multiplier MUX 7Input end I 1Or I 2Be coupled to Port Multiplier MUX 7Output terminal O.Port Multiplier MUX 8Comprise input end I 1Be used for receiving gray scale voltage V G3, input end I 2Be used for receiving gray scale voltage V G4, control end C is used for receiving control signal S C, and output terminal O.Port Multiplier MUX 8According to control signal S CWith Port Multiplier MUX 8Input end I 1Or I 2Be coupled to Port Multiplier MUX 8Output terminal O.As control signal S CDuring presentation logic " 0 ", Port Multiplier MUX 5～MUX 8Input end I 1Be coupled to Port Multiplier MUX respectively 5～MUX 8Output terminal O; As control signal S CDuring presentation logic " 1 ", Port Multiplier MUX 5～MUX 8Input end I 2Be coupled to Port Multiplier MUX respectively 5～MUX 8Output terminal O.
Polarity selecting circuit 2121 comprises input end I 1Be coupled to Port Multiplier MUX 5Output terminal O, input end I 2Be coupled to Port Multiplier MUX 6Output terminal O, output terminal O 1Be coupled to data line DL X, output terminal O 2Be coupled to data line DL (X+1), and control end C is used for receiving polarity signal S POL, polarity switch LS 2Numerical data (the DA that is exported 1Or DA 2) be converted to gray scale voltage V G2Digital analog converter DAC 3According to negative polarity subregion gamma voltage V NB, with level translator LS 3Numerical data (the DA that is exported 1Or DA 2) be converted to gray scale voltage V G3Digital analog converter DAC 4According to negative polarity main areas gamma voltage V NA, with level translator LS 4Numerical data (the DA that is exported 1Or DA 2) be converted to gray scale voltage V G4Select circuit 212 to select signal S according to gamma voltage G_SELWith polar signal S POLWith gray scale voltage V G1～V G4See through data line DL X～DL (X+3)Distribute to main areas MR 1With MR 2And subregion SR 1With SR 2In data drive circuit 210, will be by selection circuit 211 corresponding to pixel PIX 1Numerical data DA 1With corresponding to pixel PIX 2Numerical data DA 2Input to corresponding digital analog converter, to produce gray scale voltage V G1～V G4, and by selecting circuit 212 with gray scale voltage V G1～V G4Distribute to pixel PIX 1With PIX 2In main areas MR 1With MR 2And subregion SR 1With SR 2, so can reduce the number of the required digital analog converter of data drive circuit 210.Below its principle of work will be described further.
Select circuit 211 to comprise mutual exclusion or grid (XOR gate) 2111 and Port Multiplier MUX 1～MUX 4Mutual exclusion or grid 2111 are selected signal S according to gamma voltage G_SELWith polar signal S POL, carry out logical operation, to produce control signal S CWhen gamma voltage is selected signal S G_SELWith polar signal S POLPresentation logics " 0 " or all during presentation logic " 1 " all, control signal S CPresentation logic " 0 "; When gamma voltage is selected signal S G_SELPresentation logic " 0 " and polar signal S POLDuring presentation logic " 1 ", control signal S CPresentation logic " 1 "; When gamma voltage is selected signal S G_SELPresentation logic " 1 " and polar signal S POLDuring presentation logic " 0 ", control signal S CPresentation logic " 1 ".Port Multiplier MUX 1Comprise input end I 1Be used for receiving digital data DA 2, input end I 2Be used for receiving digital data DA 1, and control end C is used for receiving control signal S CPort Multiplier MUX 1According to control signal S CWith Port Multiplier MUX 1Input end I 1Or I 2Be coupled to Port Multiplier MUX 1Output terminal O.Port Multiplier MUX 2Comprise input end I 1Be used for receiving digital data DA 1, input end I 2Be used for receiving digital data DA 2, and control end C is used for receiving control signal S CPort Multiplier MUX 2According to control signal S CWith Port Multiplier MUX 2Input end I 1Or I 2Be coupled to Port Multiplier MUX 2Output terminal O.Port Multiplier MUX 3Comprise input end I 1Be used for receiving digital data DA 2, input end I 2Be used for receiving digital data DA 1, and control end C is used for receiving control signal S CPort Multiplier MUX 3According to control signal S CWith Port Multiplier MUX 3Input end I 1Or I 2Be coupled to Port Multiplier MUX 3Output terminal O.Port Multiplier MUX 4Comprise input end I 1Be used for receiving digital data DA 1, input end I 2Be used for receiving digital data DA 2, and control end C is used for receiving control signal S CPort Multiplier MUX 4According to control signal S CWith Port Multiplier MUX 4Input end I 1Or I 2Select circuit 2121 according to polar signal S POLInput end I with polarity selecting circuit 2121 1With I 2One of them input end be coupled to the output terminal O of polarity selecting circuit 2121 1, and another input end is coupled to the output terminal O of polarity selecting circuit 2121 2 Polarity selecting circuit 2122 comprises input end I 1Be coupled to Port Multiplier MUX 7Output terminal O, input end I 2Be coupled to Port Multiplier MUX 8Output terminal O, output terminal O 1Be coupled to data line DL (X+2), output terminal O 2Be coupled to data line DL (X+3), and control end C is used for receiving polarity signal S POL, polarity selecting circuit 2122 is according to polar signal S POLInput end I with polarity selecting circuit 2122 1With I 2One of them input end be coupled to the output terminal O of polarity selecting circuit 2122 1, and another input end is coupled to the output terminal O of polarity selecting circuit 2122 2As polar signal S POLDuring presentation logic " 0 ", polarity selecting circuit 2121 and 2122 input end I 1Be coupled to its output terminal O respectively 2, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 1As polar signal S POLDuring presentation logic " 1 ", polarity selecting circuit 2121 and 2122 input end I 1Be coupled to its output terminal O respectively 1, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 2
Impact damper BUF 1Be coupled to Port Multiplier MUX 5Output terminal O and the input end I of polarity selecting circuit 2121 1Between, impact damper BUF 1Be used for cushioning Port Multiplier MUX 5The gray scale voltage exported of output terminal O.Impact damper BUF 2Be coupled to Port Multiplier MUX 6Output terminal O and the input end I of polarity selecting circuit 2121 2Between, impact damper BUF 2Be used for cushioning Port Multiplier MUX 6The gray scale voltage exported of output terminal O.Impact damper BUF 3Be coupled to Port Multiplier MUX 7Output terminal O and the input end I of polarity selecting circuit 2122 1Between, impact damper BUF 3Be used for cushioning Port Multiplier MUX 7The gray scale voltage exported of output terminal O.Impact damper BUF 4Be coupled to Port Multiplier MUX 8Output terminal O and the input end I of polarity selecting circuit 2122 2Between, impact damper BUF 4Be used for cushioning Port Multiplier MUX 8The gray scale voltage exported of output terminal O.
Please refer to Fig. 4.Fig. 4 is the main areas MR of explanation in pixel-driving circuit 200 1, subregion SR 1, subregion SR 2And main areas MR 2Reversed polarity when being respectively positive and negative, positive and negative, the synoptic diagram of the operation of data drive circuit 210.At this moment, gamma voltage is selected signal S G_SELPresentation logic " 0 ", and polar signal S POLPresentation logic " 1 " is so the control signal S of mutual exclusion or grid 2111 output presentation logics " 1 " CAs control signal S CDuring presentation logic " 1 ", Port Multiplier MUX 1～MUX 4Input end I 2Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O.So, Port Multiplier MUX 1See through and fasten lock device DH 1With level translator LS 1Output digital data DA 1To digital analog converter DAC 1, Port Multiplier MUX 2See through and fasten lock device DH 2With level translator LS 2Output digital data DA 2To digital analog converter DAC 2, Port Multiplier MUX 3See through and fasten lock device DH 3With level translator LS 3Output digital data DA 1To digital analog converter DAC 3, and Port Multiplier MUX 4See through and fasten lock device DH 4With level translator LS 4Output digital data DA 2To digital analog converter DAC 4Digital analog converter DAC 1According to positive polarity main areas gamma voltage V PA, with numerical data DA 1Be converted to gray scale voltage V G1Digital analog converter DAC 2According to positive polarity subregion gamma voltage V PB, with numerical data DA 2Be converted to gray scale voltage V G2Digital analog converter DAC 3According to negative polarity subregion gamma voltage V NB, with numerical data DA 1Be converted to gray scale voltage V G3Digital analog converter DAC 4According to negative polarity main areas gamma voltage V NA, with numerical data DA 2Be converted to gray scale voltage V G4At this moment, Port Multiplier MUX 5～MUX 8Control signal S according to presentation logic " 1 " C, respectively with MUX 5～MUX 8Input end I 2Be coupled to MUX 5～MUX 8Output terminal O.So, Port Multiplier MUX 5See through impact damper BUF 1Output gray scale voltage V G1Input end I to polarity selecting circuit 2121 1, Port Multiplier MUX 6See through impact damper BUF 2Output gray scale voltage V G3Input end I to polarity selecting circuit 2121 2, Port Multiplier MUX 7See through impact damper BUF 3Output gray scale voltage V G2Input end I to polarity selecting circuit 2122 1, and Port Multiplier MUX 8See through impact damper BUF 4Output gray scale voltage V G4Input end I to polarity selecting circuit 2122 2Because polar signal S POLPresentation logic " 1 ", so the input end I of polarity selecting circuit 2121 and 2122 1Be coupled to its output terminal O respectively 1, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 2So, polarity selecting circuit 2121 sees through data line DL X, will be according to positive polarity main areas gamma voltage V PAConverting digital data DA 1Resulting gray scale voltage V G1Export main areas MR to 1, and polarity selecting circuit 2121 sees through data line DL (X+1), will be according to negative polarity subregion gamma voltage V NBConverting digital data DA 1Resulting gray scale voltage V G3Export subregion SR to 1 Polarity selecting circuit 2122 sees through data line DL (X+2), will be according to positive polarity subregion gamma voltage V PBConverting digital data DA 2Resulting gray scale voltage V G2Export subregion SR to 2, and polarity selecting circuit 2122 sees through data line DL (X+3), will be according to negative polarity main areas gamma voltage V NAConverting digital data DA 2Resulting gray scale voltage V G4Export main areas MR to 2Therefore, in pixel-driving circuit 200, as main areas MR 1, subregion SR 1, subregion SR 2And main areas MR 2Reversed polarity when being respectively positive and negative, positive and negative, select signal S by the gamma voltage of presentation logic " 0 " G_SELPolar signal S with presentation logic " 1 " POL, promptly may command selects circuit 211 with numerical data DA 1With DA 2Input to corresponding digital analog converter, to produce gray scale voltage V G1～V G4, and control selects circuit 212 with gray scale voltage V G1～V G4Correctly distribute gray scale voltage V G1～V G4Give main areas MR 1With MR 2And subregion SR 1With SR 2
Please refer to Fig. 5.Fig. 5 is the main areas MR of explanation in pixel-driving circuit 200 1, subregion SR 1, subregion SR 2And main areas MR 2Reversed polarity when being respectively negative, positive, negative, positive, the synoptic diagram of the operation of data drive circuit 210.At this moment, gamma voltage is selected signal S G_SELPresentation logic " 0 ", and polar signal S POLPresentation logic " 0 " is so the control signal S of mutual exclusion or grid 2111 output presentation logics " 0 " CAs control signal S CDuring presentation logic " 0 ", Port Multiplier MUX 1～MUX 4Input end I 1Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O.So, Port Multiplier MUX 1See through and fasten lock device DH 1With level translator LS 1Output digital data DA 2To digital analog converter DAC 1, Port Multiplier MUX 2See through and fasten lock device DH 2With level translator LS 2Output digital data DA 1To digital analog converter DAC 2, Port Multiplier MUX 3See through and fasten lock device DH 3With level translator LS 3Output digital data DA 2To digital analog converter DAC 3, and Port Multiplier MUX 4See through and fasten lock device DH 4With level translator LS 4Output digital data DA 1To digital analog converter DAC 4Digital analog converter DAC 1According to positive polarity main areas gamma voltage V PA, with numerical data DA 2Be converted to gray scale voltage V G1Digital analog converter DAC 2According to positive polarity subregion gamma voltage V PB, with numerical data DA 1Be converted to gray scale voltage V G2Digital analog converter DAC 3According to negative polarity subregion gamma voltage V NB, with numerical data D A2Be converted to gray scale voltage V G3Digital analog converter DAC 4According to negative polarity main areas gamma voltage V NA, with numerical data DA 1Be converted to gray scale voltage V G4At this moment, Port Multiplier MUX 5～MUX 8Control signal S according to presentation logic " 0 " C, respectively with MUX 5～MUX 8Input end I 1Be coupled to MUX 5～MUX 8Output terminal O.So, Port Multiplier MUX 5See through impact damper BUF 1Output gray scale voltage V G2Input end I to polarity selecting circuit 2121 1, Port Multiplier MUX 6See through impact damper BUF 2Output gray scale voltage V G4Input end I to polarity selecting circuit 2121 2, Port Multiplier MUX 7See through impact damper BUF 3Output gray scale voltage V G1Input end I to polarity selecting circuit 2122 1, and Port Multiplier MUX 8See through impact damper BUF 4Output gray scale voltage V G3Input end I to polarity selecting circuit 2122 2Because polar signal S POLPresentation logic " 0 ", so the input end I of polarity selecting circuit 2121 and 2122 1Be coupled to its output terminal O respectively 2, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 1So, polarity selecting circuit 2121 sees through data line DL X, will be according to negative polarity main areas gamma voltage V NAConverting digital data DA 1Resulting gray scale voltage V G4Export main areas MR to 1, and polarity selecting circuit 2121 sees through data line DL (X+1), will be according to positive polarity subregion gamma voltage V PBConverting digital data DA 1Resulting gray scale voltage V G2Export subregion SR to 1 Polarity selecting circuit 2122 sees through data line DL (X+2), will be according to negative polarity subregion gamma voltage V NBConverting digital data DA 2Resulting gray scale voltage V G3Export subregion SR to 2, and polarity selecting circuit 2122 sees through data line DL (X+3), will be according to positive polarity main areas gamma voltage V PAConverting digital data DA 2Resulting gray scale voltage V G1Export main areas MR to 2Therefore, in pixel-driving circuit 200, as main areas MR 1, subregion SR 1, subregion SR 2And main areas MR 2Reversed polarity when being respectively negative, positive, negative, positive, select signal S by the gamma voltage of presentation logic " 0 " G_SELPolar signal S with presentation logic " 0 " POL, promptly may command selects circuit 211 with numerical data DA 1With DA 2Input to corresponding digital analog converter, to produce gray scale voltage V G1～V G4, and control selects circuit 212 with gray scale voltage V G1～V G4Correctly distribute gray scale voltage V G1～V G4Give main areas MR 1With MR 2And subregion SR 1With SR 2
As shown in the above description, in pixel-driving circuit 200 of the present invention, at data line DL X～DL (X+3), 210 of data drive circuits need four digital analog converter (DAC 1～DAC 4), can provide correct gray scale voltage to main areas MR 1, MR 2With subregion SR 1, SR 2In other words, when pixel-driving circuit 200 had M bar data line, data drive circuit 210 only needed M digital analog converter.Therefore, compared to the pixel-driving circuit 100 of correlation technique, pixel-driving circuit 200 of the present invention can reduce the quantity of required digital analog converter, with the saving cost, and reduces power consumption.
Please refer to Fig. 6.Fig. 6 is the synoptic diagram of another embodiment 600 of explanation pixel-driving circuit of the present invention.Pixel- driving circuit 600 and 200 different being in, transistor Q 1Second end be coupled to subregion SR 1, transistor Q 2Second end be coupled to main areas MR 1, transistor Q 3Second end be coupled to main areas MR 2, transistor Q 4Second end be coupled to subregion SR 2At this moment, utilize data drive circuit 210 still can correctly distribute to main areas MR 1With MR 2And subregion SR 1With SR 2, below its principle of work will be described further.
Please refer to Fig. 7.Fig. 7 is the subregion SR of explanation in pixel-driving circuit 600 1, main areas MR 1, main areas MR 2And subregion SR 2Reversed polarity when being respectively positive and negative, positive and negative, the synoptic diagram of the operation of data drive circuit 210.At this moment, gamma voltage is selected signal S G_SELPresentation logic " 1 ", and polar signal S POLPresentation logic " 1 " is so the control signal S of mutual exclusion or grid 2111 output presentation logics " 0 " CAs control signal S CDuring presentation logic " 0 ", Port Multiplier MUX 1～MUX 4Input end I 1Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O.So, Port Multiplier MUX 1See through and fasten lock device DH 1With level translator LS 1Output digital data DA 2To digital analog converter DAC 1, Port Multiplier MUX 2See through and fasten lock device DH 2With level translator LS 2Output digital data DA 1To digital analog converter DAC 2, Port Multiplier MUX 3See through and fasten lock device DH 3With level translator LS 3Output digital data DA 2To digital analog converter DAC 3, and Port Multiplier MUX 4See through and fasten lock device DH 4With level translator LS 4Output digital data DA 1To digital analog converter DAC 4Digital analog converter DAC 1According to positive polarity main areas gamma voltage V PA, with numerical data DA 2Be converted to gray scale voltage V G1Digital analog converter DAC 2According to positive polarity subregion gamma voltage V PB, with numerical data DA 1Be converted to gray scale voltage V G2Digital analog converter DAC 3According to negative polarity subregion gamma voltage V NB, with numerical data DA 2Be converted to gray scale voltage V G3Digital analog converter DAC 4According to negative polarity main areas gamma voltage V NA, with numerical data DA 1Be converted to gray scale voltage V G4At this moment, Port Multiplier MUX 5～MUX 8Control signal S according to presentation logic " 0 " C, respectively with MUX 5～MUX 8Input end I 1Be coupled to MUX 5～MUX 8Output terminal O.So, Port Multiplier MUX 5See through impact damper BUF 1Output gray scale voltage V G2Input end I to polarity selecting circuit 2121 1, Port Multiplier MUX 6See through impact damper BUF 2Output gray scale voltage V G4Input end I to polarity selecting circuit 2121 2, Port Multiplier MUX 7See through impact damper BUF 3Output gray scale voltage V G1Input end I to polarity selecting circuit 2122 1, and Port Multiplier MUX 8See through impact damper BUF 4Output gray scale voltage V G3Input end I to polarity selecting circuit 2122 2Because polar signal S POLPresentation logic " 1 ", so the input end I of polarity selecting circuit 2121 and 2122 1Be coupled to its output terminal O respectively 1, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 2So, polarity selecting circuit 2121 sees through data line DL X, will be according to positive polarity subregion gamma voltage V PBConverting digital data DA 2Resulting gray scale voltage V G2Export subregion SR to 1, and polarity selecting circuit 2121 sees through data line DL (X+1), will be according to negative polarity main areas gamma voltage V NAConverting digital data DA 1Resulting gray scale voltage V G4Export main areas MR to 1 Polarity selecting circuit 2122 sees through data line DL (X+2), will be according to positive polarity main areas gamma voltage V PAConverting digital data DA 2Resulting gray scale voltage V G1Export main areas MR to 2, and polarity selecting circuit 2122 sees through data line DL (X+3), will be according to negative polarity subregion gamma voltage V NBConverting digital data DA 2Resulting gray scale voltage V G3Export subregion SR to 2Therefore, in pixel-driving circuit 600, group region S R 1, main areas MR 1, main areas MR 2And subregion SR 2Reversed polarity when being respectively positive and negative, positive and negative, select signal S by the gamma voltage of presentation logic " 1 " G_SELPolar signal S with presentation logic " 1 " POL, promptly may command selects circuit 211 with numerical data DA 1With DA 2Input to corresponding digital analog converter, to produce gray scale voltage V G1～V G4, and control selects circuit 212 with gray scale voltage V G1～V G4Correctly distribute gray scale voltage V G1～V G4Give main areas MR 1With MR 2And subregion SR 1With SR 2
Please refer to Fig. 8.Fig. 8 is the subregion SR of explanation in pixel-driving circuit 600 1, main areas MR 1, main areas MR 2And subregion SR 2Reversed polarity when being respectively negative, positive, negative, positive, the synoptic diagram of the operation of data drive circuit 210.At this moment, gamma voltage is selected signal S G_SELPresentation logic " 1 ", and polar signal S POLPresentation logic " 0 " is so the control signal S of mutual exclusion or grid 2111 output presentation logics " 1 " CAs control signal S CDuring presentation logic " 1 ", Port Multiplier MUX 1～MUX 4Input end I 2Be coupled to Port Multiplier MUX respectively 1～MUX 4Output terminal O.So, Port Multiplier MUX 1See through and fasten lock device DH 1With level translator LS 1Output digital data DA 1To digital analog converter DAC 1, Port Multiplier MUX 2See through and fasten lock device DH 2With level translator LS 2Output digital data DA 2To digital analog converter DAC 2, Port Multiplier MUX 3See through and fasten lock device DH 3With level translator LS 3Output digital data DA 1To digital analog converter DAC 3, and Port Multiplier MUX 4See through and fasten lock device DH 4With level translator LS 4Output digital data DA 2To digital analog converter DAC 4Digital analog converter DAC 1According to positive polarity main areas gamma voltage V PA, with numerical data DA 1Be converted to gray scale voltage V G1Digital analog converter DAC 2According to positive polarity subregion gamma voltage V PB, with numerical data DA 2Be converted to gray scale voltage V G2Digital analog converter DAC 3According to negative polarity subregion gamma voltage V NB, with numerical data DA 1Be converted to gray scale voltage V G3Digital analog converter DAC 4According to negative polarity main areas gamma voltage V NA, with numerical data DA 2Be converted to gray scale voltage V G4At this moment, Port Multiplier MUX 5～MUX 8Control signal S according to presentation logic " 1 " C, respectively with MUX 5～MUX 8Input end I 2Be coupled to MUX 5～MUX 8Output terminal O.So, Port Multiplier MUX 5See through impact damper BUF 1Output gray scale voltage V G1Input end I to polarity selecting circuit 2121 1, Port Multiplier MUX 6See through impact damper BUF 2Output gray scale voltage V G3Input end I to polarity selecting circuit 2121 2, Port Multiplier MUX 7See through impact damper BUF 3Output gray scale voltage V G2Input end I to polarity selecting circuit 2122 1, and Port Multiplier MUX 8See through impact damper BUF 4Output gray scale voltage V G4Input end I to polarity selecting circuit 2122 2Because polar signal S POLPresentation logic " 0 ", so the input end I of polarity selecting circuit 2121 and 2122 1Be coupled to its output terminal O respectively 2, and the input end I of polarity selecting circuit 2121 and 2122 2Be coupled to its output terminal O respectively 1So, polarity selecting circuit 2121 sees through data line DL X, will be according to negative polarity subregion gamma voltage V NBConverting digital data DA 1Resulting gray scale voltage V G3Export subregion SR to 1, and polarity selecting circuit 2121 sees through data line DL (X+1), will be according to positive polarity main areas gamma voltage V PAConverting digital data DA 1Resulting gray scale voltage V G1Export main areas MR to 1 Polarity selecting circuit 2122 sees through data line DL (X+2), will be according to negative polarity main areas gamma voltage V NAConverting digital data DA 2Resulting gray scale voltage V G4Export main areas MR to 2, and polarity selecting circuit 2122 sees through data line DL (X+3), will be according to positive polarity subregion gamma voltage V PBConverting digital data DA 2Resulting gray scale voltage V G2Export subregion SR to 2Therefore, the subregion SR in pixel-driving circuit 600 1, main areas MR 1, main areas MR 2And subregion SR 2Reversed polarity when being respectively negative, positive, negative, positive, select signal S by the gamma voltage of presentation logic " 1 " G_SELPolar signal S with presentation logic " 0 " POL, promptly may command selects circuit 211 with numerical data DA 1With DA 2Input to corresponding digital analog converter, to produce gray scale voltage V G1～V G4, and control selects circuit 212 with gray scale voltage V G1～V G4Correctly distribute gray scale voltage V G1～V G4Give main areas MR 1With MR 2And subregion SR 1With SR 2
In like manner, as shown in the above description, in pixel-driving circuit 600 of the present invention, at data line DL X～DL (X+3), 210 of data drive circuits need four digital analog converter (DAC 1～DAC 4), can provide correct gray scale voltage to main areas MR 1, MR 2With subregion SR 1, SR 2In other words, when pixel-driving circuit 600 had M bar data line, data drive circuit 210 only needed M digital analog converter.Therefore, compared to the pixel-driving circuit 100 of correlation technique, pixel-driving circuit 600 of the present invention can reduce the quantity of required digital analog converter, with the saving cost, and reduces power consumption.
In addition, the relation that couples between pixel and the data line is not defined as Fig. 2 or mode shown in Figure 6.For example, please refer to Fig. 9 and Figure 10.Fig. 9 is the synoptic diagram of another embodiment 900 of pixel-driving circuit of the present invention.Figure 10 is the synoptic diagram of part-structure of the data drive circuit 910 of pixel-driving circuit 900.Compared to pixel-driving circuit 200, in pixel-driving circuit 900, main areas MR 1See through transistor Q 1Be coupled to data line DL X, subregion SR 1See through transistor Q 2Be coupled to data line DL (X+1), main areas MR 2See through transistor Q 3Be coupled to data line DL (X+2), and subregion SR 2See through transistor Q 4Be coupled to data line DL (X+3)As shown in figure 10, data drive circuit 910 and 210 different output terminal O that are in polarity selecting circuit 2122 1Be coupled to data line DL (X+3), and the output terminal O of polarity selecting circuit 2122 2Be coupled to data line DL (X+2), thus, no matter be in pixel-driving circuit 200 or 900, the output terminal O of polarity selecting circuit 2122 1All be to be coupled to subregion SR 2, and the output terminal O of polarity selecting circuit 2122 2All be to be coupled to main areas MR 2Therefore by Fig. 4 and the illustrated mode of Fig. 5, data drive circuit 910 can distribute correct gray scale voltage V G1～V G4Give main areas MR 1With MR 2And subregion SR 1With SR 2In other words, in pixel-driving circuit, even the relation of coupling between pixel and the data line changes, as long as the structure of data drive circuit is done corresponding adjustment, data drive circuit can distribute correct gray scale voltage to give the main areas and the subregion of each pixel.
In sum, pixel-driving circuit provided by the present invention comprises one first pixel, one second pixel, and a data drive circuit, each pixel comprises a main areas and a subregion, and this main areas and this subregion are stored gray scale voltage in correspondence with each other when display frame.In this data drive circuit, select circuit to input to corresponding digital analog converter with one second numerical data by one first corresponding to one first numerical data of this first pixel corresponding to this second pixel, producing one first gray scale voltage, one second gray scale voltage, one the 3rd gray scale voltage and one the 4th gray scale voltage, and select circuit that those gray scale voltages are offered main areas and subregion in this first pixel and this second pixel by one second.So can reduce the number of the required digital analog converter of this data drive circuit,, and reduce power consumption with the cost of saving pixel-driving circuit.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (15)

1. pixel-driving circuit comprises:
One first pixel, comprise one first main areas and one first subregion, this first main areas is coupled to one first data line and one scan line, this first subregion is coupled to one second data line and this sweep trace, and this first main areas and this first subregion are stored the gray scale voltage corresponding to one first numerical data respectively;
One second pixel, comprise one second main areas and one second subregion, this second subregion is coupled to one the 3rd data line and this sweep trace, this second main areas is coupled to one the 4th data line and this sweep trace, and this second main areas and this second subregion are stored the gray scale voltage corresponding to one second numerical data respectively; And
One data drive circuit comprises:
One first digital analog converter is used for according to a positive polarity main areas gamma voltage, is one first gray scale voltage with this first numerical data or this second digital data conversion;
One second digital analog converter is used for according to a positive polarity subregion gamma voltage, is one second gray scale voltage with this first numerical data or this second digital data conversion;
One the 3rd digital analog converter is used for according to a negative polarity subregion gamma voltage, is one the 3rd gray scale voltage with this first numerical data or this second digital data conversion;
One the 4th digital analog converter is used for according to a negative polarity main areas gamma voltage, is one the 4th gray scale voltage with this first numerical data or this second digital data conversion;
One first selects circuit, be used for selecting a signal and a polar signal according to a gamma voltage, select this first numerical data, input to wherein two digital analog converters of this first digital analog converter, this second digital analog converter, the 3rd digital analog converter and the 4th digital analog converter, and this second numerical data is inputed to two other digital analog converter; And
One second selects circuit, is used for selecting signal and this polar signal that this first gray scale voltage, this second gray scale voltage, the 3rd gray scale voltage and the 4th gray scale voltage are seen through this first data line, this second data line, the 3rd data line, distribute to this first main areas, this first subregion, this second main areas and this second subregion with the 4th data line according to this gamma voltage.
2. pixel-driving circuit as claimed in claim 1, wherein this data drive circuit also comprises:
One first level translator is coupled between this first selection circuit and this first digital analog converter;
One second level translator is coupled between this first selection circuit and this second digital analog converter;
One the 3rd level translator is coupled between this first selection circuit and the 3rd digital analog converter; And
One the 4th level translator is coupled between this first selection circuit and the 4th digital analog converter.
3. pixel-driving circuit as claimed in claim 2, wherein this data drive circuit also comprises:
One first data are fastened the lock device, are coupled between this first selection circuit and this first level translator;
One second data are fastened the lock device, are coupled between this first selection circuit and this second level translator;
One the 3rd data are fastened the lock device, are coupled between this first selection circuit and the 3rd level translator; And
One the 4th data are fastened the lock device, are coupled between this first selection circuit and the 4th level translator.
4. pixel-driving circuit as claimed in claim 2, wherein when this gamma voltage selects signal and this polar signal all to represent one first predetermined logic or all represent one second predetermined logic, this first selection circuit is exported this second numerical data to this first digital analog converter and the 3rd digital analog converter, and this first selection circuit is exported this first numerical data to this second digital analog converter and the 4th digital analog converter; When this gamma voltage selects this first predetermined logic of signal indication and this polar signal to represent this second predetermined logic, this first selection circuit is exported this first numerical data to this first digital analog converter and the 3rd digital analog converter, and this first selection circuit is exported this second numerical data to this second digital analog converter and the 4th digital analog converter; When this gamma voltage selects this second predetermined logic of signal indication and this polar signal to represent this first predetermined logic, this first selection circuit is exported this first numerical data to this first digital analog converter and the 3rd digital analog converter, and this first selection circuit is exported this second numerical data to this second digital analog converter and the 4th digital analog converter.
5. pixel-driving circuit as claimed in claim 4, wherein this first selection circuit comprises:
One mutual exclusion or grid are used for selecting signal and this polar signal according to this gamma voltage, to produce a control signal;
One first Port Multiplier, comprise a first input end and be used for receiving this second numerical data, one second input end is used for receiving this first numerical data, one control end is used for receiving this control signal, and an output terminal, this first Port Multiplier is used for this output terminal of this first input end or this second input end of this first Port Multiplier being coupled to this first Port Multiplier according to this control signal;
One second Port Multiplier, comprise a first input end and be used for receiving this first numerical data, one second input end is used for receiving this second numerical data, one control end is used for receiving this control signal, and an output terminal, this second Port Multiplier is used for this output terminal of this first input end or this second input end of this second Port Multiplier being coupled to this second Port Multiplier according to this control signal;
One the 3rd Port Multiplier, comprise a first input end and be used for receiving this second numerical data, one second input end is used for receiving this first numerical data, one control end is used for receiving this control signal, and an output terminal, the 3rd Port Multiplier is used for this output terminal of this first input end or this second input end of the 3rd Port Multiplier being coupled to the 3rd Port Multiplier according to this control signal; And
One the 4th Port Multiplier, comprise a first input end and be used for receiving this first numerical data, one second input end is used for receiving this second numerical data, one control end is used for receiving this control signal, and an output terminal, the 4th Port Multiplier is used for this output terminal of this first input end or this second input end of the 4th Port Multiplier being coupled to the 4th Port Multiplier according to this control signal.
6. pixel-driving circuit as claimed in claim 5, wherein when this gamma voltage selected signal and this polar signal all to represent this first predetermined logic or all represent this second predetermined logic, this control signal was represented this first predetermined logic; When this gamma voltage selected this first predetermined logic of signal indication and this polar signal to represent this second predetermined logic, this control signal was represented this second predetermined logic; When this gamma voltage selected this second predetermined logic of signal indication and this polar signal to represent this first predetermined logic, this control signal was represented this second predetermined logic.
7. pixel-driving circuit as claimed in claim 6, wherein when this control signal is represented this first predetermined logic, this first input end of this first Port Multiplier is coupled to this output terminal of this first Port Multiplier, this first input end of this second Port Multiplier is coupled to this output terminal of this second Port Multiplier, this first input end of the 3rd Port Multiplier is coupled to this output terminal of the 3rd Port Multiplier, and this first input end of the 4th Port Multiplier is coupled to this output terminal of the 4th Port Multiplier; When this control signal is represented this second predetermined logic, this second input end of this first Port Multiplier is coupled to this output terminal of this first Port Multiplier, this second input end of this second Port Multiplier is coupled to this output terminal of this second Port Multiplier, this second input end of the 3rd Port Multiplier is coupled to this output terminal of the 3rd Port Multiplier, and this second input end of the 4th Port Multiplier is coupled to this output terminal of the 4th Port Multiplier.
8. pixel-driving circuit as claimed in claim 6, wherein this second selection circuit comprises:
One the 5th Port Multiplier, comprise a first input end and be used for receiving this second gray scale voltage, one second input end is used for receiving this first gray scale voltage, one control end is used for receiving this control signal, and an output terminal, the 5th Port Multiplier is used for this output terminal of this first input end or this second input end of the 5th Port Multiplier being coupled to the 5th Port Multiplier according to this control signal;
One the 6th Port Multiplier, comprise a first input end and be used for receiving the 4th gray scale voltage, one second input end is used for receiving the 3rd gray scale voltage, one control end is used for receiving this control signal, and an output terminal, the 6th Port Multiplier is used for this output terminal of this first input end or this second input end of the 6th Port Multiplier being coupled to the 6th Port Multiplier according to this control signal;
One the 7th Port Multiplier, comprise a first input end and be used for receiving this first gray scale voltage, one second input end is used for receiving this second gray scale voltage, one control end is used for receiving this control signal, and an output terminal, the 7th Port Multiplier is used for this output terminal of this first input end or this second input end of the 7th Port Multiplier being coupled to the 7th Port Multiplier according to this control signal;
One the 8th Port Multiplier, comprise a first input end and be used for receiving the 3rd gray scale voltage, one second input end is used for receiving the 4th gray scale voltage, one control end is used for receiving this control signal, and an output terminal, the 8th Port Multiplier is used for this output terminal of this first input end or this second input end of the 8th Port Multiplier being coupled to the 8th Port Multiplier according to this control signal;
One first polarity selecting circuit, comprise this output terminal that a first input end is coupled to the 5th Port Multiplier, one second input end is coupled to this output terminal of the 6th Port Multiplier, one first output terminal, one second output terminal, and one control end be used for receiving this polar signal, this first polarity selecting circuit is used for according to this polar signal this first input end of this first polarity selecting circuit and one of them input end of this second input end being coupled to this first output terminal of this first polarity selecting circuit, and another input end is coupled to this second output terminal of this first polarity selecting circuit; And
One second polarity selecting circuit, comprise this output terminal that a first input end is coupled to the 7th Port Multiplier, one second input end is coupled to this output terminal of the 8th Port Multiplier, one first output terminal, one second output terminal, and one control end be used for receiving this polar signal, this second polarity selecting circuit is used for according to this polar signal this first input end of this second polarity selecting circuit and one of them input end of this second input end being coupled to this first output terminal of this second polarity selecting circuit, and another input end is coupled to this second output terminal of this second polarity selecting circuit.
9. pixel-driving circuit as claimed in claim 8, wherein when this control signal is represented this first predetermined logic, this first input end of the 5th Port Multiplier is coupled to this output terminal of the 5th Port Multiplier, this first input end of the 6th Port Multiplier is coupled to this output terminal of the 6th Port Multiplier, this first input end of the 7th Port Multiplier is coupled to this output terminal of the 7th Port Multiplier, and this first input end of the 8th Port Multiplier is coupled to this output terminal of the 8th Port Multiplier; When this control signal is represented this second predetermined logic, this second input end of the 5th Port Multiplier is coupled to this output terminal of the 5th Port Multiplier, this second input end of the 6th Port Multiplier is coupled to this output terminal of the 6th Port Multiplier, this second input end of the 7th Port Multiplier is coupled to this output terminal of the 7th Port Multiplier, and this second input end of the 8th Port Multiplier is coupled to this output terminal of the 8th Port Multiplier.
10. pixel-driving circuit as claimed in claim 8, wherein when this polar signal is represented this first predetermined logic, this first input end of this first polarity selecting circuit is coupled to this second output terminal of this first polarity selecting circuit, this second input end of this first polarity selecting circuit is coupled to this first output terminal of this first polarity selecting circuit, this first input end of this second polarity selecting circuit is coupled to this second output terminal of this second polarity selecting circuit, and this second input end of this second polarity selecting circuit is coupled to this first output terminal of this second polarity selecting circuit; When this polar signal is represented this second predetermined logic, this first input end that this second input end that this first input end of this first polarity selecting circuit is coupled to this first output terminal, this first polarity selecting circuit of this first polarity selecting circuit is coupled to this second output terminal of this first polarity selecting circuit, this second polarity selecting circuit is coupled to this first output terminal of this second polarity selecting circuit, and this second input end of this second polarity selecting circuit is coupled to this second output terminal of this second polarity selecting circuit.
11. pixel-driving circuit as claimed in claim 8, wherein this second selection circuit also comprises:
One first impact damper is coupled between this first input end of this output terminal of the 5th Port Multiplier and this first polarity selecting circuit, and this first impact damper is used for cushioning the gray scale voltage that this output terminal of the 5th Port Multiplier is exported;
One second impact damper is coupled between this second input end of this output terminal of the 6th Port Multiplier and this first polarity selecting circuit, and this second impact damper is used for cushioning the gray scale voltage that this output terminal of the 6th Port Multiplier is exported;
One the 3rd impact damper is coupled between this first input end of this output terminal of the 7th Port Multiplier and this second polarity selecting circuit, and the 3rd impact damper is used for cushioning the gray scale voltage that this output terminal of the 7th Port Multiplier is exported; And
One the 4th impact damper is coupled between this second input end of this output terminal of the 8th Port Multiplier and this second polarity selecting circuit, and the 4th impact damper is used for cushioning the gray scale voltage that this output terminal of the 8th Port Multiplier is exported.
12. pixel-driving circuit as claimed in claim 8, wherein this first output terminal of this first polarity selecting circuit is coupled to this first data line, this second output terminal of this first polarity selecting circuit is coupled to this second data line, this first output terminal of this second polarity selecting circuit is coupled to the 3rd data line, and this second output terminal of this second polarity selecting circuit is coupled to the 4th data line.
13. pixel-driving circuit as claimed in claim 12, wherein when this gamma voltage selects this first predetermined logic of signal indication and this polar signal to represent this second predetermined logic, this second select circuit see through this first data line provide this first gray scale voltage to this first main areas, see through this second data line provide the 3rd gray scale voltage to this first subregion, see through the 3rd data line and provide this second gray scale voltage to this second subregion, and see through the 4th data line and provide the 4th gray scale voltage to this second main areas; When this gamma voltage selects signal and this polar signal all to represent this first predetermined logic, this second select circuit see through this first data line provide the 4th gray scale voltage to this first main areas, see through this second data line provide this second gray scale voltage to this first subregion, see through the 3rd data line and provide the 3rd gray scale voltage to this second subregion, and cross the 4th data line and provide this first gray scale voltage to this second main areas.
14. pixel-driving circuit as claimed in claim 8, wherein this first output terminal of this first polarity selecting circuit is coupled to this second data line, this second output terminal of this first polarity selecting circuit is coupled to this first data line, this first output terminal of this second polarity selecting circuit is coupled to the 4th data line, and this second output terminal of this second polarity selecting circuit is coupled to the 3rd data line.
15. pixel-driving circuit as claimed in claim 14, wherein when this gamma voltage selects signal and this polar signal all to represent this second predetermined logic, this second select circuit see through this first data line provide the 4th gray scale voltage to this first main areas, see through this second data line provide this second gray scale voltage to this first subregion, see through the 3rd data line and provide the 3rd gray scale voltage to this second subregion, and cross the 4th data line and provide this first gray scale voltage to this second main areas; When this gamma voltage selects this second predetermined logic of signal indication and this polar signal to represent this first predetermined logic, this second select circuit see through this first data line provide this first gray scale voltage to this first main areas, see through this second data line provide the 3rd gray scale voltage to this first subregion, see through the 3rd data line and provide this second gray scale voltage to this second subregion, and cross the 4th data line and provide the 4th gray scale voltage to this second main areas.
CN2010105461487A 2010-11-10 2010-11-10 Pixel driving circuit Active CN101976542B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2010105461487A CN101976542B (en) 2010-11-10 2010-11-10 Pixel driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2010105461487A CN101976542B (en) 2010-11-10 2010-11-10 Pixel driving circuit

Publications (2)

Publication Number Publication Date
CN101976542A true CN101976542A (en) 2011-02-16
CN101976542B CN101976542B (en) 2012-07-04

Family

ID=43576424

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010105461487A Active CN101976542B (en) 2010-11-10 2010-11-10 Pixel driving circuit

Country Status (1)

Country Link
CN (1) CN101976542B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157254A (en) * 2014-08-18 2014-11-19 深圳市华星光电技术有限公司 Gamma voltage generating module and liquid crystal panel
CN104347047A (en) * 2014-11-11 2015-02-11 深圳市华星光电技术有限公司 Array substrate, display equipment and driving method thereof
CN104952408A (en) * 2015-07-06 2015-09-30 深圳市华星光电技术有限公司 Source electrode drive module and liquid crystal panel
CN105099456A (en) * 2014-05-08 2015-11-25 旭曜科技股份有限公司 Decoding voltage conversion device and digital analog converter employing same
CN112150959A (en) * 2019-06-26 2020-12-29 联咏科技股份有限公司 Data driver for driving display panel and driving method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10319924A (en) * 1997-05-17 1998-12-04 Lg Electron Inc Liquid crystal display panel driving circuit of digital system
CN1388706A (en) * 2001-05-29 2003-01-01 三洋电机株式会社 Display and its controlling circuit
US20040257328A1 (en) * 2003-06-23 2004-12-23 Lim Kyoung Moon Data drive IC of liquid crystal display and driving method thereof
CN1901021A (en) * 2005-07-20 2007-01-24 三星电子株式会社 Driving apparatus for display device
CN101458914A (en) * 2009-01-09 2009-06-17 友达光电股份有限公司 Panel driving apparatus and method, and liquid crystal display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10319924A (en) * 1997-05-17 1998-12-04 Lg Electron Inc Liquid crystal display panel driving circuit of digital system
CN1388706A (en) * 2001-05-29 2003-01-01 三洋电机株式会社 Display and its controlling circuit
US20040257328A1 (en) * 2003-06-23 2004-12-23 Lim Kyoung Moon Data drive IC of liquid crystal display and driving method thereof
CN1901021A (en) * 2005-07-20 2007-01-24 三星电子株式会社 Driving apparatus for display device
CN101458914A (en) * 2009-01-09 2009-06-17 友达光电股份有限公司 Panel driving apparatus and method, and liquid crystal display

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105099456B (en) * 2014-05-08 2018-12-25 敦泰电子股份有限公司 Decoding turns pressure device and the application decoding turns the digital analog converter of pressure device
CN105099456A (en) * 2014-05-08 2015-11-25 旭曜科技股份有限公司 Decoding voltage conversion device and digital analog converter employing same
WO2016026149A1 (en) * 2014-08-18 2016-02-25 深圳市华星光电技术有限公司 Gamma voltage generating module and liquid crystal panel
GB2542529A (en) * 2014-08-18 2017-03-22 Shenzhen China Star Optoelect Gamma voltage generating module and liquid crystal panel
RU2667383C2 (en) * 2014-08-18 2018-09-19 Шэньчжэнь Чайна Стар Оптоэлектроникс Текнолоджи Ко., Лтд. Gamma-voltage generation module and liquid crystalline panel
CN104157254A (en) * 2014-08-18 2014-11-19 深圳市华星光电技术有限公司 Gamma voltage generating module and liquid crystal panel
GB2542529B (en) * 2014-08-18 2020-07-01 Shenzhen China Star Optoelect Gamma voltage generating module and liquid crystal panel
CN104347047A (en) * 2014-11-11 2015-02-11 深圳市华星光电技术有限公司 Array substrate, display equipment and driving method thereof
CN104347047B (en) * 2014-11-11 2016-09-07 深圳市华星光电技术有限公司 Array base palte, display device and driving method thereof
CN104952408A (en) * 2015-07-06 2015-09-30 深圳市华星光电技术有限公司 Source electrode drive module and liquid crystal panel
CN104952408B (en) * 2015-07-06 2018-11-23 深圳市华星光电技术有限公司 Source drive module and liquid crystal display panel
CN112150959A (en) * 2019-06-26 2020-12-29 联咏科技股份有限公司 Data driver for driving display panel and driving method
CN112150959B (en) * 2019-06-26 2024-05-28 联咏科技股份有限公司 Data driver for driving display panel and driving method

Also Published As

Publication number Publication date
CN101976542B (en) 2012-07-04

Similar Documents

Publication Publication Date Title
KR102115530B1 (en) Display device and driving method thereof
KR100613325B1 (en) Driving apparatus and display module
US7961167B2 (en) Display device having first and second vertical drive circuits
CN1877405B (en) Liquid crystal displaying apparatus using data line driving circuit
US20080170057A1 (en) Data driver device and display device for reducing power consumption in a charge-share operation
CN101174398A (en) Driving method of liquid crystal display apparatus and driving circuit of the same
CN101976542B (en) Pixel driving circuit
JP2008292837A (en) Display device
KR20080082897A (en) Display driver
KR102054409B1 (en) Source drive circuit and liquid crystal display panel
CN102955310B (en) Pixel driving structure, driving method and display device
US8872865B2 (en) Pixel-driving circuit
CN101123075B (en) Display apparatus drive device and driving method
KR20120085076A (en) Data processing method, data driving circuit and display device including the same
CN104715729B (en) Source electrode drive circuit
US8736531B2 (en) Driving device for liquid crystal display panel
JP2007288787A (en) Digital-to-analog converter and driving method of display device
KR102166897B1 (en) Display device and driving method thereof
US20080198126A1 (en) Display Apparatus and Display Drive Circuit
CN100552763C (en) Driving circuit and display of organic electroluminescence thereof
CN103578432B (en) Electric power selection apparatus, source electrode driver and How It Works thereof
CN102208174B (en) Voltage level selection circuit and data driver
CN115101019B (en) Source electrode driving circuit and method and display panel
CN102646400A (en) Display driving circuit, driving method and liquid crystal display device
CN102622952B (en) Pixel driver with electronic element sharing structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant