CN101963652A - Method and device for generating interfering noise and method and system for testing voltage tolerance - Google Patents
Method and device for generating interfering noise and method and system for testing voltage tolerance Download PDFInfo
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Abstract
The invention provides method and device for generating interfering noise and method and system for testing voltage tolerance. The method for generating interfering noise comprises the following steps of: generating at least one path of signals according to work frequency of a circuit to be tested; summing the generated at least one path of signals; and amplifying the summed signals to obtain interfering noise, wherein the voltage value of the interfering noise is equal to a design value of the voltage tolerance of the circuit to be tested. The device for generating interfering noise comprises a signal generating module, a summing device and an amplifier. The invention can generate interfering noise which is suitable for testing the voltage tolerance and can test whether the actual voltage tolerance of the circuit conforms to a design requirement.
Description
Technical field
The embodiment of the invention relates to the communication technology, relates in particular to the method and apparatus of generation interference noise and the method and system of test voltage tolerance limit.
Background technology
Electronic product always is subjected to various interference of noise in real work, such as, be subjected to noise from power supply, telecommunications mouth, space radiation, static etc.Noise causes the operation irregularity of product possibly, makes product problems such as data packet loss occur, even crashes.
In order to improve the antijamming capability of electronic product, for design of electronic products voltage tolerant.In digital circuit, voltage tolerant has 2 kinds, i.e. high level voltage tolerance limit and low level voltage tolerance limit.Referring to Fig. 1, high level voltage tolerance limit=VOH min-VIH min, low level voltage tolerance limit=VIL max-VOL max, wherein, VOH min is the minimum value of the high level of drive side output signal, VIH min is the minimum value of the high level of receiving end input signal, and VIL max is the low level maximal value of receiving end input signal, and VOL max is the low level maximal value of drive side output signal.Referring to Fig. 1, even because noise, make the high level of signal of electronic product reduce or low level raises, as long as in high level voltage tolerance limit and low level voltage marginal range, just can guarantee the correct reception of receiving end to signal.
As seen, voltage tolerant makes electronic product can tolerate the noise in transmission and the receiving course to a certain extent for various undesirable factors provide a buffer zone, occupies important effect in the design of product noise budget.Yet the virtual voltage tolerance limit of electronic product is may be owing to board design mistake etc. former thereby cause the virtual voltage tolerance limit not meet designing requirement, such as, voltage tolerant dwindles.Therefore,, need the voltage tolerant of test products, thereby determine whether the virtual voltage tolerance limit adheres to specification, and then whether the antijamming capability of definite electronic product meets the requirements for electronic product.
In the prior art, the method of the voltage tolerant of test products comprises: the noise such as surge, static, power frequency magnetic field that form arbitrary form by jamming equipment, the electronic product complete machine is carried out interference noise to be detected, judge that electronic product whether can operate as normal, if can, the virtual voltage tolerance limit that this electronic product then is described adheres to specification, otherwise, illustrate that the virtual voltage tolerance limit of this electronic product does not meet designing requirement.
By above description as can be seen, prior art is at random to produce interference noise when generation is used for the interference noise of test voltage tolerance limit, and do not consider the characteristics of voltage tolerant, use this kind interference noise that electronic product is disturbed, whether the virtual voltage tolerance limit that then can not detect electronic product exactly adheres to specification, thereby can't accurately estimate the antijamming capability of product.
And, comprise all multicircuits in the electronic product, adopt the way of prior art test electronic product complete machine, can only obtain the designing requirement whether the electronic product complete machine meets voltage tolerant, and whether the virtual voltage tolerance limit that can't obtain some physical circuits in the electronic product meets the designing requirement of voltage tolerant, thereby can't find out the circuit that voltage tolerant does not meet designing requirement, greatly reduce testing efficiency, can't satisfy diversified testing requirement.
Summary of the invention
The embodiment of the invention provides the method and apparatus that produces interference noise, so that produce the interference noise that is applicable to the test voltage tolerance limit.
The embodiment of the invention also provides the method and system of test voltage tolerance limit, and whether virtual voltage tolerance limit that can test circuit adheres to specification.
The method of the generation interference noise that the embodiment of the invention provides comprises:
Frequency of operation according to circuit under test produces at least one road signal;
With at least one road signal plus that produces;
Signal after the addition is amplified, obtain interference noise, the magnitude of voltage of this interference noise equals the design load of the voltage tolerant of described circuit under test.
Described frequency of operation according to circuit under test produces at least one road signal and comprises:
According to the frequency of operation of described circuit under test, produce the signal of the each harmonic of at least one road work first-harmonic.
The signal of the each harmonic of at least one road work of described generation first-harmonic comprises:
Produce the signal of the first harmonic of one tunnel work first-harmonic; Perhaps,
Produce the signal of the third harmonic of the second harmonic of three tunnel first harmonics that are respectively the work first-harmonic, work first-harmonic and work first-harmonic; Perhaps,
Produce the signal of the quintuple harmonics of the four-time harmonic of third harmonic, work first-harmonic of second harmonic, the work first-harmonic of five tunnel first harmonics that are respectively the work first-harmonic, work first-harmonic and work first-harmonic.
The signal expression of the each harmonic of described work first-harmonic is: F (xn)=an*sin (m*2* π * f*t), wherein, the n road signal of xn for producing, an is the attenuation coefficient of the n road signal of generation, m is an overtone order, and m and n are natural number, and an is the arbitrary value between 0～1, f is the frequency of operation of described circuit under test, and t is a time parameter.
Described voltage tolerant comprises high level voltage tolerance limit and low level voltage tolerance limit;
Described signal after the addition is amplified comprises: with the voltage of signals value of the smaller in the design load of the design load of described high level voltage tolerance limit and described low level voltage tolerance limit after divided by described addition, obtain enlargement factor; Amplify according to the signal of described enlargement factor after described addition.
After obtaining described interference noise, further comprise: described interference noise is carried out high pass and isolation processing.
The device of the generation interference noise that the embodiment of the invention provides comprises:
Signal generator module is used for producing at least one road signal according to the frequency of operation of circuit under test;
Summitor is used at least one road signal plus that will produce;
Amplifier is used for the signal after the addition is amplified, and obtains interference noise and output, and the magnitude of voltage of described interference noise equals the design load of the voltage tolerant of described circuit under test.
Described signal generator module comprises at least one road signal source, and each road signal source produces the signal of the each harmonic of work first-harmonic respectively according to the frequency of operation of described circuit under test.
Described signal generator module further comprises each signal attenuator that is connected to after each road signal source;
The signal expression that every signal source on the way produces is: F (xn)=sin (m*2* π * f*t), wherein, the n road signal of xn for producing, m is an overtone order, and m and n are natural number, and an is the arbitrary value between 0～1, f is the frequency of operation of described circuit under test, and t is a time parameter;
The signal attenuator that every signal source on the way connects, the signal that the received signal source produces and exports, this signal times is exported to described summitor after with attenuation coefficient, the expression formula of the signal of signal attenuator output is F (xn)=an*sin (m*2* π * f*t), wherein, an is the arbitrary value between 0～1 for the attenuation coefficient of the n road signal of generation.
Described amplifier comprises the processing and amplifying module, with the voltage of signals value of the smaller in the design load of the design load of the high level voltage tolerance limit of described circuit under test and low level voltage tolerance limit after divided by described addition, obtains enlargement factor; Amplify according to the signal of described enlargement factor after described addition.
This device further comprises: high pass and isolation module are used for the interference noise of described amplifier output is carried out high pass and isolation processing.
The method of the test voltage tolerance limit that the embodiment of the invention provides comprises that any one method that produces interference noise of utilizing the embodiment of the invention to provide obtains interference noise;
The interference noise that obtains is applied in the circuit under test;
Whether the electronic equipment by judging described circuit under test place operate as normal, judges whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
The system of the test voltage tolerance limit that the embodiment of the invention provides, any one that comprises that the embodiment of the invention provides produces device, electronic equipment and the pick-up unit of interference noise, wherein,
Described electronic equipment is used for receiving interference noise on the circuit under test of inside;
Described pick-up unit is used for judging by judging whether operate as normal of described electronic equipment whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
The method and apparatus of the generation interference noise that the embodiment of the invention proposes and the method and system of test voltage tolerance limit, not at random to produce interference noise, but produce the interference noise that magnitude of voltage equals the voltage tolerant design load of circuit under test, that is to say, the interference noise that produces should be the maximum interference noise that the circuit under test of electronic product can be born, and, noise signal is to produce according to the frequency of operation of circuit under test, easier formation is disturbed to circuit under test, therefore, the interference noise that the present invention produces is highly suitable for the test voltage tolerance limit, use this kind interference noise that electronic product is disturbed, whether the virtual voltage tolerance limit that then can detect the circuit of electronic product exactly adheres to specification, thereby can accurately estimate the antijamming capability of product.
And, the method and system of the test voltage tolerance limit that the embodiment of the invention proposes is not that the electronic product complete machine is tested, but test at concrete circuit in the electronic product, like this, whether the virtual voltage tolerance limit that can obtain a concrete circuit meets the designing requirement of this circuit voltage tolerance limit, thereby can accurately find out the circuit that virtual voltage tolerance limit in the electronic product does not meet designing requirement, improve testing efficiency greatly, satisfy diversified testing requirement.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the synoptic diagram of high level voltage tolerance limit and low level voltage tolerance limit;
Fig. 2 is the basic flow sheet that produces interference noise in the embodiment of the invention;
Fig. 3 is the process flow diagram that produces interference noise in a preferred embodiment of the invention;
Fig. 4 is the basic structure synoptic diagram that produces the device of interference noise in the embodiment of the invention;
Fig. 5 is a kind of preferred structure synoptic diagram that produces the device of interference noise in the one embodiment of the invention;
Fig. 6 is the structural representation of the system of test voltage tolerance limit in the embodiment of the invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The embodiment of the invention has proposed a kind of method that produces interference noise, and referring to Fig. 2, this method comprises:
Step 201: the frequency of operation according to circuit under test produces at least one road signal.
Step 202: at least one road signal plus that will produce.
Step 203: the signal after the addition is amplified, obtain interference noise, the magnitude of voltage of this interference noise equals the design load of the voltage tolerant of described circuit under test.
As seen, the method of the generation interference noise that the embodiment of the invention proposes is not at random to produce interference noise, but produce the interference noise that magnitude of voltage equals the voltage tolerant design load of circuit under test, that is to say, the interference noise that produces should be the maximum interference noise that the circuit under test of electronic product can be born, and, noise signal is to produce according to the frequency of operation of circuit under test, easier formation is disturbed to circuit under test, therefore, the interference noise that the present invention produces is highly suitable for the test voltage tolerance limit, use this kind interference noise that electronic product is disturbed, whether the virtual voltage tolerance limit that then can detect the circuit of electronic product exactly adheres to specification, thereby can accurately estimate the antijamming capability of product.
Fig. 3 is the process flow diagram that produces interference noise in a preferred embodiment of the invention.Referring to Fig. 3, in a preferred embodiment of the invention, be example with MII interface circuit in the test ethernet device, the process that produces interference noise at this circuit under test comprises:
Step 301: the parameter of input circuit under test comprises: frequency of operation f, VOH min, VIH min, VIL max and VOL max.
The input parameters is for the ease of the parameter characteristic according to this MII interface circuit in this step, produces the interference noise that is applicable to this MII interface circuit in subsequent process.
Usually, the frequency of operation f of MII interface circuit is 25MHz.A kind of VOHmin of MII interface circuit, VIH min, VIL max and VOL max parameter can be referring to shown in the following tables 1.
| Project | Unit: V |
| VIH?min | ?2 |
| VIL?max | 0.8 |
| VOH?min | 2.8 |
| VOL?max | 0.4 |
Table 1
Can obtain the design load of high level voltage tolerance limit=VOH min-VIHmin=0.8V, the design load of low level voltage tolerance limit=VIL max-VOL max=0.4V according to above-mentioned table 1.
Step 302: the frequency of operation f according to circuit under test produces at least one road signal.
In the present embodiment, at least one road signal can be one the tunnel or any a few road (such as arbitrarily even number road or odd number road arbitrarily) signal.
In practice, circuit be subjected to having its work first-harmonic easilier, and the interference of noise that is combined into of the each harmonic of first-harmonic.This interference noise has the time enough width, and on the circuit signal of the operate as normal that is easy to be added to, therefore, in the step 302 of the embodiment of the invention, can produce the signal of the each harmonic of at least one road work first-harmonic according to the frequency of operation f of circuit under test.
Preferably, because easier circuit under test is produced of the noise that the signal on odd number road is formed by stacking disturbed, therefore, in this step, the signal that produces the each harmonic of at least one road work first-harmonic can include but not limited to following mode:
Mode one, produce the signal of the first harmonic of one tunnel work first-harmonic, promptly only produce the signal of one tunnel work first-harmonic;
Mode two, generation three tunnel are respectively the signal of the third harmonic of the first harmonic of work first-harmonic, the second harmonic of work first-harmonic and the first-harmonic of working;
Mode three, generation five tunnel are respectively the signal of the quintuple harmonics of the first harmonic of work first-harmonic, the second harmonic of work first-harmonic, the third harmonic of work first-harmonic, the four-time harmonic of work first-harmonic and the first-harmonic of working.
In this step, the signal expression of the each harmonic of work first-harmonic is: F (xn)=an*sin (m*2* π * f*t), wherein, the n road signal of xn for producing, an is the attenuation coefficient of the n road signal of generation, m is an overtone order, m and n are natural number, an is the arbitrary value between 0～1, and f is the frequency of operation of described circuit under test, and t is a time parameter.
In this step, can control each road voltage of signals intensity level, even can be 0 to control the generation several signals by the value that attenuation coefficient an is set by the attenuation coefficient an that controls each road signal.Such as, one has five tunnel signal sources, need to produce three road signals, so, the attenuation coefficient a4 of the 4 road and the 5 road signal and attenuation coefficient a1, a2 and a3 that a5 is 0, the 1,2 and 3 road signals can be set be respectively 1.Like this, just can produce the signal of the each harmonic of three tunnel work first-harmonics, its expression formula is respectively:
First harmonic first-harmonic: F (the x1)=sin (2* π * f*t) that promptly works of work first-harmonic;
The second harmonic of work first-harmonic: F (x2)=sin (2*2* π * f*t);
The third harmonic of work first-harmonic: F (x3)=sin (2*2* π * f*t).
Step 303: each road signal plus that will produce.
Step 304:, determine the enlargement factor A of signal according to the parameter of circuit under test.
Here, the enlargement factor A of signal is relevant with the magnitude of voltage of the interference noise of ultimate demand generation.For the interference noise that guarantees to produce can be used to simultaneously check whether the high level voltage tolerance limit of circuit under test and low level voltage tolerance limit adhere to specification, can make the magnitude of voltage U0 of the interference noise that ultimate demand produces equal smaller in the design load of the design load of high level voltage tolerance limit and low level voltage tolerance limit.Table 1 according to step 301 place can obtain U0=0.4V.
Enlargement factor A is: each the road voltage of signals value after divided by addition of the smaller U0 in the design load of the design load of high level voltage tolerance limit and low level voltage tolerance limit.
Step 305: the signal after utilizing enlargement factor A to addition amplifies and exports, and obtains interference noise.
Because enlargement factor A is smaller U0 in the design load of the design load of high level voltage tolerance limit and low level voltage tolerance limit each road voltage of signals value after divided by addition, therefore, the magnitude of voltage of the interference noise that obtains in this step equals the smaller in the design load of the design load of high level voltage tolerance limit and low level voltage tolerance limit.
Step 306: interference noise is carried out high pass and isolation processing.
Here, because desirable interference noise should be high frequency and AC signal, therefore, can handle low-frequency component in the filtering interfering noise by the high pass of this step, and come flip-flop in the filtering interfering noise, thereby more be applicable to the interference noise of test circuit voltage tolerant by the isolation processing of this step.
So far, then finished the process that produces interference noise in the embodiment of the invention.
In addition, need to prove, it is a kind of preferred implementation procedure that the present invention produces the interference noise method that above-mentioned all flow processs based on Fig. 3 are described, produce in the actual realization of interference noise method in the present invention, can on the basis of flow process shown in Figure 2, be out of shape arbitrarily as required, can be to select the arbitrary steps among Fig. 3 to realize, the sequencing of each step also can be adjusted etc. as required.Such as, in a kind of actual realization, the process of execution in step 306 not; For another example, in another kind of actual realization of the inventive method, when step 304 is determined enlargement factor A, can choose at random in the design load of the design load of high level voltage tolerance limit and low level voltage tolerance limit any one and needing be used as the magnitude of voltage U0 of the interference noise that produces, rather than select both smallers.
The embodiment of the invention has also proposed a kind of device that produces interference noise, and referring to Fig. 4, this device comprises:
Referring to Fig. 5, in one embodiment of the invention, signal generator module 401 comprises the signal source 501 at least one road, and each road signal source 501 produces the signal of the each harmonic of work first-harmonic respectively according to the frequency of operation of described circuit under test.
In another embodiment of the present invention, signal generator module 401 further comprises each signal attenuator 502 that is connected to after each road signal source 501;
The signal expression that every signal source on the way 501 produces is: F (xn)=sin (m*2* π * f*t), wherein, the n road signal of xn for producing, m is an overtone order, and m and n are natural number, and an is the arbitrary value between 0～1, f is the frequency of operation of described circuit under test, and t is a time parameter;
The signal attenuator 502 that every signal source on the way 501 connects, the signal that received signal source 501 produces and exports, this signal times is exported to described summitor 402 after with attenuation coefficient, the expression formula of the signal of signal attenuator 502 outputs is F (xn)=an*sin (m*2* π * f*t), wherein, an is the arbitrary value between 0～1 for the attenuation coefficient of the n road signal of generation.
At another embodiment of the present invention, amplifier 403 comprises processing and amplifying module 503, the voltage of signals value of smaller in the design load of the high level voltage tolerance limit of the described circuit under test of processing and amplifying module 503 usefulness and the design load of low level voltage tolerance limit after divided by described addition obtains enlargement factor; Amplify according to the signal of described enlargement factor after the addition of summitor 402 output.
In another embodiment of the present invention, the device that produces interference noise may further include: high pass and isolation module 504 are used for the interference noise of described amplifier 403 outputs is carried out high pass and isolation processing.
Need to prove that the structure of each embodiment of the device of above-mentioned generation interference noise shown in Figure 5 can be carried out combination in any and be used.Such as, include only the signal source 501 at least one road in the signal generator module 401, and do not comprise signal attenuator 502; For another example, do not comprise high pass and isolation module 504 in the device of generation interference noise, and comprise other all structures shown in Figure 5.
In addition, the embodiment of the invention has also proposed a kind of method of test voltage tolerance limit, and any one method that produces interference noise that can at first adopt the embodiment of the invention to propose obtains interference noise; Then, the interference noise that obtains is applied in the circuit under test of electronic equipment; By judging whether operate as normal of this electronic equipment, judge whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
In addition, the embodiment of the invention has also proposed a kind of system of test voltage tolerance limit, referring to Fig. 6, comprising: device 601, electronic equipment 602 and the pick-up unit 603 of any one generation interference noise that the embodiment of the invention proposes, wherein,
Described electronic equipment 602 is used for receiving the interference noise of device 601 outputs that produce interference noise on the circuit under test of inside;
Described pick-up unit 603 is used for judging by judging whether operate as normal of described electronic equipment 602 whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
In the method and system of the test voltage tolerance limit that the embodiment of the invention proposes, by judge electronic equipment whether operate as normal judge whether the virtual voltage tolerance limit of described circuit under test meets the specific implementation method of the design load of voltage tolerant can be with reference to relevant treatment of the prior art.Whether the phenomenon of restarting or crashing appears such as, the electronic equipment of judging the circuit under test place, if, determine that then the virtual voltage tolerance limit of circuit under test does not meet the design load of voltage tolerant, otherwise, the design load of voltage tolerant met.For another example, whether the high level of signal that detects input at receiving end greater than VIH min, if, determine that then the virtual voltage tolerance limit of circuit under test meets the design load of voltage tolerant, otherwise, do not meet the design load of voltage tolerant.And for example, whether the low level of signal that detects input at receiving end less than VIL max, if, determine that then the virtual voltage tolerance limit of circuit under test meets the design load of voltage tolerant, otherwise, do not meet the design load of voltage tolerant.
The method and apparatus of the generation interference noise that the embodiment of the invention proposes and the method and system of test voltage tolerance limit go for any one electronic product, such as, Ethernet switch or router.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of programmed instruction, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (13)
1. produce the method for interference noise, it is characterized in that, comprising:
Frequency of operation according to circuit under test produces at least one road signal;
With at least one road signal plus that produces;
Signal after the addition is amplified, obtain interference noise, the magnitude of voltage of this interference noise equals the design load of the voltage tolerant of described circuit under test.
2. method according to claim 1 is characterized in that, described frequency of operation according to circuit under test produces at least one road signal and comprises:
According to the frequency of operation of described circuit under test, produce the signal of the each harmonic of at least one road work first-harmonic.
3. method according to claim 2 is characterized in that, the signal of the each harmonic of at least one road work of described generation first-harmonic comprises:
Produce the signal of the first harmonic of one tunnel work first-harmonic; Perhaps,
Produce the signal of the third harmonic of the second harmonic of three tunnel first harmonics that are respectively the work first-harmonic, work first-harmonic and work first-harmonic; Perhaps,
Produce the signal of the quintuple harmonics of the four-time harmonic of third harmonic, work first-harmonic of second harmonic, the work first-harmonic of five tunnel first harmonics that are respectively the work first-harmonic, work first-harmonic and work first-harmonic.
4. method according to claim 2, it is characterized in that, the signal expression of the each harmonic of described work first-harmonic is: F (xn)=an*sin (m*2* π * f*t), wherein, the n road signal of xn for producing, an is the attenuation coefficient of the n road signal of generation, m is an overtone order, and m and n are natural number, and an is the arbitrary value between 0～1, f is the frequency of operation of described circuit under test, and t is a time parameter.
5. according to the arbitrary described method of claim 1～4, it is characterized in that described voltage tolerant comprises high level voltage tolerance limit and low level voltage tolerance limit;
Described signal after the addition is amplified comprises: with the voltage of signals value of the smaller in the design load of the design load of described high level voltage tolerance limit and described low level voltage tolerance limit after divided by described addition, obtain enlargement factor; Amplify according to the signal of described enlargement factor after described addition.
6. according to the arbitrary described method of claim 1～4, it is characterized in that, after obtaining described interference noise, further comprise: described interference noise is carried out high pass and isolation processing.
7. produce the device of interference noise, it is characterized in that, comprising:
Signal generator module is used for producing at least one road signal according to the frequency of operation of circuit under test;
Summitor is used at least one road signal plus that will produce;
Amplifier is used for the signal after the addition is amplified, and obtains interference noise and output, and the magnitude of voltage of described interference noise equals the design load of the voltage tolerant of described circuit under test.
8. device according to claim 7 is characterized in that, described signal generator module comprises at least one road signal source, and each road signal source produces the signal of the each harmonic of work first-harmonic respectively according to the frequency of operation of described circuit under test.
9. device according to claim 8 is characterized in that, described signal generator module further comprises each signal attenuator that is connected to after each road signal source;
The signal expression that every signal source on the way produces is: F (xn)=sin (m*2* π * f*t), wherein, the n road signal of xn for producing, m is an overtone order, and m and n are natural number, and an is the arbitrary value between 0～1, f is the frequency of operation of described circuit under test, and t is a time parameter;
The signal attenuator that every signal source on the way connects, the signal that the received signal source produces and exports, this signal times is exported to described summitor after with attenuation coefficient, the expression formula of the signal of signal attenuator output is F (xn)=an*sin (m*2* π * f*t), wherein, an is the arbitrary value between 0～1 for the attenuation coefficient of the n road signal of generation.
10. according to the arbitrary described device of claim 7～9, it is characterized in that, described amplifier comprises the processing and amplifying module, with the voltage of signals value of the smaller in the design load of the design load of the high level voltage tolerance limit of described circuit under test and low level voltage tolerance limit after, obtain enlargement factor divided by described addition; Amplify according to the signal of described enlargement factor after described addition.
11. according to the arbitrary described device of claim 7～9, it is characterized in that this device further comprises: high pass and isolation module are used for the interference noise of described amplifier output is carried out high pass and isolation processing.
12. the method for test voltage tolerance limit is characterized in that, comprises utilizing the method for the arbitrary described generation interference noise of claim 1～6 to obtain interference noise;
The interference noise that obtains is applied in the circuit under test;
Whether the electronic equipment by judging described circuit under test place operate as normal, judges whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
13. the system of test voltage tolerance limit is characterized in that, comprises device, electronic equipment and pick-up unit as the arbitrary described generation interference noise of claim 7～11,
Described electronic equipment is used for receiving interference noise on the circuit under test of inside;
Described pick-up unit is used for judging by judging whether operate as normal of described electronic equipment whether the virtual voltage tolerance limit of described circuit under test meets the design load of voltage tolerant.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361610A (en) * | 2002-01-18 | 2002-07-31 | 张程霞 | Electromagnetic interference method of network |
| CN1792030A (en) * | 2003-03-26 | 2006-06-21 | 艾利森电话股份有限公司 | Noise generator |
| WO2007088987A1 (en) * | 2006-01-31 | 2007-08-09 | Institute Of National Colleges Of Technology, Japan | Noise generator, noise generating method and noise-applied device |
| CN101610118A (en) * | 2008-06-18 | 2009-12-23 | 深圳市格兰德林科技有限公司 | The method of measurement of characteristics of signal transmission passage and measurement mechanism |
-
2010
- 2010-09-14 CN CN2010102827631A patent/CN101963652A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361610A (en) * | 2002-01-18 | 2002-07-31 | 张程霞 | Electromagnetic interference method of network |
| CN1792030A (en) * | 2003-03-26 | 2006-06-21 | 艾利森电话股份有限公司 | Noise generator |
| WO2007088987A1 (en) * | 2006-01-31 | 2007-08-09 | Institute Of National Colleges Of Technology, Japan | Noise generator, noise generating method and noise-applied device |
| CN101610118A (en) * | 2008-06-18 | 2009-12-23 | 深圳市格兰德林科技有限公司 | The method of measurement of characteristics of signal transmission passage and measurement mechanism |
Non-Patent Citations (2)
| Title |
|---|
| 卓放等: "基于叠加原理实现的大功率可编程谐波电压源的研制", 《第三届电能质量（国际）研讨会论文集》 * |
| 武健等: "可编程电压质量扰动发生装置的研究", 《电力电子技术》 * |
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